Bipolar CMOS DMOS Process Research Articles

Optimization of Impact Ionization in Metal–Oxide–Semiconductor Field-Effect Transistors for Improvement of Breakdown Voltage and Specific On-Resistance

For the past few decades, metal–oxide–semiconductor field-effect transistors (MOSFETs) have been the most important application in IC circuits. In certain circuit applications, the breakdown voltage and specific on-resistance serve as key electrical parameters. This article introduces a readily accessible approach to enhance the source–drain breakdown voltage (BVDS) of MOSFETs based on the Bipolar-CMOS-DMOS (BCD) platform without extra costs. By attentively refining the process steps and intricacies of the doping procedures, the breakdown voltages of NMOS and PMOS experienced increments of 3.4 V and 4.6 V, translating to enhancements of 31.5% and 50.3%. Parallel simulations offer insightful mechanistic explanations through simulation tools, facilitating superior outcomes. This initiative lays significant groundwork for the advancement of a comprehensive BCD process development framework.

A 2.41 ppm/°C bandgap voltage reference with second‐order curvature compensation

SummaryA current‐mode (CM) bandgap voltage reference (BGR) with second‐order curvature compensation is presented in this paper. The proposed CM BGR offers a simple compensation structure that requires only six additional transistors compared with traditional BGR designs, making it an attractive solution for low temperature coefficient (TC) voltage references. Proportional to absolute temperature (PTAT) current digital‐to‐analog converters (DACs) are used to suppress the effect of process variation and device mismatch on TC. The compensation signal is generated using the voltage difference of two bipolar junction transistor (BJT) emitter–bases whose currents are the sum and difference of the PTAT current and the zero to absolute temperature (ZTAT) current, respectively. The proposed CM BGR is designed with 0.18‐μm BIPOLAR CMOS DMOS process. A TC is 2.41 ppm/°C over a wide temperature range of −40°C to 150°C. The linear sensitivity of the supply voltage from 1.2 to 2 V is 0.027%/V. With an active area of 0.0721 mm2, it consumes 68 μA at room temperature. The integrated output noise from 0.1 to 10 Hz is 21.9 μV.

A New Design Technique for a High-Speed and High dV/dt Immunity Floating-Voltage Level Shifter

This paper presents a high-speed level shifter with about 500 V/ns power supply slew immunity. In this designed structure, a narrow pulse-controlled current source is adapted to accelerate the voltage conversion and reduce the power consumption. A Fast-Slewing Circuit speeds up the operation of the level shifter based on the current comparison principle. Edge detection technology is used to filter the generated voltage noise and achieve high dV/dt immunity. The proposed level shifter simulated with the 0.18 μm BCD (bipolar-CMOS-DMOS) process shows fast responses with a typical delay of 1.49 ns and 500 V/ns dV/dt immunity in the 200 V high-voltage application, which only occupies a 0.022 mm2 active area with the 0.18 μm BCD process.

Design and verification of a hybrid electrostatic discharge model for Gate-Controlled silicon controlled rectifier

The DC breakdown characteristic of electrostatic discharge (ESD) protection device, which is an important indicator of its transparency and circuit compatibility, has received widespread attention. Currently, methods such as Verilog-A hardware description language, circuit-level SPICE simulation, and process-level device modeling cannot simultaneously achieve high accuracy, good convergence, and fast simulation speed. Therefore, in this paper, a hybrid ESD model based on Technology Computer Aided Design (TCAD) device-level simulation, Monte Carlo numerical modeling and Verilog-A behavioral modeling is proposed to characterize the ESD characteristics of gate-controlled silicon-controlled rectifier (GCSCR). A device-level model of GCSCR was established using TCAD, and the working mechanism was simulated. By extracting the electric field from TCAD and using the Monte Carlo modeling method, the DC characteristic of GCSCR was accurately characterized. In addition, the snapback characteristic of the device was successfully simulated by Verilog-A. The effectiveness of the above approaches was further verified based on the 0.18 μm standard BCD (Bipolar-CMOS-DMOS) process. Comparison results indicate that the hybrid model exhibits high simulation accuracy, good convergence and good universality and scalability, providing a simple and effective modeling solution for ESD devices of different structures and sizes.1This work is supported by the National Natural Science Foundation of China (Grant No. 62174052, 61827812), Hunan Science and Technology Department Huxiang High-level Talent Gathering Project (Grant No. 2019RS1037) and Innovation Project of Science and Technology Department of Hunan Province (Grant No. 2020GK2018).

A negative voltage generator with 4-stage configurable parallel switching for smart window film applications

ABSTRACT A negative voltage generator was developed that can be used in the drivers of smart window films (SWF), which have typical operating voltages of 8 to 10 V. It consists of four Negative Charge Pump (NCP) stages and a 4-phase non-overlapping Clock Generator (CG), where the 4 NCP stages are configurable by external digital signals. This generates a wide output voltage range necessary to control different SWF modes, such as opaque, transparent, and tinted modes. TSMC 0.18-m HV BCD (High-Voltage Bipolar-CMOS-DMOS) process was used to fabricate the proposed negative voltage generator on silicon. Measurement results demonstrate that at switching frequency (fsw) = 20 MHz, supplied voltage (VDD) = 4.5 V and Vin = GND, it generates a wide output voltage range of −3.9 to −14.0 V, achieving the widest voltage range among the prior works, which covers the required negative voltage range for SWF usage. The peak efficiency is measured on silicon to be 58.08% .

Triboelectric charge modulation to understand the electrification process in nanogenerators combined with an efficient power management system for IoT applications

Mechanical energy harvesting from ambient environment has been considered one of the promising technologies for developing autonomous self-powering units, sensors, and various other electronic applications. Triboelectric nanogenerators (TENGs) are one of the recent technologies gaining tremendous interest because of their ability to efficiently harvest ambient energy and convert it into electricity. The phenomenon of the triboelectrification effect in TENGs is not fully understood, along with extracting a maximum electrical output. Herein, we studied the electrification process between two triboelectric films by modulating their charge polarity. The charge polarity in the triboelectric film was modulated without any surface chemical functionalization. A TENG was fabricated to experimentally study the electrification process. Initially, the accepting/donating electrons of a triboelectric film were modulated using fluorine and oxygen atoms contained in polymers and operated against an oppositely charged triboelectric film. After optimizing the electrical output and conducting various stability investigations, the electrical output from the TENG was enhanced. Ultra-low power management integrated circuit (PMIC) implemented in a 180 nm high-voltage BCD (Bipolar CMOS DMOS) process was used. While matching the effective impedance of the TENGs, the PMIC achieves a total energy transfer efficiency of 81.5% utilizing a relatively low input power of 6.5 µW, showing state-of-the-art performance.

Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20-W/Ch Transmitter, and a 128 × 128 SPAD Receiver With SNR-Based Pixel Binning and Resolution Upscaling

An entire solid-state direct time-of-flight (dToF) light detection and ranging (LiDAR) system that incorporates innovations for both the transmitter (TX) and the receiver (RX) is presented in this work. For the illumination TX, we demonstrate solid-state channel addressability, which significantly reduces the transmit power and improves the ranging distance by dividing the field of view (FoV) into separately illuminated sub-regions. In the RX, we introduce single-photon avalanche diodes (SPADs) pixel binning, which enables reconfigurability of the sensor’s spatial resolution. Finally, we introduce a machine learning (ML) technique that enables this pixel-binned depth sensor to upscale its spatial resolution after training/inference fusion with the intensity image. The laser diode driver (LDD) chip is implemented in the 180-nm bipolar-CMOS-DMOS (BCD) process and is capable of pumping more than 8-A peak current into a multi-junction vertical-cavity surface-emitting laser (VCSEL) array, producing up to 20.3-W optical pulses under 12.5-V supply voltage. The sensor chip is also implemented in the 180-nm BCD process with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$128 \times 128$ </tex-math></inline-formula> SPAD array and reconfigurable pixel binning. Hardware and software co-optimization under low signal-to-noise ratio (SNR) conditions with ML-based spatial resolution upscaling is demonstrated.

A 6.78-MHz Digital Rectifier-Based Single-Stage Wireless Charger Using Digital-Controlled CC–CV Technique for Implantable Biomedical Devices

This letter presents a digital rectifier-based single-stage wireless charger. The proposed charger regulates charging current by adjusting the size of the power switch digitally, and the power loss of the switch can be reduced adaptively according to the charging condition. The power conversion efficiency is consequently improved significantly. Furthermore, high charging resolution and low output voltage ripple have been achieved by introducing a successive approximation method. Compared with the conventional analog-controlled charging technique, the proposed digital control can shorten the mode transition time, and thus avoid potential battery overcharging. In addition, a high-speed current sensor operating at 6.78 MHz is proposed to guarantee the sensing accuracy. The proposed single-stage wireless charger is fabricated in a 0.18-µm bipolar CMOS DMOS process with a die area of 0.56 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula> . The measured peak receiver efficiency of the proposed charger is 92.8%.

The integrated fast short-circuit protection technique with soft turn-off for SiC MOSFET

In this paper, the integrated fast short-circuit protection technique with soft turn-off is proposed for SiC (silicon carbide) MOSFET. Two short-circuit faults, HSF (hard switching fault) and FOF (flashover fault), can be judged by detecting EMI (electromagnetic interference) noises of SiC MOSFET. When there are short-circuit faults for SiC MOSFET, the soft turn-off is initiated to reduce EMI noises and protect SiC MOSFET. The proposed fast short-circuit protection technique is realized on the chip and is verified in a 0.18 μm BCD (Bipolar-CMOS-DMOS) process. Simulation results show that the proposed short-circuit protection has a fast response speed and then SiC MOSFET is turned off slowly when there are HSF and FOF. Therefore, the proposed fast short-circuit protection technique can be well applied for SiC MOSFETs, making SiC MOSFETs safely used in HV (high-voltage) and high current applications.

The ESD Characteristics of a pMOS-Triggered Bidirectional SCR in SOI BCD Technology

In this work, the electrostatic discharge (ESD) characteristics of a pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) that was fabricated in a 0.18 μm silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process, is investigated. The multi-snapback phenomenon was observed under the transmission line pulsing (TLP) test system. It was found that gate voltage and inserting shallow trench isolation (STI) can significantly affect the trigger voltage and holding voltage. The underlying physical mechanism related to the multi-snapback phenomenon and the effects of gate voltage on the critical parameters was investigated through the experimental results and the assistance of technology computer-aided design (TCAD) simulations. The adjustments of gate voltage and STI on the critical ESD parameters of the device provide an effective design idea for low-voltage ESD protection in the SOI BCD process.

Design Techniques of Sub-ns Level Shifters With Ultrahigh dV/dt Immunity for Various Wide-Bandgap Applications

In high-frequency gate drivers, especially for wide-bandgap applications, hundreds of voltages per nanosecond noise would be generated. Therefore, the sub-ns delay level shifter with high dV/dt immunity is necessary for signal conversion among different voltage domain areas. This article presents design techniques for the sub-ns delay level shifter with ultrahigh dV/dt immunity. The propagation delay of the proposed floating level shifter is dramatically reduced by utilizing the edge detection technique. In order to further improve the performance, auxiliary pull-up circuit, promoting delay matching, and self-calibration techniques are adopted, which make the proposed level shifters more suitable for high-frequency wide-bandgap applications. The level shifter is fabricated in a 0.5 μm bipolar CMOS DMOS (BCD) process, whose results demonstrate the final level shifter achieves zero static power consumption, a 0.024 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area, and dV/dt immunity up to 250 V/ns. The measurement results show that the sub-ns delay level shifter can be realized, and the minimum delay is only 664 ps at VSSH 25 V. Its figure of merit is just 0.044 ns/(μm × V), which is optimal among previous level shifters. The level shifters are also simulated at the 0.18 μm BCD process, and the propagation delay can be decreased by more than 60%.

3–12-V Wide Input Range Adaptive Delay Compensated Active Rectifier for 6.78-MHz Loosely Coupled Wireless Power Transfer System

This paper presents a wide input range active rectifier using a bipolar-CMOS-DMOS (BCD) process with a high voltage conversion ratio (VCR) and high power conversion efficiency (PCE). The proposed rectifier ensures safe and robust operation under large input voltage variations, which can be caused by changes in the magnetic coupling or loading conditions. It supports an input voltage range 3-12 V with the adaptive delay-compensated active operation of the power switches. An active signal clamper and voltage-time hybrid gate control circuit with two compensation loops was proposed for the optimal gate transition of low-side NMOS switches. For high-side PMOS switches, a fully integrated low-power-consuming high-side driver is proposed to replace the conventional high-side gate driving structure. The proposed active rectifier was fabricated through a TSMC 0.18 μm BCD process. The measurement results show that the proposed rectifier achieves stable and well-delay-compensated active operation, resulting in a high VCR and PCE with a wide output power range from 4.5 to 288 mW. Peak VCR and PCE of 96.8% and 93.7%, respectively, were achieved.

An Area-Efficient 10-Bit Buffer-Reused DAC for AMOLED Column Driver ICs

In this paper, we proposed an area-efficient 10-bit digital-to-analog converter (DAC) with buffer-reusing method to dramatically relief the severe area exploding issue in high-definition active-matrix organic light-emitting diode (AMOLED) driver integrated circuits (ICs). In our design, we implement the functionalities of a large number of switches and capacitors in conventional DAC by a compact internal buffer. Furthermore, we minimize the buffer capacity requirement by elaborately reusing the indispensable output buffer in the typical column driver. In this way, we can cut down nearly a half of the decoder-switches and simultaneously reduce the capacitor size from 8 C to 3 C without designing an intricate and power-consuming amplifier separately. A prototype 6-channel column driver employing the proposed buffer-reused DAC was fabricated by 0.35 μm 2P3M BCD (Bipolar, CMOS, DMOS) process and its effective layout area per channel is 0.0429 mm2, which is 42.8% smaller than that of the conventional 10-bit R-C DAC. Besides, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.514 LSB/0.631 LSB, respectively and the maximum value of inter-channel deviation voltage output (DVO) is 3.25 mV. The settling time within 5.6 μs is readily achieved under 1.5 kΩ-resistance and 100 pF-capacitance load. Measurement results indicate that the proposed buffer-reused DAC can successfully minimize the die area while maintaining other required performances.

A 600 V high voltage gate driver IC with excellent allowable negative VS bias capability for E-mode GaN power devices

In this paper, a 600 V high voltage gate driver IC with excellent allowable negative VS bias capability is proposed. In order to prevent the bootstrap capacitor from overcharging, a voltage signal from negative voltage sensor is utilized to control the charging path of it when the negative voltage in VS is detected. A bilevel isolated bootstrap circuit is utilized for the level shifter and the subsequent circuit, respectively. It guarantees the normally functions even when VS is lower than − VCC. The proposed 600 V gate driver IC is fabricated in 0.5 μm 600 V Bipolar–CMOS–DMOS process. Measured results show that its basic function is normal even when Vs = − 6 V at 5 V power supply voltage. The quiescent current when Vs = − 6 V is 40.63 μA, which is approximately same with it when VS = 0 V.

Avalanche Ruggedness Capability and Improvement of 5-V n-Channel Large-Array MOSFET in BCD Process

Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current ( ${I}_{\text {AV}}$ ) achieved from the modified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12 $000~\mu \text{m}$ .

A high-efficiency charge pump in BCD process for implantable medical devices * * Project supported by the National Natural Science Foundation of China (No. 61474092).

This paper presents a high-efficiency charge pump circuit composed of cascaded cross-coupled voltage doublers implemented in an isolated bipolar-CMOS-DMOS (BCD) technology for implantable medical devices. Taking advantage of the transistor structures in the isolated BCD process, the leakage currents caused by the parasitic PNP transistors in the cross-coupled PMOS serial switches are eliminated by simply connecting the inside substrate terminal to the isolation terminal of each PMOS transistor. The simple circuit structure leads to small parasitic capacitance in the voltage doubler, which in turn ensures high efficiency of the overall charge pump. The proposed charge pump with 5 cascaded voltage doublers is fabricated in a 0.35-μm isolated BCD process. Measurement results with 2-V power supply, 1-MHz driving clock frequency and 40-μA current load show that an efficiency of 72.6% is achieved, and the output voltage can be pumped to about 11.5 V at zero load current. The chip area of the charge pump is 1.6 × 0.35 mm2.

A Supply-Scalable Dual-Rate Dual-Mode DAC With an Adaptive Swing Control

This brief presents a dual-rate dual-mode power digital-to-analog converter (DAC) circuit to cover wide range of supply voltages. For various applications, it is designed to have dual conversion rate of Nyquist and oversampling in conventional current-steering DACs, and its output stage is implemented to support two kind modes of high-voltage and low-voltage. To achieve optimal performance of spurious-free dynamic range, the output swing is adaptively maximized depending on supply voltage levels. For feasibility of the proposed supply-scalable dual-rate dual-mode structure, a power DAC prototype is fabricated in a 0.18 mm bipolar CMOS DMOS process, and experimentally verified to provide normalized power efficiency of 81.5%.

Investigation of Unexpected Latchup Path Between HV-LDMOS and LV-CMOS in a 0.25- $\mu \text{m}$ 60-V/5-V BCD Technology

The latchup path which may potentially exist at the interface between high-voltage (HV) and low-voltage (LV) circuits in a HV bipolar-CMOS-DMOS (BCD) technology is investigated in this brief. Owing to multiple well structures used to realize the HV device in the BCD process, the expected latchup path in the test structure was hardly triggered. However, a parasitic silicon-controlled rectifier path featuring a very low holding voltage is found in the experimental silicon chip. Such a parasitic path is first reported in the literature. It may influence the electrostatic discharge robustness of CMOS IC products with the HV and LV circuits integrated together. Thus, the layout rules at the HV and LV interface should be carefully defined to avoid the occurrence of an unexpected parasitic path.

래치-업 면역과 높은 감내 특성을 가지는 LIGBT 기반 ESD 보호회로에 대한 연구

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

A Multiphase Buck Converter With a Rotating Phase-Shedding Scheme For Efficient Light-Load Control

Mobile devices need to minimize their power consumption in order to maximize battery runtime, except during short extremely busy periods. This requirement makes dc-dc converters usually operate in standby mode or under light-load conditions. Therefore, implementation of an efficient regulation scheme under a light load is a key aspect of dc-dc converter design. This paper presents a multiphase buck converter with a rotating phase-shedding scheme for efficient light-load control. The converter includes four phases operating in an interleaved manner in order to supply high current with low output ripple. The multiphase converter implements a rotating phase-shedding scheme to distribute the switching activity concentrated on a single phase, resulting in a distribution of the aging effects among the phases instead of a single phase. The proposed multiphase buck converter was fabricated using a 0.18 μm bipolar CMOS DMOS process. The supply voltage ranges from 2.7 V to 5 V, and the maximum allowable output current is 4.5 A.