Bipolar Transistor Power Research Articles

A fully integrated GaAs HBT power amplifier for WLAN 802.11ax applications

AbstractA fully integrated gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) power amplifier (PA) for wireless local area network 802.11ax applications is presented in this paper. The structure consists of two‐stage power cells. To satisfy the high linearity requirements of IEEE 802.11ax, we analyzed the distortion of amplitude‐to‐amplitude and amplitude‐to‐phase. Due to the thermal and voltage sensitivity of GaAs HBT, an adaptive bias circuit is designed to ensure linearity. Moreover, an efficient passive output matching network is designed by analyzing the efficiency of the passive network. The design electromagnetic structure is fabricated in a 2‐μm GaAs HBT process. Under continuous wave testing, the output power reaches 27.2 dBm and the maximum efficiency of 28% at 2.4 GHz. Under the excitation of a 40 MHz 1024‐quadratic amplitude modulation signal, the output power meeting error vector magnitude of −35 dB reaches 16.8–17.2 dBm from 2.4 to 2.5 GHz.

A fast-switching low-loss field-stop IGBT with dual control gate of SIPOS material

A fast-switching low-loss field-stop insulated gate bipolar transistor with a dual control gate (DIGBT) of a semi-insulating polycrytalline silicon (SIPOS) material is proposed in this paper. Because the SIPOS has uniform high resistance, it has an approximate linear electric potential distribution. When DIGBT conducts, the higher electric potential on SIPOS causes the P-type drift region (P-drift) to generate an inversion layer of electrons, adjusting the number of carriers and making the generation of non-equilibrium carriers no longer dependent on the doping concentration in P-drift (Nd) but on the electric potential distribution on SIPOS. Therefore, it can solve the contradiction among the breakdown voltage, forward voltage drop [VCE(sat)], turn-off time (toff), and turn-off loss (Eoff) caused by the Nd. Through Technology Computer Aided Design (TCAD) simulation, the VCE(sat) of DIGBT is 30.6% lower than that of SJFS IGBT. Meanwhile, DIGBT reduces the toff by 62.8% while reducing the Eoff by 83.0% compared to SJFS IGBT. In addition, the static latch-up I–V and the forward biased safe operating area of the DIGBT have been significantly improved. This paper adjusts the number of carriers through the characteristics of SIPOS material, enabling the above-mentioned physical phenomena to be applied in insulated gate bipolar transistor power devices and achieving device performance breakthroughs.

Critical solder joint in insulated gate bipolar transistors (IGBT) power module for improved mechanical reliability

This investigation identifies the critical solder joint in a typical Insulated Gate Bipolar Transistor (IGBT) module and provided new knowledge on how operating thermal loads degrade IGBT-attach, Diode-attach, and Substrate solder joints in the device. SolidWorks software is used to create three realistic 3-D Finite Element (FE) models of the typical IGBT module used in this investigation. In-service operating power and IEC 60068–2-14 thermal cycles are implemented in ANSYS mechanical package to simulate the response of the three solder joints in the FE models to the load cycles. The solder in the joints is lead-free alloy of 96.5% tin, 3% silver, and 0.5% copper (SAC305) composition. The SAC305 material properties are modelled as time and temperature dependent with Anand's visco-plastic model employed as the constitutive model. Results show that the key degradation mechanism of solder joints in IGBT module are stress, plastic strain, and strain energy magnitudes. Accumulated plastic strain in the joints is found the predominant damage factor. Critical solder joint in the module depends on the load cycle the device experiences. IGBT-attach solder joint is critical in active power load cycle. Substrate solder joint degraded most in passive thermal cum combined passive thermal and active power load cycles.

Thermal and electrical evaluation of insulated gate bipolar transistor (IGBT) power modules

The thermal reliability of two different high-power insulated gate bipolar transistor (IGBT) modules was studied under both conduction and switching regimes by experimental and numerical approaches. Indeed, the reliability of semiconductor devices is tightly linked to the junction temperatures reached in the IGBT, which is a function of the diode chips present in such devices and its operating condition. However, measurements of the semiconductor temperatures are often difficult to be done, thus requiring modeling and simulation tools to accurately evaluate the instantaneous temperature under different thermal loads. For this reason, a transient 3D heat transfer numerical model of two different IGBT power devices was proposed using the Finite Element Method, assuming that heat is dissipated on the IGBT by natural convection and radiation. These simulations were validated with experimental measurements, obtained through infrared thermography, performed for the IGBT modules either opened or enclosed, varying the heat source, the module orientation and under conduction or switching regime. For the switching regime, power losses due to the gate-closing and gate-opening transitions between conducting and non-conducting states were taken into consideration. The heat losses were modeled assuming the time-dependent heat dissipation obtained by previous electrical simulations, and it was compared with time-averaged heat source solutions. Results showed that averaging the heat source can significantly reduce the computational time, allowing quick design explorations. Overall, the numerical model led to deviations of less than 16% over the transient heating and at steady-state. Finally, the impact of a heat sink attached to the IGBT was studied, demonstrating that the proposed model can be used for accurate and quick investigations of potential failures and for the development of more efficient IGBT devices.

DOE optimization of a liquid cold plate used in a thermal management system for power converters in the railway sector through 3D CFD analysis

The thermal management system for power electronics is becoming a key factor in order to guarantee optimal working conditions, efficiency and safety of those components. In the field of liquid-cooled power electronics, the design of an optimal liquid cold plate (LCP) is fundamental to increase the heat transfer, minimizing the maximum temperature and the pressure drop. This work presents an optimization procedure of a finned extruded profile of an LCP for insulated gate bipolar transistor (IGBT) power module, for railway propulsion. The optimization has been performed through DOE, by considering different values of several control factors (shape of the fin, length of the fin, pitch between the channels created by the fins), in order to minimize the LCP maximum temperature and the pressure drop between inlet and outlet. The combination of different values of control factors results in 18 prototypes, which have been compared using three-dimensional CFD simulations, performed in Ansys Fluent environment. The influence of parameters variation on the objective functions (i.e. maximum temperature of the liquid cold plate and pressure drop) has been verified.

Bond wire lift-off detection by gate voltage waveform in IGBT turn-off process enhanced by digital gate control

This paper presents a new detection method of bond wire lift-off in Insulated Gate Bipolar Transistor (IGBT) power module. The bond wire lift-off is a major failure mode in power cycle degradation of the IGBT module, and many monitoring methods have been proposed and demonstrated for safety operation of power electronics systems in the previous works. In this study, we focus on the gate voltage waveform as an indicator to detect wire-lift for a simple and straightforward detection method. Due to the increase in parasitic inductance caused by bond wire lift-off, the turn-off switching waveform becomes modulated. The digital gate control (DGC) was employed to control the switching behavior to obtain precision for low-noise and high-performance. Furthermore, the DGC 2-step vector control (2-sVC) can enhance the sensitivity of bond wire lift-off failure detection by gate voltage waveform change. As feature quantities, the gate voltage spike peak, its amplitude and the timing shift were measured at various operating conditions. The DGC obtained larger feature quantities compared with conventional gate control. In particular, high-current conditions were found to be more favorable for achieving high sensitivity due to the high die/dt. From these results, the DGC is effective to achieve both the high sensitivity to detect bond wire lift-off by gate voltage waveform and maintaining the best switching performance.

Thermal Performance Optimization of Integrated Microchannel Cooling Plate for IGBT Power Module.

In high-integration electronic components, the insulated-gate bipolar transistor (IGBT) power module has a high working temperature, which requires reasonable thermal analysis and a cooling process to improve the reliability of the IGBT module. This paper presents an investigation into the heat dissipation of the integrated microchannel cooling plate in the silicon carbide IGBT power module and reports the impact of the BL series micropump on the efficiency of the cooling plate. The IGBT power module was first simplified as an equivalent-mass block with a mass of 62.64 g, a volume of 15.27 cm3, a density of 4.10 g/cm3, and a specific heat capacity of 512.53 J/(kg·K), through an equivalent method. Then, the thermal performance of the microchannel cooling plate with a main channel and a secondary channel was analyzed and the design of experiment (DOE) method was used to provide three factors and three levels of orthogonal simulation experiments. The three factors included microchannel width, number of secondary inlets, and inlet diameter. The results show that the microchannel cooling plate significantly reduces the temperature of IGBT chips and, as the microchannel width, number of secondary inlets, and inlet diameter increase, the junction temperature of chips gradually decreases. The optimal structure of the cooling plate is a microchannel width of 0.58 mm, 13 secondary inlets, and an inlet diameter of 3.8 mm, and the chip-junction temperature of this structure is decreased from 677 °C to 77.7 °C. In addition, the BL series micropump was connected to the inlet of the cooling plate and the thermal performance of the microchannel cooling plate with a micropump was analyzed. The micropump increases the frictional resistance of fluid flow, resulting in an increase in chip-junction temperature to 110 °C. This work demonstrates the impact of micropumps on the heat dissipation of cooling plates and provides a foundation for the design of cooling plates for IGBT power modules.

Enhancement of turn-off gate voltage waveform change by digital gate control for bond wire lift-off detection in IGBT module

The bond wire lift-off is the one of main failures for insulated gate bipolar transistors (IGBT) power modules. The wire lift-off increases parasitic inductance LeE in the module and the gate voltage Vge waveform is modulated by LeE·dIe/dt. Therefore, the Vge waveform has the potential for an indicator of condition monitoring. The Digital gate control (DGC) can control switching behavior precisely for low-loss and low-noise switching. It is also effective for sensitivity enhancement of Vge waveform changed by the wire lift-off. This paper reports how the DGC 2-step vector control (2-sVC) can improve the wire lift-off failure detection sensitivity by Vge waveform. The experiment results showed that the Vge spike was generated by LeE·dIe/dt at the turn-off switching and the spike generation timing depended on the wire number. The DGC obtained the larger timing-shift Δtwire and the amplitude ΔVge-surge than those at the conventional gate control. In addition, the best vector condition improved the trade-off between turn-off loss and collector voltage overshoot compared with the conventional gate control. From these results, the DGC is effective to enhance the sensitivity of bond wire lift-off detection by Vge waveform maintaining the best switching performance.

The development status and future of the field effect transistor

FET is short for Field Effect Transistor (FET). There are two main types: Junction FET-JFET and metal-oxideSemiconductor FETs (MOS-FETs). Conduction by the majority of carriers, also known as a monopolar transistor. Itis part of voltage controlling semiconductor device. With the advantages of high input resistance (107 ~ 1015 Ω), lownoise, low power consumption, extensive dynamic range, easy integration, no secondary breakdown phenomenon, andwide safe working area, it has become a strong competitor of bipolar transistors and power transistors

The dependence of proton energy on the parametric degradation in silicon bipolar junction transistors

The effects of high total dose proton irradiation on the reliability of silicon NPN rf power bipolar junction transistor (BJT) were examined by subjecting to 1, 3, and 5 MeV protons in the dose range from 100 Krad to 100 Mrad. The electrical characteristics such as Gummel characteristics (IB, IC-VBE), excess base current (ΔIB = IBpost – IBpre), current gain (hFE), and output characteristics (IC-VCE), built-in potential (Vbi) and the effective doping concentration (Nd) were studied before and after irradiation. SRIM simulation was conducted to understand the range and energy loss of protons in the BJT structure. SRIM and experimental results infer that the proton irradiation at lower energy (1 MeV) was found to degrade the current–voltage(I-V) and capacitance–voltage (C-V) characteristics more severely than higher-energy (3 and 5 MeV) proton irradiation. Thermal annealing on irradiated devices was also conducted to study the parametric recovery of irradiated devices.

High-Efficiency 200-GHz Neutralized Common-Base Power Amplifiers in 250-nm InP HBT

The analysis, design, and measurement of two Indium Phosphide (InP) heterojunction bipolar transistor (HBT) power amplifier (PA) designs are presented at G-band with record efficiency. A pseudo-differential common-base (CB) stage with neutralization capacitors and low-loss coupled-line balun (CLB) improve the gain and reduce matching loss. A single-stage design achieves 8.3 to 12.7-dBm output power and 7.7 to 17.3% power-added efficiency (PAE) over 180 to 220 GHz. The use of compact baluns allows the design to occupy only 0.011mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with power density of 1.69 W/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A 3-stage, 4-way power-combined PA delivers 16.6 to 19.7-dBm output power and 6.5 to 13% PAE over 185 to 210 GHz.

High Linear and Temperature Insensitive GaAs Power Amplifier Operating at 3.3–3.6 GHz Using a Multi-Feedback Branch Bias Circuit

This letter describes a design of a 3.3–3.6-GHz GaAs heterojunction bipolar transistor (HBT) power amplifier (PA) with high linearity and temperature insensitivity for the fifth-generation (5G) of new radios (NRs). By involving a multi-feedback branches bias circuit, the voltage at the feedback node of the bias circuit can achieve dynamic self-tuning to stabilize the base voltage as the amplifier’s input power grows and stabilize the bias current as the temperature increases as well. A three-stage common source structure PA in the form of a monolithic microwave integrated circuit (MMIC) is designed using a multi-feedback branch bias circuit with a size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times1.2$ </tex-math></inline-formula> mm. Measured with continuous wave (CW) signals, the output 1-dB compression point at 3.3–3.6 GHz is 34 dBm. The linearity of the PA is also evaluated using a 5G-NR 100-MHz 64-quadratic-amplitude modulated (QAM)-orthogonal frequency division multiplexing (OFDM) signal with a 7-dB peak-to-average-power ratio (PAPR). The proposed PA achieves an adjacent channel power ratio (ACPR) less than −49.5 dBc at an average power of 28 dBm with a power-added efficiency (PAE) of 20% without the use of digital pre-distortion (DPD). In the temperature range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 40\,\,^{\circ }\text{C}$ </tex-math></inline-formula> to 120 °C, the variance of bias current, small signal gain, PAE, output power at 1-dB compression point (OP1dB), and ACPR is relatively minor. This design is ideally suited for 5G communication systems due to its high linearity and temperature insensitivity.

Temperature distribution in multichip IGBT module and its impact on collector current sharing

Multichip Insulated Gate Bipolar Transistor (IGBT) power modules are widely used in high power applications. However, the parallel connection of IGBT chips results in an inhomogeneous temperature/current distribution. In this paper, a thermographic camera is used to capture the temperature distribution of an opened Infineon IGBT module FF600R17ME4 where each IGBT switch has three IGBT chips. The influence of temperature distribution on collector current sharing is then examined in both healthy conditions and bond wire lift-off scenarios. In this research, the critical temperature distribution is demonstrated experimentally at both chip and switch levels. The experimental results reveal that there are, depending on the collector current, 8 °C to 60 °C temperature difference at the chip level and 2 °C to 10 °C maximum temperature variation at the switch level. The severe temperature distribution impacts the collector current sharing less than 1 % variation under healthy conditions and 0.507 % at IC = 240 A upon the first bond wire lift-off. Other findings are that during homogeneous temperature distribution current densities are nearly similar per chip and less dependent on chip temperatures. Findings of this research have the potential to influence multichip Insulated Gate Bipolar Transistor (mIGBT) layout design. For example, having investigated the current density distribution at different operating points, it is recommended to increase the number of bond wires by 11 % for the chip placed in the middle for this particular module in order to increase reliability. Potential future research areas have also been identified.

A 27-MHz frequency shift keying wireless system resilient to in-band interference for wireless sensing applications

&lt;span lang="EN-US"&gt;A 27-MHz wireless system with binary frequency shift keying (BFSK) modulation at 400-kHz is reported. The receiver has been designed to handle in-band interference corrupting the BFSK signal with the use of complex filters and amplitude comparison method. The BFSK modulation is carried out with a voltage-controlled oscillator before up-converting with a 27-MHz local oscillator. The bipolar junction transistors (BJT-based) power amplifier with 30% efficiency pumps 220 mW into a spiral antenna. The inductive-degenerated low-noise amplifier with a voltage of more than 30 dB amplifies an incoming signal before feeding into a mixer for complex direct down conversion. With deliberate Gaussian interference injection, the minimum ratios between the signal with interference and the interference only at the distance of 2.5, 10 and 15 m are 3.3, 8.5 and 11.5 dB, respectively at a maximum data rate of 20 kbps. Without any interference included, the system can achieve a data rate of 40 kbps at the maximum transmission distance of 15 m. Conceptually agreed with the presented bit-error-rate (BER) analysis, the BER measurements with Gaussian and single-tone/two-tone in-band interferences also confirm superiority offered by the amplitude comparison method where the signal-to-noise ratio is at 1 dB for BER=10&lt;sup&gt;-3&lt;/sup&gt; at 10 kbps (10 dB better than the phase detection counterpart).&lt;/span&gt;

Fault Recognition of Multilevel Inverter Using Artificial Neural Network Approach

This paper focuses on the development of a diagnostic tool for detecting insulated gate bipolar transistor power electronic switch flaws caused by both open and short circuit faults in multi-level inverter time-frequency output voltage specifications. High-resolution laboratory virtual instrument engineering workbench software testing tool with a sample rate data collection system, as well as specialized signal processing and soft computing technologies, are used in this proposed method. On a single-phase cascaded H-bridge multilevel inverter, simulation and experimental investigations of both open and short issues of the insulated gate bipolar transistor components are performed out. In all conceivable switch issues, the output voltage signals are evaluated for different modulation index values. Fast fourier transform and discrete wavelet transform methods are used to investigate the frequency domain properties of output voltage signals. In the artificial neural network, the back propagation training technique was employed, and the generated neural parameter values were used in the Laboratory Virtual Instrumentation Engineering Workbench real-time fault diagnosis model.

Online Junction Temperature Measurement of Double-sided Cooling IGBT Power Module through On-state Voltage with High Current

The aim of this study is to achieve online monitoring of the junction temperature of double-sided-cooling insulated gate bipolar transistor (IGBT) power modules by using the on-state voltage under a high current to maximize the utilization of IGBT power chips. Online junction temperature measurement plays an important role in improving the reliability of the inverter with IGBT, increasing the power density of the motor controller of electric vehicles, and reducing the cost of electric vehicles.

Aluminium corrosion in power semiconductor devices

In this study, insulated gate bipolar transistor (IGBT) power modules were exposed to high voltage, high humidity, high temperature and reverse bias (HV-H3TRB) conditions until end-of-life (EoL). The limited lifetime of power semiconductor devices when used in demanding applications involving high relative humidity during operation is commonly reported to be associated with the design of the edge termination in power transistor or diode chips. A physics-of-failure (PoF) oriented methodology was adopted in failure analysis, including using lock-in thermography (LiT) for failure localisation and using an advanced microwave-induced plasma (MIP) decapsulation technique for the selective etching of the edge termination polyimide passivation film. A focused ion beam (FIB) was utilised to create a cross-section of the samples for both scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX) analysis. The evidence gathered using the physics-of-failure methodology were compared with the results from advanced statistical analysis of the failure distributions in Weibull plots, including comparison of α and β parameters. This analysis revealed correlation with the Weibull distributions and the results from the physics-of-failure. Aluminium corrosion products were systematically observed on guard rings (GR) and field plates (FP) showing that the migration of these corrosion products forming an electrical path between the guard rings that seems to be a major failure mechanism in high humidity environments when reverse bias voltage is applied.

Predicting the power module cumulative damage degree in new energy vehicle: Improved Manson model

The cumulative fatigue damage degree is a core parameter used to evaluate the service life of an IGBT module and accurately calculate the cumulative fatigue damage degree. This study is necessary to accurately evaluate the cumulative fatigue damage of insulated gate bipolar transistor (IGBT) power module in drivetrain system to improve the reliability of stable operation of electric vehicles. Especially, the improved Manson model calculates the cumulative fatigue damage of IGBT more accurately. The reliability of IGBT module is effectively evaluated to make the effective operation and maintenance strategy of drivetrain system in electric vehicles, and improving the reliability of electric vehicles. The limitations of the Manson model were considered, and an improved Manson model was proposed and the spectrum of temperature load was obtained by the rain-flow counting method of junction temperature-time curve. The cumulative fatigue damage of IGBT module was calculated using the improved Manson and Miner models. The results revealed that in situations 1 and 2, the total damage calculated by the improved Manson model was 230.25% and 8.39% higher than that of the Miner model. The working period was segmented. The results indicate that the damage degree calculated with non-segmentation was greater than that with segmentation. The total damage calculated by the improved Manson and Miner model was closer to the true value than that calculated by the Miner model.

A Multi-Source Co-Simulation Method for the Thermal Stability of GaAs Sub-6G Power Amplifier with Adjustable Bias Current

In this paper, the thermal stability of GaAs heterojunction bipolar transistor (HBT) power amplifier (PA) in a sub-6G band has been improved by a multi-source co-simulation method. To reduce the parameter errors caused by the variations of thermal resistances, a co-simulation method for the multiple heat sources of fully-integrated PA is proposed. Specifically, an adjustable bias circuit is applied on the PA for temperature compensation using a zero-to-absolute-temperature (ZTAT) current. To verify the proposed method, a sub-6G PA is realized in the GaAs HBT process. The experimental results show that the variations in power added efficiency and output power is stabilized due to the 3.5% error ZTAT current. The errors between simulation and measurement are reduced from 6% to 1%. According to the thermal factor defined in co-simulation, the working temperature decreases 10 °C, while the area only increases 27%. The above results prove that that thermal stability and the simulation reliability can be co-designed with the minimal area cost.

Design and Development of a Measurement System Dedicated to Estimate the Junction Temperature of Insulated Gate Bipolar Transistor Modules

The damage state estimation of an Insulated Gate Bipolar Transistor (IGBT) power module requires the measurement of the junction temperature (Tj) of the active region. However, the accurate measurement of the temperature Tj is not simple to achieve and several methods have been developed to improve the accuracy of Tj measurements. Some of the well-known methods include the use of thermo-sensitive electrical parameters (TSEP). Although the TSEP methods do not provide access to the thermal mapping of the IGBT surface, they have the advantage of not affecting the physical integrity of the module. This paper aims to present a reliable programmable measurement system dedicated to estimating with great accuracy the thermal performance of the IGBT power module on the microsecond scale using the TSEP method. The advantage of this system is to provide full control of the injection of the power current and allows quick measurements of the cooling curve just after the injection of the heating power in the chip. The junction temperature calculated from the TSEP was found to be equal to 97.5 °C, which was confirmed by using the thermal camera. The accuracy of the proposed technique was found to be less than 2%. A comparison with the thermal Resistor-Capacitor (RC) network model is also carried out in this work. Experimental results demonstrate that the designed system is high efficiency and can, therefore, be used by scientific researchers and industrial engineers for predictive maintenance to monitor the performance state of IGBT power modules, which will reduce the probability of its failure or degradation.