Current Gain Of Bipolar Transistors Research Articles

Ionizing radiation influence on parameters of analog components of the master slice array МН2ХА030

Structured arrays and master slice arrays are often used to reduce cost, design and test time for radiation hardened analog integrated circuits. One of such master slice arrays is МН2ХА030, which uses bipolar and junction field-effect transistors. The purpose of this article is to estimate the effect of ionizing radiation on the parameters of the operational amplifier OAmp2 and comparators ADComp1 and ADComp3 created on the МН2ХА030 master slice array. Еhe results of measurements of analog components after exposure to 60Co gamma quanta with an absorbed dose of up to 700 krad and a fast electron fluence of up to 2.9·1015 el./cm2 with an energy of 6 MeV are presented. The OAmp2 operational amplifier provides a satisfactory level of basic static parameters (input current, offset voltage, voltage gain) at a fast electron fluence of up to 3.7·1014 el./cm2 with an energy of 6 MeV. There are a decrease in the voltage gain and an increase in the offset voltage at electron fluence of greater than 1015 el./cm2. The latter can be caused by a decrease in the efficiency of the common-mode signal feedback integrated into operational amplifier with a significant drop in current gain of bipolar transistors. All considered analog components provide a satisfactory level of basic static parameters at a fast electron fluence of up to 3.7·1014 el./cm2 with an energy of 6 MeV and an absorbed dose of 60Co gamma quanta of at least 700 krad. It is assumed that resistance of OAmp2, ADComp1, ADComp3 to the action of 60Co gamma quanta is significantly higher and requires further research. The developed analog components can be used in signal reading devices required in front-end of sensors for space instrumentation and nuclear electronics.

Characterization and modeling the effect of temperature on power HBTs InGaP/GaAs

The variation and stability of HBT’s parameters at different temperatures are important for utilizing these devices in high-power integrated circuits. The temperature dependence of the DC current gain of bipolar transistors, as a key device parameter, has been extensively investigated. A major issue of the power HBT’s is that the current gain is decreased with junction temperature due to self-heating effect. Hence, how to stabilize the DC current gain and RF performances is important issue to develop the power HBTs. This work describes the DC and high-frequency temperature dependence of InGaP/GaAs HBT’s. The substrate temperature (T) was varied from 25 to 150°C. The static and dynamic performances of the HBT are degraded at high temperature, due to the reduced of carrier mobility with increasing temperature. The current gain (β) decreases at high temperatures; from 140 to 127 at 25 to 150°C, while the decreases in the peak Ft and Fmax are observed from about 110 GHz to 68 GHz and from 165 GHz to 53 GHz respectively in the temperature range of 25 to 150°C.

Degradation of bipolar transistors at high doses obtained at elevated temperature applied during gamma-irradiation

The paper presents investigation results of radiation-induced change in current gain of bipolar transistors at elevated temperature applied during gamma-irradiation with high levels of dose. The regularities obtained during irradiation at elevated temperature coincide qualitatively with the data obtained previously during irradiation at low dose rate. Results of simulation confirm the possibility of applying of developed model of radiation induced degradation of bipolar transistor for irradiation at different temperatures.

Radiation Degradation of Bipolar Transistor Current Gain

Radiation Degradation of Bipolar Transistor Current Gain

A high precision high PSRR bandgap reference with thermal hysteresis protection

To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits, a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations. In addition, an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed. Based on the CSMC 0.5 μm 20 V BCD process, the designed circuit is implemented; the active die area is 0.17 × 0.20 mm2. Simulation and testing results show that the temperature coefficient is 13.7ppm/K with temperature ranging from −40 to 150 °C, the power supply rejection ratio is −98.2 dB, the line regulation is 0.3 mV/V, and the power consumption is only 0.38 mW. The proposed bandgap voltage reference has good characteristics such as small area, low power consumption, good temperature stability, high power supply rejection ratio, as well as low line regulation. This circuit can effectively prevent thermal oscillation and is suitable for on-chip voltage reference in high precision analog, digital and mixed systems.

A simulation model for the density of states and for incomplete ionization in crystalline silicon. II. Investigation of Si:As and Si:B and usage in device simulation

Building on Part I of this paper [Altermatt et al., J. Appl. Phys. 100, 113714 (2006)], the parametrization of the density of states and of incomplete ionization (ii) is extended to arsenic- and boron-doped crystalline silicon. The amount of ii is significantly larger in Si:As than in Si:P. Boron and phosphorus cause a similar amount of ii although the boron energy level has a distinctly different behavior as a function of dopant density than the phosphorus level. This is so because the boron ground state is fourfold degenerate, while the phosphorus ground state is twofold degenerate. Finally, equations of ii are derived that are suitable for implementation in device simulators. Simulations demonstrate that ii increases the current gain of bipolar transistors by up to 25% and that it decreases the open-circuit voltage of thin-film solar cells by up to 10mV. The simulation model therefore improves the predictive capabilities of device modeling of p-n-junction devices.

Metal-sulfur-based air-stable passivation of GaAs with very low surface-state densities

An air-stable electronic surface passivation for GaAs and other III–V compound semiconductors that employs sulfur and a suitable metal ion, e.g., Zn, and that is robust towards plasma dielectric deposition has been developed. Initial improvements in photoluminescence are twice that of S-only treatments and have been preserved for >11 months with SiOxNy dielectric encapsulation. Photoluminescence and x-ray photoelectron spectroscopies indicate that the passivation consists of two major components with one being stable for >2 years in air. This process improves heterojunction bipolar transistor current gain for both large and small area devices.

Measurement of dose rate dependence of radiation induced damage to the current gain in bipolar transistors

We report the study of radiation induced change in the current gain of bipolar transistors for three different gamma dose rates. The dose rates differed by a factor of 60 with the lowest close to that anticipated for the LHC, and the highest at a rate we have been routinely using for radiation damage tests. The maximum dose attained was 200 kRad, which is high enough to compare with other measurements. The importance of annealing to high dose rate data is demonstrated.

An accurate charge control approach for modeling excess phase shift in the base region of bipolar transistors

The conventional charge control approach is extended to enable the accurate determination of excess phase shift in the ac common-emitter current gain of bipolar transistors arising from distributed stored minority carrier charge in the neutral base. Generalized expressions, valid for transistors with arbitrary impurity profiles and position-dependent transport parameters, are presented from which the excess phase shift can be determined solely from device structure and process data. The ac model parameters which result from the extended charge control approach are used in an existing high-frequency compact nonquasi-static bipolar model which is suitable for SPICE simulation.

Repair of Plasma Etch Related Gate Perimeter Damage Using Low Temperature Oxidation

Plasma etching of polysilicon gate electrodes results in a degraded breakdown voltage for high perimeter, comb capacitor structures formed over p‐silicon. p‐Well structures with other geometric configurations and all n‐well capacitor structures do not show this degradation. A low temperature oxidation during temperature ramping in the source/drain implant anneal can repair the gate dielectric damage, increasing the comb capacitor breakdown voltage by up to 1.5 MV/cm. Polysilicon reoxidation treatments after gate etching can also restore comb capacitor breakdown voltage, but their application is limited by the need to avoid metal oxide semiconductor field effect transistor short channel degradation and undesired bipolar transistor current gain increase.

Effect of rapid epitaxy in in situ phosphorus-doped polysilicon emitter on current-gain of bipolar transistors

The effect of rapid solid-phase epitaxy (SPE) on the current gain of in situ phosphorus-doped polysilicon-emitter (IDP) transistors has been evaluated, IDP technology is used to produce very-high-speed small-emitter bipolar transistors, which have very high current gain due to their hetero-emitter-like characteristics. The IDP film is deposited on a clean poly/mono-silicon surface, followed by rapid thermal annealing (RTA). The poly/mono interface was analyzed and the lattice image was observed by high-resolution transmission electron microscopy (TEM). The majority of the IDP transistors had poly/mono-silicon interfacial hetero-emitter-like characteristics and thus had high current gain. The remaining transistors, however, did not exhibit hetero-emitter-like characteristics due to SPE and thus the current gain was reduced. These results are well explained using an interfacial residual-stress model: rapid epitaxy occurs when the amorphous silicon film is annealed by RTA, which eliminates the interfacial residual stress and in turn the hetero-emitter-like characteristics.

Degradation of bipolar transistor current gain by hot holes during reverse emitter-base bias stress

Experimental evidences are given which demonstrate that degradation of the common-emitter forward current gain h/sub FE/ of submicron silicon npn bipolar transistors at low reverse emitter-base junction applied voltage is caused by primary hot holes of the n/sup +//p emitter tunneling current rather than secondary hot electrons generated by the hot holes or thermally-generated hot electrons. Experiments also showed similar kinetic energy dependence of the generation rate of oxide/silicon interface traps by primary hot electrons and primary hot holes. Significant h/sub FE/ degradation was observed at stress voltages less than 2.4 V.

Si band-gap shrinkage caused by local strain at Si/SiO2 edge

This letter describes Si band-gap shrinkage caused by local strain at the local oxidation of silicon (LOCOS) edge. The local band-gap shrinkage of 20–30 meV is shown to exist at the LOCOS edge by measuring the forward-biased junction current of square n+ regions on a p substrate for various junction sizes. The junction current is observed to be proportional to the peripheral length rather than the area of the square n+ regions at liquid-nitrogen temperatures. It is also likely that the shrinkage would degrade the current gain of bipolar transistors, especially at low temperatures.

The enhancement of gate-induced-drain-leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain beta

An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 mu m SOI devices. This can pose severe constraints in future 0.1 mu m SOI device design. A novel technique was developed based on this mechanism to measure the lateral bipolar transistor current gain beta of SOI devices without using a body contact.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Emitter efficiency, transit times and current gain of bipolar transistors

A generalized theory of emitter efficiency, transit times, and current gain of bipolar transistors have been developed by taking non-uniform doping and carrier concentrations, bandgap narrowing, mobility, diffusion coefficient, bulk and surface recombinations, and others into consideration. The final expressions exhibit forms identical to the traditional ones for non-degenerate semiconductors with position-independent device parameters. Numerical calculations carried out on a simpler model resulting from the use of approximate models for various parameters demonstrate effects of these parameters on emitter efficiency, transit times and current gain. These calculations point, in particular, to the importance of optimum doping concentrations in the emitter and base regions for obtaining maximum current gain, and of bandgap narrowing in determining the performance limitations of bipolar transistors.

Experimental study of the minority-carrier transport at the polysilicon—monosilicon interface

This paper presents the results of an experimental study designed to explore both qualitatively and quantitatively the mechanism of the improved current gain in bipolar transistors with polysilicon emitter contacts. Polysilicon contacts were deposited and heat treated at different conditions. The electrical properties Were measured using p-n junction test structures that are much more sensitive to the contact properties than are bipolar transistors. A simple phenomenological model was used to correlate, the structural properties with electrical measurements. Possible transport mechanisms are examined and estimates are made about upper bounds on transport parameters in the principal regions of the devices. The main conclusion of this study is that the minority-carrier transport in the polycrystalline silicon is dominated by a highly disordered layer at the polysilicon-monosilicon interface characterized by very low minority-carrier mobility. The effective recombination velocity at the n+polysilicon-n+monosilicon interface was found to be a strong function of fabrication conditions. The results indicate that the recombination velocity can be much smaller than 104cm/s.

Current gain of silicon bipolar transistor with polysilicon emitter contact

A two-region analysis is presented to predict the common-emitter current gain of a bipolar transistor with the polysilicon contact to the emitter for a case when the recombinations at the mono-poly interface are not negligible. The calculated current-gain enhancement for typical device parameters and for different values of interface recombination velocity show that the current-gain enhancement and its increase with decrease of emitter width is smaller for the interface with larger recombinations.

Effect of silicide process on bipolar transistor current gain

Emitter Gummel number of modern bipolar transistors is an important factor in determining device performance, especially for heavily doped, shallow junction transistors. Removal of even small amounts of the active dopant from the shallow emitter, e.g., Ar sputteretch and PtSi formation, can significantly reduce the current gain of bipolar transistors. A simple theory of bipolar transistor gain shows that degradation of current gain is due to the reduction of emitter Gummel number. Emphasis is placed on the control of the Ar sputteretch and PtSi formation to obtain desired current gain and to determine its implication in the development of advanced bipolar transistors with very shallow emitter junctions.

The influence of post-emitter processing on the current gain of bipolar transistors

The effects of post-emitter processing on the current gain of n-p-n and p-n-p transistors used in linear integrated circuits, is the subject of this paper. It is seen that during the emitter diffusion deep level impurities segregate into the bulk and space-charge regions of the emitter. The aluminum alloy process at 500°C provides a powerful scavenging action that getters the impurities. The post-alloy current gain increases by a factor of ten. This gettering is effective in phosphorus diffused emitters if the dielectric is either a CVD oxide, a plasma deposited oxide, or phosphorus glass under Si 3 N 4 . With thermally oxidized emitters there is no improvement in current gain. Boron diffused emitters, however, respond to the aluminum alloy process regardless of the dielectric. This study also identifies two processes that contribute to bandgap narrowing ( \DeltaE_{g} ) these are the emitter diffusion and the post-emitter thermal oxidation. A value of \DeltaE_{g} = 0.04 eV measured after the emitter diffusion was found to increase to 0.09 eV after thermal oxidation at 975°C. This additional component of \DeltaE_{g} is a result of the anomalous accumulation of phosphorus at the silicon surface during oxidation.

Piezoresistance as the source of stress-induced changes of current gain in bipolar transistors

Changes in common-emitter current gain by uniaxial compression stresses are measured for various kinds of bipolar transistors fabricated on (111) silicon. The results are explained by simple theoretical relationships based upon piezoresistance.