Binary To Excess-1 Converter Research Articles

Enhanced Quasi-Static Energy Recovery and Modified Clock Gating for the Wallace Tree Multiplier with Reversible Adders

High-speed, low-power digital circuits are essential in many digital applications. The objective of the paper is to design high-speed low-power multipliers with reversible gates. The realization of a multiplier with an efficient clocking system is also presented to reduce leakage power consumption. The existing reversible configurations do not possess an effective clocking system for reducing power in an idle state. In this work, a modified clock gating (MCG) and Enhanced Quasi-Static Energy Recovery Logic (EQSERL) are designed to generate a clock pulse. The EQSERL reduces the dynamic state in the circuit and it is designed with reduced complexity. This process effectively reduces leakage power consumption in the circuit. The conventional clock gating circuit is modified for connecting it with the EQSERL. This MCG circuit reduces unwanted power consumption. The conventional Wallace tree multiplier (WTM) involves full adder and half adder circuits. In this proposed work, a square root carry select adder (SQRT CSLA) with a reversible binary to excess-1 converter (BEC) and a ripple carry adder is presented. The reversible gates such as the Feynman gate, the Toffoli gate, and the dual key gate are employed. Finally, the proposed architecture is tested with different clocking circuits using Synopsys tools and the performance metrics like delay and power are observed.

Design and Implementation of Area Efficient 16-bit Carry Skip Adder

Adders are fundamental unit in many computer systems. One of the most efficient adder architectures in terms of delay and area is the carry-skip adder. In this paper an area efficient 16-bit carry-skip adder to achieve high speed and low area were designed. CSA is a rapid adder that is used in data processing systems to execute quick arithmetic operations. As a result, a Modified Carry Skip Adder (MCSA) is developed using a single Ripple Carry Adder (RCA) and a Binary to Excess-1 Converter (BEC) instead of twin RCAs to save size while sacrificing speed. The design is coded in VHDL and its area and delay are analyzed using Xilinx ISE 14.7. The hardware simulation is done in Xilinx Spartan 3E FPGA.

Performance Investigation of a Modified Hybrid Parallel Prefix Adder for Speedy and Lesser Power Computations

Achieving high speed and lesser power in large operand adders is greatly necessitated for incorporating modern portable systems, which are highly demanded in the artificial intelligence sector, especially in deep learning-based applications. Conventional speedy adder structures are based on parallel-prefix (PP) types that have huge power consumption. The modified design is deemed the key solution for contemporary demands in today's modern consumer electronics. The existing hybrid adder (HA) architecture functions on the basis of the framework, in which the least significant carriers are produced in large PP adders quicker than the most-significant ones. The base concept of this HA is to customize the binary to Excess-1 Converter (BEC) and make C in = 1 in the standard Carry Select Adder (CSA) to reduce power and area than RCA. The key improvement in BEC is minimizing the logic gate counts that are necessitated than FA of n-bit architecture. In the existing KS-RCA, the customized BEC is introduced for achieving considerable performance metrics improvement. All existing work and the proposed adder implementation are done in Cadence tool RTL compiler with 90 nm TSMC technologies using the dynamic power verification and analysis methods of RTL. The proposed technique efficiently diminishes the delay that is 76.39% lesser than the CSEL-BEC , 70.86% lesser than CSEL-RCA, and significantly 3.27% lower than the KS-RCA. Also, power consumption is reduced up to 28.92%, 10.61%, and 11.06% than the existing methods, such as KS-RCA, CSEL-RCA, and CSEL-BEC, respectively. However, the area is efficiently reduced by the proposed method up to 29.52% concerning the maximum value of implemented techniques.

Design of Carry Select Adder using BEC and Common Boolean Logic

Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and power consumption in a great way we proposed a design using binary to excess 1 converter (BEC). This paper proposes an dynamic method which replaces a BEC using Common Boolean Logic.

Design and analysis of 32 bit high speed carry select adder

In the area of VLSI design, the focus is on reducing delays, power consumption and space, and improving speed. This paper presents the design of 32-bit modified-HSCSA using parallel prefix adder in which the basic design is based on Binary to Excess-1 Converter (BE1C) and also handouts brief review on traditional techniques used in standard BE1C, Brent-Kung (BK), Lander-Fischer (LF) and Kogge-Stone (KS). The performance of the presented 32 bit modified –CSA using parallel prefix adder is compared with traditional techniques and observed reduced delay. Verilog HDL is used to design the structure and the simulation and synthesis is carried out using Xilinx.

High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic

In this paper, we propose some SQuare-RooT (SQRT) Carry SeLect Adder (CSLA) architectures including a high-speed design, a design with the lowest area compared to previous CSLAs, and two hybrid designs. The first proposed architecture is an optimized design of the Binary to Excess-1 Converter (BEC)-based CSLA by employing a new fast and merged add-one and multiplexing circuit. This architecture in addition to attaining much lower area, delay and energy consumption compared to the BEC CSLA, requires almost the same area compared to the best existing CSLA i.e. IRredundant Carry Generation and Selection scheme (IRCGS CSLA) while providing a higher speed. The second proposed CSLA as the lowest-area design is the area-optimized architecture of IRCGS CSLA that exploits a new logic optimization while maintaining its speed. This scheme makes use of a multiplexer-based logic to reduce the number of gates and to achieve a more compact design. In addition, two hybrid CSLAs are proposed by exploiting the benefits of both proposed CSLA architectures. Experimental results show that the hybrid CSLAs lead to lowest area-delay product and energy-delay product among all the proposed and previous designs in a wide range of 8-bit to 128-bit adder size. In fact, 10–48% reduction in area-delay product and 8–65% reduction in energy-delay product are achieved compared to previous designs. Moreover, the hybrid CSLAs outperform the best existing design with respect to all three parameters of area, delay and energy.

High-Performance Carry Select Adders

This research article proposes high-performance square-root carry select adder (SQRT CSLA) architectures with high speed, area and energy efficiency when compared to the existing SQRT CSLA architectures. The first proposed method uses an optimized design of binary to excess-1 converter (BEC)-based SQRT CSLA by incorporating a carry enable binary to excess-1 converter (CEBEC) design that exploits a new logic optimization on the carry propagation path to improve speed of operation, area and energy efficiency. The second proposed method is an optimized design of the regular SQRT CSLA by employing the carry enable and add-one ripple carry adder (ARCA) architectures to decrease the number of gates. Simulation results show that the proposed CEBEC SQRT CSLA offers a savings of 22.81%, 9.95%, 7.95% and 3.98% on area, 14.50%, 5.21%, 3.72% and 3.11% in power consumption and offers 6.78%, 15.46%, 6.57% and 3.83% lesser delay, 20.33%, 19.92%, 10.09% and 6.89% lesser PDP, 28%, 23.85%, 13.78% and 7.58% lesser ADP than the existing regular, BEC SQRT CSLA, SQRT CSLA1 and SQRT CSLA2 architectures. The proposed ARCA SQRT CSLA architecture exhibits 9.26%, 17.71%, 9.06% and 6.39% lesser delay than the existing regular, BEC SQRT CSLA, SQRT CSLA1 and SQRT CSLA2 architectures.

Design of high speed low power optimized square root BK adder

Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these two regarding area and power is Carry Select Adder (CSA). Parallel prefix adders are used to obtain quick results. In this course work, a new methodology to Modified Square Root Brent Kung adder (MSR-BK-A) is proposed to design an optimized adder and to calculate various performance parameters like area, power and delay for square root adder designs. By optimizing the structure of Binary-to-Excess-1 converter(BEC) and using it in Square Root BK adder, the power and delay can be reduced with a trade of in area. The simulated results conclude that, the MSR-BK-A with Modified BEC gives better performance in terms of power and delay. These designs have been simulated, verified and synthesized using Xilinx ISE 14.7 tool.

Performance and Analysis of Low Power, Areaefficient and High Speed Carryfast Adder

Abstract Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8, 16,32,and 64-bit square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power. Binary to Excess-1 Converter (BEC) instead of RCA with the regular CSLA to achieve lower area and power consumption. The main advantage of this BEC logic comes from the lesser number of logic gates than the n-bit Full Adder structure. The delay and area evaluation methodology of the basic adder blocks. The SQRT CSLA has been chosen for comparison with the proposed design as it has a more balanced delay, and requires lower power and area. Reducing the area and power consumption in the CSLA. Efficient gate-level modification to significantly reduce the area and powerof the CSLA.

Implementation of 32-Bit Carry Select Adder using Brent-Kung Adder

The circuit used to add the two numbers or two bits is adder. The main problem with the adder is both the area and delay to produce the final output. So, this paper implements an adder it requires a less amount of delay and area to produce the final output. The reduction of delay and area is done by the Parallel Prefix Adders. It plays a prominent role in Digital Combinational Circuits. Area and power are other factors which really makes the adder effective. The techniques used to get a less amount of delay and area is by using the Binary-to-Excess-1 Converter (BEC) and a Parallel Prefix Adder. The delay of the Modified Linear Carry Select Adder of Brent Kung Adder is less when compared with the Regular Carry Select Adder architecture. The delay and area further can be improved by using a Square root Carry Select adder. This paper focuses on operation of Parallel Prefix Adders of 32 bit Brent-Kung Adder. Keywords: And-Or-Inverter (AOI) Logic, Binary-to-Excess-1 Converter (BEC), Brent-Kung (BK) Adders, Carry Select Adder (CSLA), Parallel Prefix Adder

Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic

Hierarchy multiplier is attractive because of its ability to carry the multiplication operation within one clock cycle. The existing hierarchical multipliers occupy more area and also results in more delay. Therefore, in this paper, a method to reduce the computation delay of hierarchy multiplier by employing CslA and Binary to Excess 1 Converter (BEC) is proposed. The use of BEC eliminates the n/4 number of adders, existing in the conventional addition scheme, where n denotes the multiplier input width. As the area of the hierarchy multiplier is determined by its base multiplier, the base multiplier is realized with the proposed Vedic multiplier, which has small area and operates with less delay than the conventional multipliers. In addition, the reduction of power consumption in the hierarchy multiplier can be ensured by implementing the designed multiplier with full swing Gate Diffusion Input (GDI) logic. The performances of the proposed and the existing multipliers are evaluated by Cadence SPICE simulator using 45nm technology model. From the simulation results, the performance parameters namely, delay and power consumption are calculated. Further, the area is measured from the corresponding layout for the same technology model. It is examined from the results that the proposed multiplier operates with 17% lesser power delay product than the recently reported hierarchy multiplier. The Monte Carlo simulation is performed to understand the robustness of the proposed hierarchy multiplier.

Low - Power and Area - Efficient Square – Root Carry Select Adders using Modified XOR Gate

Background/Objectives : XOR gate is a primary element in binary adders because which is used to detect sum – output. In this paper a 2-input XOR gate is accomplished by a modified design. Methods/Statistical analysis : Usually a half adder (HA) circuit is designed with one XOR and one AND gate but if this modified XOR is used in HA, the design requires only one XOR gate and the AND gate can be acquired from XOR gate itself. Findings: This modified XOR gate design gives better result when the adder circuit has more number of XOR gates, so we used this modified XOR gate in conventional sqrt CSLA, binary to excess-1 converter (BEC) based sqrt CSLA and optimized logic based (OLB) sqrt CSLA. The results show that Area – Delay – Product (ADP) has been reduced in proposed circuits, 12.45% in conventional sqrt CSLA, 21.45% in BEC based sqrt CSLA and 17.81% in OLB sqrt CSLA. Applications/Improvements: These adders can be used in Arithmetic Logic Unit (ALU) of a micro-processor as a binary adder.

High Speed Area Efficient FFT using Modified SQRT CSLA and 5:3 & 9:4 Compressor

While designing fast fourier transform (FFT) cores, due to the use of multiplexers, memory, or ROMs, there is a substantial increase in power consumption and area. In order to increase speed and throughput, folding and pipelining methods have been approached by various existing designs. But the prime disadvantage of those architectures is the use of multipliers for twiddle multiplications. This present work has proposed fast fourier transform using compressors based multiplier. Both parallel and pipelining techniques have also been used in the proposed designs. Carry Select adder is known to be the fastest adder among the Conventional adder structures. This work uses an efficient Carry select adder by sharing the binary to excess-1 converter (BEC) term. After a logic simplification, we only need one XOR gate, one AND gate and one inverter gate for carry and summation operation. Through the multiplexer, we can select the correct output according to the logic states of the carry in signal. These all design and experiments were carried out on a Xilinx 14.1i Vertex-7 device family.

Design and Implementation of High Speed and Low Power Modified Square Root Carry Select Adder (MSQRTCSLA)

Multiplication and Accumulation (MAC) unit is recognized as high potential in every Digital Signal Processor (DSP). In MAC unit, both Multiplication and Accumulation functions are involved, but the performances of MAC unit is mostly depends on dataflow structure of Accumulation unit. In this study, Modified Square Root Carry Select Adder (MSQRTCSLA) is designed through Very Large Scale Integration (VLSI) System design environment. In the proposed design, Half Adder (HA) and Full Adder (FA) circuits are realized and identified the redundant logic functions. Hence, a new half adder named “Reduced Half Adder (RHA)” and a new full adder named “Reduced Full Adder (RFA)” are proposed in this study. Further the design of RHA and RFA is integrated into Binary to Excess-1 Converter (BEC) based SQRT CSLA architecture to improve the accumulation function of MAC unit. A new BEC based SQRT CSLA architecture is named as “Modified Square Root Carry Select Adder (MSQRTCSLA). Low power consumption, High Speed and Less area utilization are the main key factors in VLSI System design environment. Therefore, Minimizing the Area-Delay Product (ADP) of MSQRTCSLA is the main goal of this study. MSQRTCSLA based accumulation structure offers 22.86% reduction of delay and 8.87% reduction power consumption than conventional BEC based SQRT CSLA based accumulation structure.

FFT utilizing Modified SQRT CSLA and Proposed 5:3 and 9:4 Compressor

While designing Fast Fourier Transform (FFT) cores, due to the use of multiplexers, memory, or ROMs, there is a substantial increase in power consumption and area. In order to increase speed and throughput, folding and pipelining methods have been approached by various existing designs. But the prime disadvantage of those architectures is the use of multipliers for twiddle multiplications. This present work has proposed fast fourier transform using compressors based multiplier. Both parallel and pipelining techniques have also been used in the proposed designs. Carry Select adder is known to be the fastest adder among the Conventional adder structures. This work uses an efficient Carry select adder by sharing the binary to excess-1 converter (BEC) term. After a logic simplification, we only need one XOR gate, one AND gate and one inverter gate for carry and summation operation. Through the multiplexer, we can select the correct output according to the logic states of the carry in signal. These all design and experiments were carried out on a Xilinx 14.1i Spartan 3e device family.

An Area and Speed Efficient Square Root Carry Select Adder Using Optimized Logic Units

Adder is an inevitable circuit in any of the VLSI Designs. Since, the arithmetic operations such as subtraction, multiplication and division depends on the operation of addition, adder is dubbed as heart of any Digital Signal Processor (DSP), microprocesso r and VLSI Architecture. In this report, the logic formulations in regular carry select adder (CSLA) and binary to excess 1 converter (BEC) based CSLA are analysed and the data dependency, redundant logic operations were scrutinized to improve the Area - Del ay Product (ADP). All the redundant logic operations identified were removed and a new logic formulation has been proposed for the CSLA based on data dependency. In the proposed arrangement, the carry select (CS) operation is carried out before calculation of final - sum . Carry input for various selections (corresponding to C in = 0 and 1 ) and fixed C in bits are used for logic optimization of CG and CS units. An efficient CSLA scheme is obtained using optimized logic units using BEC based CSLA Approach. The propo sed CSLA design provides significant values of area and delay than the recently proposed CSLAs. Due to a small carry - output delay, the proposed CSLA design is well suited for square - root (SQRT) based variable CSLA Approach. Simulation results shows that th e proposed SQRT - CSLA involves nearly 42% less area - delay - product (ADP) than the existing CSLAs. This is best among the existing CSLA designs for different bit - widths (128, 64, 32 and 16). Area in terms of logical elements and the delay in nano - seconds were obtained through Xilinx ISE 13.2 Version.

Implementation of Regular Linear Carry Select Adder with Binary to Excess-1 Converter

Regular Linear Carry Select Adder (RCSLA) is one of the fastest adders. From the structure of RCSLA, there is scope to reduce area by using Binary to Excess-1 converter (BEC) technique. By using BEC technique in RCSLA 16, 32, 64 bit architectures have been developed and compared with Regular Linear Carry Select Adder. The modified architectures have reduced area and power with slight increase in delay. Simulation and Synthesis are carried on Xilinx ISE 12.2.The result analysis shows that the modified architectures are better than RCSLA.

VLSI Implementation of Low Power Area Efficient Fast Carry Select Adder

Select Adder (CSLA) is one of the speedest adder utilized as a part of numerous computational frameworks to perform quick number-crunching operations. The Carry select adder utilizes an effective plan by imparting the Common Boolean logic (CLB) term. The modified CSLA architecture building design has created utilizing Binary to Excess-1 converter (BEC). This paper introduces an unique method that replaces the BEC using common Boolean logic. Experimental analysis illustrates that the proposed architecture achieves advantages in terms of speed, area consumption and power.

Implementing Design of Modified Area Efficient Enhanced Square Root Carry Select Adder

In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. In following paper, an area-efficient carry select adder by sharing the common Boolean logic term (CBL) is proposed. Based on this modification a new architecture has been developed and compared with the regular and modified Square-root CSLA (SQRT CSLA) architecture. The modified architecture has been developed using Binary to Excess-1 converter (BEC). The proposed work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in CMOS process technology. The proposed architecture has reduced area, power and delay as compared with the regular SQRT CSLA architecture.

Designing of Modified Area Efficient Square Root Carry Select Adder (SQRT CSLA)

In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converter (BEC). Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed by using CBl. The proposed design has reduced area as well as power,but in this we study only for area with a slight increase in the delay.