Binary Phase Shift Keying Demodulator Research Articles

Design and FPGA Implementation of Signal Strength Measurement Techniques for Satellite Communication Systems

Communication receivers perform three major functions, frequency down conversion, IF demodulation and subcarrier demodulation. The functioning of a receiver is mainly controlled by input signal strength and relative dynamics. Signal strength is measured in terms of Signal to Noise ratio (SNR) and Carrier to Noise power density (C/No). Any measure of signal strength indirectly gives information about receiver performance for that period. Apart from this, SNR measurement in close loop with Phase Locked Loop (PLL) parameter forms the adaptive PLL system, which is one of the driving forces for this paper. The focus of this paper is to find suitable signal strength measurement techniques and their implementation for satellite communication systems. Signal to Noise Variance method (SNV) and Narrow band Wide band Power Ratio (NWPR) methods are considered based on the performance and realization aspects. All techniques require division, logarithm, and multiplication functions for their realization in hardware. CO-ordinate Rotation Digital Computer (CORDIC) algorithm is considered for realizing logarithm function. A comparison study is done for developed algorithm with Intellectual Property (IP) core. Developed SNR techniques are simulated for Binary Phase Shift Keying (BPSK) demodulator system and performance is evaluated for Additive White Gaussian Noise (AWGN). The paper describes the FPGA design and simulations of these techniques. Developed design is targeted to commercial and space qualified FPGA platforms. FPGA implementations results are compared with system level simulation results, and both are found to be satisfactory. Application of developed system in adaptive BPSK demodulator is also presented.

Performance Analysis of BPSK Modulation: A Theoretical Approach

Abstract: Binary Phase Shift Keying (BPSK) represents a fundamental modulation technique extensively utilized within digital communication systems. The present study presents an analytical examination of BPSK modulation, with a specific focus on its theoretical aspects, MATLAB implementation, and performance analysis. The article commences by providing an introduction to modulation techniques and a concise overview of BPSK, emphasizing its significance and applications. Theoretical foundations encompassing the mathematical representation, key parameters, and characteristics of BPSK are thoroughly deliberated upon. Performance metrics, namely the bit error rate (BER) and signal-to-noise ratio (SNR), are scrutinized, incorporating theoretical derivations and analysis. Following this, the implementation of BPSK modulation and demodulation in MATLAB is expounded, supplemented by coding algorithms and code snippets. Empirical results acquired from the MATLAB implementation are presented and scrutinized, alongside a comparison to the theoretical analysis. The article concludes by summarizing the principal findings and contributions, accentuating the advantages and limitations associated with BPSK modulation, and suggesting potential avenues for future research within this domain. By concentrating on the theoretical aspects and providing comprehensive derivations and mathematical analysis, this research enhances our understanding and exploration of BPSK modulation, thereby circumventing the reliance on simulation-based methodologies

Minimally Invasive Hypoglossal Nerve Stimulator Enabled by ECG Sensor and WPT to Manage Obstructive Sleep Apnea

A hypoglossal nerve stimulator (HGNS) is an invasive device that is used to treat obstructive sleep apnea (OSA) through electrical stimulation. The conventional implantable HGNS device consists of a stimuli generator, a breathing sensor, and electrodes connected to the hypoglossal nerve via leads. However, this implant is bulky and causes significant trauma. In this paper, we propose a minimally invasive HGNS based on an electrocardiogram (ECG) sensor and wireless power transfer (WPT), consisting of a wearable breathing monitor and an implantable stimulator. The breathing external monitor utilizes an ECG sensor to identify abnormal breathing patterns associated with OSA with 88.68% accuracy, achieved through the utilization of a convolutional neural network (CNN) algorithm. With a skin thickness of 5 mm and a receiving coil diameter of 9 mm, the power conversion efficiency was measured as 31.8%. The implantable device, on the other hand, is composed of a front-end CMOS power management module (PMM), a binary-phase-shift-keying (BPSK)-based data demodulator, and a bipolar biphasic current stimuli generator. The PMM, with a silicon area of 0.06 mm2 (excluding PADs), demonstrated a power conversion efficiency of 77.5% when operating at a receiving frequency of 2 MHz. Furthermore, it offers three-voltage options (1.2 V, 1.8 V, and 3.1 V). Within the data receiver component, a low-power BPSK demodulator was ingeniously incorporated, consuming only 42 μW when supplied with a voltage of 0.7 V. The performance was achieved through the implementation of the self-biased phase-locked-loop (PLL) technique. The stimuli generator delivers biphasic constant currents, providing a 5 bit programmable range spanning from 0 to 2.4 mA. The functionality of the proposed ECG- and WPT-based HGNS was validated, representing a highly promising solution for the effective management of OSA, all while minimizing the trauma and space requirements.

Simultaneous BPSK classical communication and continuous variable quantum key distribution with a locally local oscillator regenerated by optical injection phase locked loop

This paper proposes a scheme for simultaneous classical communication and continuous variable quantum key distribution with a true local oscillator. In this scheme, the emitter’s laser, after binary phase-shift keying (BPSK) modulation, is multiplexed in polarization with the quantum signal and sent to the receiver. After BPSK demodulation and correction, this signal is used for local oscillator regeneration by an optical injection phase-locked loop method. Comparing the effective noise sources in this scheme with typical local local oscillator schemes revealed that continuous variable quantum key distribution (CV-QKD) with a true local oscillator based on the optical injection phase-locked loop encounters lower levels of noise in comparison to the pre-existing genuine local oscillator CV-QKDs.

Design of an efficient binary phase-shift keying based IEEE 802.15.4 transceiver architecture and its performance analysis

<span lang="EN-US">The IEEE 802.15.4 <a name="_Hlk109306810"></a>physical layer (PHY) standard is one of the communication standards with wireless features by providing low-power and low-data rates in wireless personal area network (WPAN) applications. In this paper, an efficient IEEE 802.15.4 digital transceiver hardware architecture is designed using the binary phase-shift keying (BPSK) technique. The transceiver mainly has transmitter and receiver modules along with the error calculation unit. The BPSK modulation and demodulation are designed using a digital frequency synthesizer (DFS). The DFS is used to generate the in-phase (I) and quadrature-phase (Q) signals and also provides better system performance than the conventional voltage-controlled oscillator (VCO) and look up table (LUT) based memory methods. The differential encoding-decoding mechanism is incorporated to recover the bits effectively and to reduce the hardware complexity. The simulation results are illustrated and used to find the error bits. The design utilizes less chip area, works at 268.2 MHz, and consumes 108 mW of total power. The IEEE 802.15.4 transceiver provides a latency of 3.5 clock cycles and works with a throughput of 76.62 Mbps. The bit error rate (BER) of 2×10-5 is achieved by the proposed digital transceiver and is suitable for real-time applications. The work is compared with existing similar approaches with better improvement in performance parameters.</span>

A 28 nm Bulk CMOS Fully Digital BPSK Demodulator for US-Powered IMDs Downlink Communications

Low-invasive and battery-less implantable medical devices (IMDs) have been increasingly emerging in recent years. The developed solutions in the literature often concentrate on the Bidirectional Data-Link for long-term monitoring devices. Indeed, their ability to collect data and communicate them to the external world, namely Data Up-Link, has revealed a promising solution for bioelectronic medicine. Furthermore, the capacity to control organs such as the brain, nerves, heart-beat and gastrointestinal activities, made up through the manipulation of electrical transducers, could optimise therapeutic protocols and help patients’ pain relief. These kinds of stimulations come from the modulation of a powering signal generated from an externally placed unit coupled to the implanted receivers for power/data exchanging. The established communication is also defined as a Data Down-Link. In this framework, a new solution of the Binary Phase-Shift Keying (BPSK) demodulator is presented in this paper in order to design a robust, low-area, and low-power Down-Link for ultrasound (US)-powered IMDs. The implemented system is fully digital and PLL-free, thus reducing area occupation and making it fully synthesizable. Post-layout simulation results are reported using a 28 nm Bulk CMOS technology provided by TSMC. Using a 2 MHz carrier input signal and an implant depth of 1 cm, the data rate is up to 1.33 Mbit/s with a 50% duty cycle, while the minimum average power consumption is cut-down to 3.3 μW in the typical corner.

A 0.9 pJ/b, Reference Clock Free, Delay-Based, All-Digital Coherent BPSK Demodulator

This letter proposes a novel reference clock free, delaybased coherent binary phase-shift keying (BPSK) demodulator suitable for biomedical devices which receive power and data through the same wireless link. The proposed BPSK demodulator mixes the BPSK input signal and its copy delayed by a half of the carrier period to generate a data Hipping signal whose rising edges indicate when the phases of the BPSK signal Hip. The data are then recovered by sampling the BPSK input signal using the derived data Hipping signal. A phase selector recovers the coherent clock with a 50% duty cycle by selecting either the delayed BPSK input or its complement according to the recovered data. The open-loop operation of the proposed BPSK demodulator enables it to achieve a data rate as high as the carrier frequency. The all-digital implementation makes the demodulator compact, low power, and able to operate at 0.5 V. A test chip running with a 13.56-MHz carrier has been designed and fabricated. Measurement results show that at 0.9 V and a data rate of 13.56 Mb/s, the proposed demodulator only consumes 12.2 μW, corresponding to an FoM of 0.90 pJ/b. This FoM is at least 61 times better than those of the state-of-the-art designs.

Performance Examination of OFDM Modulation Techniques in LTE 4G

The digital modulation methods are being chosen in high data rate systems as Long Term Evolution (LTE) and LTE-A. Quadrature Phase Shift Keying (QPSK) and Binary Phase Shift Keying (BPSK) is the simplest form of the PSK with double carrying capacity when compare to the other traditional techniques in modulation. In conventional method the performance was analyzed in MIMO .In this paper proposed the performance analysis of BPSK and QPSK modulator and demodulator in LTE 4G system models under the Additive white Gaussian Noise (AWGN) and Rayleigh fading by comparing the Bit Error Rate (BER). From the analysis, compare to BPSK QPSK has good BER. Using the MATLAB Simulink tool Implementation is performed.

A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control

A 16-channel closed-loop neuromodulation system-on-chip (SoC) for human epileptic seizure control is proposed and designed. In the proposed SoC, a 16-channel neural-signal acquisition unit (NSAU), a biosignal processor (BSP), a 16-channel high-voltage-tolerant stimulator (HVTS), and wireless power and bidirectional data telemetry are designed. In the NSAU, the input protection circuit is used to prevent MOSFET from overstressing by the high-voltage stimulations. Hence, NSAUs can share electrodes with stimulators. The auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIAs) are designed with the chopper-stabilized technique with a new offset reduction loop. The measured input-referred noise is 2.09 $\mu \textrm {V}_{\mathrm {rms}}$ and the noise-efficiency factor (NEF) is 3.78. The entropy-and-spectrum seizure detection algorithm is implemented in the BSP with 0.76-s seizure detection latency and 97.8% detection accuracy. When the seizure onset is detected by the BSP, the HVTS with adaptive supply control delivers 0.5–3-mA biphasic current stimulation to suppress the seizure onset. The proposed SoC is powered wirelessly, and the bidirectional data telemetry is realized through the same pair of coils in 13.56 MHz. The downlink data rate is 211 Kb/s with the binary phase-shift keying (BPSK) modulation and a new BPSK demodulator. The uplink data rate is 106 Kb/s with the load-shift keying (LSK) modulation. The proposed SoC is fabricated in a 0.18- $\mu \text{m}$ CMOS technology and occupies 25 mm2. Electrical tests have been performed to characterize the SoC performance. In vivo animal experiments using mini-pigs have been performed to successfully verify the closed-loop neuromodulation functions on epileptic seizure suppression.

A fully digital BPSK demodulator for biomedical application

This paper presents a fully digital binary phase-shift-keying (BPSK) demodulator. The proposed system employs a proposed clipper circuit to clamp all peaks of the negative and positive of the received BPSK signal and to generate a synchronous reset signal. The time domain analysis of the voltage clipper shows that the proposed clipper can reduce the output low-to-high and high-to-low times, compared to conventional inverter. This causes two digital signals are generated at the extremum of the modulated BPSK with shrunk pulse widths and removes the need for voltage controlled oscillator (VCO) signal. The proposed BPSK demodulator is designed and post layout simulated in 0.18 μm standard CMOS technology at 10 MHz carrier wave. Monte Carlo's simulation results of the voltage clipper show that the maximum voltage offset never exceed from the nominal value. The proposed demodulator consumes 14 μW using a 1.8 V power supply and occupies 32 × 35 μm2 core area and 500 × 500 μm2 total chip area.

Hiding Stealth Optical CDMA Signals in Public BPSK Channels for Optical Wireless Communication

A new optical steganography scheme is proposed that transmits a stealth optical code-division multiple-access (OCDMA) signal through a public binary phase-shift keying (BPSK) channel. Polarization beam splitters and arrayed waveguide gratings are used to implement a spectral-polarization coding (SPC) system with an incoherent optical source. We employ a Walsh–Hadamard code as the signature code of the user who wants to transmit stealth information using the system. A free space optical link applied to this system maintains the polarization states of light during propagation. The secret data are extracted using correlation detection and balanced subtraction in the OCDMA decoder of the intended receiver, and the other signal from the public channel is reduced by the OCDMA decoder. At the demodulator of the public channel, BPSK demodulation eliminates the stealth signal so that the public channel is not affected by the stealth signal. The two signals cannot interfere with each other. The results of this study show that our proposed optical steganography system is highly secure. The stealth signal can be favorably hidden in the public channel when the average source power of the stealth signal, public noise, and public signal are −5, −3, and 0 dBm, respectively.

BPSK Modulation and Demodulation with Power Line Carrier Communication and GSM Communication for Smart Metering

GSM/GPRS and PLC communication are used for Automatic Meter Reading (AMR) applications. These AMR systems have made substantial progress over the recent years in terms of functionality, scalability, performance and openness such that they can perform remote metering applications for very demanding and complex systems. By using BPSK (Binary Phase Shift Keying) modulation with Power Line Carrier Communication, Smart Metering can be done in Rural Smart Micro-grids. The design and Simulation of BPSK Modulation and Demodulation are successfully done by using MATLAB/Simulink software. The advantages of using BPSK modulation over the QPSK modulation and the advantages of PLC Communication over the GSM Communication is identified in this paper.

Demodulation of acoustic telemetry binary phase shift keying signal based on high-order Duffing system**Project supported by the National Natural Science Foundation of China (Grant No. 51177117) and the National Key Science & Technology Special Projects, China (Grant No. 2011ZX05021-005).

In order to grasp the downhole situation immediately, logging while drilling (LWD) technology is adopted. One of the LWD technologies, called acoustic telemetry, can be successfully applied to modern drilling. It is critical for acoustic telemetry technology that the signal is successfully transmitted to the ground. In this paper, binary phase shift keying (BPSK) is used to modulate carrier waves for the transmission and a new BPSK demodulation scheme based on Duffing chaos is investigated. Firstly, a high-order system is given in order to enhance the signal detection capability and it is realized through building a virtual circuit using an electronic workbench (EWB). Secondly, a new BPSK demodulation scheme is proposed based on the intermittent chaos phenomena of the new Duffing system. Finally, a system variable crossing zero-point equidistance method is proposed to obtain the phase difference between the system and the BPSK signal. Then it is determined that the digital signal transmitted from the bottom of the well is ‘0’ or ‘1’. The simulation results show that the demodulation method is feasible.

A 10-Gb/s Silicon Microring Resonator-Based BPSK Link

We design and demonstrate for the first time an end- to-end binary phase-shift keying (BPSK) link based on silicon microring resonators, with an operational bit-rate at 10 Gb/s. The obtained bit-error-rate is below the forward error correction limit, validating the practical application of the demonstrated technique. Performance comparisons to conventional BPSK modulation and demodulation techniques are also made. The microring-based BPSK link promises a compact, energy efficient, and low-cost interconnect solution for high-capacity transceivers.

A fully digital low-power wide-speed-range BPSK demodulator

A novel binary phase-shift keying (BPSK) demodulator architecture is presented. By using fully digital and trigger receiving method, the proposed demodulator can work properly at a wide speed range and hence can be applied in different applications such as wireless communications, biological implants and portable facilities, etc. The proposed demodulator was implemented by a 0.35-μm complementary metal-oxide-semiconductor (CMOS) process and the chip area is about 0.5 mm2. Measurement results reveal that the proposed demodulator can successfully demodulate the 100 MHz/10 Mbps BPSK signal which is the highest performance. While when it is used to demodulate the lowest speed BPSK signal of 10 MHz/1.0 Mbps, the power consumption is only 319 μw, and the bit error rate (BER) is less than the low test bond (10–9). Measurement results also show that the designed demodulator can work at 100% data-rate-to-carrier-frequency (DRCF) ratio with the frequency up to 25 MHz.

Design and Implementation of Bpsk Modulator and Demodulator Using Vhdl

This paper give the brief description of digital communication system.Digital communication is more reliable, secure and efficient than that of analog communication.In Digital communication,BPSK is most important and efficient technique in terms of signal power. In this paper BPSK modulator and demodulator are purely design by using hardware description language (VHDL) and implementing it on Spartan 3E FPGA kit. I. Introduction In the last years, a major transition from analog to digital modulation techniques has occurred and it can be seen in all areas of wireless communication, satellite and cellular systems. A digital communication system is more reliable than an analog. The aim of the paper is to create a BPSK (Binary Phase Shift Keying) modulator and demodulator using Xilinx ISE 12.3 software. BPSK consist of modulator a channel and demodulator. The modulated signal was achieved in the first Spartan 3E board, passed through a channel and transmitted to the second board, which behaves as a demodulator.

A Low-Power 13.56 MHz RF Front-End Circuit for Implantable Biomedical Devices

A low-power fully-integrated CMOS RF front-end circuit for a passive 13.56 MHz biomedical implant is presented. A 13.56 MHz binary phase shift keying (BPSK) signal is received by an internal coil. This front-end circuit is composed of a full-wave bridge rectifier, a linear regulator, a BPSK demodulator, and a clock/data recovery (CDR). A full-wave bridge rectifier converts the carrier waveform with the BPSK signal to an unregulated DC voltage. A linear regulator stabilizes the unregulated DC voltage to 1.8 V that serves as the DC source for the implant. A BPSK demodulator detects the incoming BPSK signal from the internal coil and translates the demodulated data to the CDR which can successfully recover the clock and data for the system controller. This chip with a core area of 0.45 mm(2) has been fabricated in a TSMC 0.18 μm 1P6M CMOS technology. The total power consumed is only 632 μW.

An Ultra-Low-Power BPSK Receiver and Demodulator Based on Injection-Locked Oscillators

Two highly integrated ultra-low-power binary phase-shift keying (BPSK) receivers for short-range wireless communications are presented. The receivers consist of a power divider, two injection-locked RC oscillators with limiting buffers, and an xor output stage. The demodulation principle exploits the dynamic phase response of the two BPSK signal injected oscillators. As proofs of concept, a 300-MHz receiver/demodulator and an 868/915-MHz industrial-scientific-medical band receiver with digital tuning were implemented in 90-nm bulk CMOS technology. The 300-MHz RX/demod has an active die area of 0.04 mm2, RF input sensitivity of -34 dBm at 1 Mb/s, and consumes just 120 μW from a 1-V supply. The energy efficiency of 0.12 nJ/bit is among the best reported to date for low-power coherent demodulator. Based on the same architecture, the 868/915-MHz BPSK receiver prototype has an active die area of 0.04 mm2, an RF input sensitivity of -50 dBm at 2 Mb/s, and consumes only 216 μW from a 1.2-V supply (0.11 nJ/bit). Digital control of the injection-locked oscillator offset frequencies is implemented on-chip.

Ultra-low power self-calibrating process-insensitive BPSK demodulator for bio-implantable chips

A novel non-coherent binary phase shift keying (BPSK) demodulator featuring ultra-low power and high data rate is presented for inductively powered biomedical implants. A self-calibration technique with process variations compensation is proposed in order to minimize the effect of transmitter frequency changes and to enhance circuit robustness. The circuit is designed in the 0.18µm standard CMOS technology. Simulation results show that the demodulator can tolerate a relatively large frequency shift of at least 85% around the centre frequency in all process corners. The power consumption of the demodulator at a data transmission rate of 16Mbps is as low as 9.4µW at a supply voltage of 1.8V, which is much lower compared to other state of the art BPSK demodulators.

Fully Digital BPSK Demodulator and Multilevel LSK Back Telemetry for Biomedical Implant Transceivers

A novel fully digital binary-phase-shift-keying (BPSK) transceiver for forward data telemetry and a multilevel load-shift-keying (LSK) transceiver for passive back telemetry are implemented. The digital architecture for the BPSK demodulator allows for much less power consumption compared with prior art. The basic premise of the demodulation is to regenerate the incoming BPSK signal using a digital phase-locked loop. We demonstrate the silicon realization of the BPSK demodulator operating at 13.56 MHz in a 0.5-mum complementary metal-oxide-semiconductor process with power consumption of 2.3 mW. The silicon area is 536 times 546 mum2. A novel multilevel LSK for passive back telemetry is implemented, and it works by modulating the load impedance at the implant to create distinct reflections at the primary coil of the reader. The reflections at the reader are decoded for data information using a discrete realization of highly sensitive LSK receiver. The simulation and measurement results indicate 2times improvement in data rate compared with conventional bilevel back telemetry. This brief also shows the implementation of a forward BPSK modulator based on a class-E power amplifier to complete a full biomedical implant transceiver implementation.