Bias Scheme Research Articles

Investigation of AlN/Si based heterogeneous Junction using inter-digitated electrodes for enhanced UV light detection

A 200 nm thick AlN layer is fabricated by Hydride Vapor Phase Epitaxial (HVPE) technique onto the n-type Silicon < 111 > wafer. After epitaxial growth the AlN is masked and 100 nm thick interdigitated electrodes of Silver are deposited by the atomistic scaled Physical Vapor Deposition (PVD) system. These interdigitated electrodes are further examined with five possible circuit configurations of AlN/Silicon under multiple biases and temperatures. Different electrical and electro-optical characterization such as Current-Voltage, Charge Deep Level Transient Spectroscopy and Kinetics of Dark and UV current; have been performed for each configuration. For all such cases the Ultra-Violet (UV) light has been sensed and found that the reversed biased silicon coupled with interdigitated AlN schemes may provide largest responsivity under both photovoltaic and photoconductive modes. Also, the photo-conversion gain (ratio of UV Current / Dark Current) of each case under different physical conditions have also been emulated and found that the same reverse biased configuration leads higher extent of photo-conversion gain. The charge based transient analysis using (Q-DLTS) have been performed for all said configurations and it is found that the same reverse biased scheme offers largest magnitude of capture cross section i.e. ~ 10−18 cm2, which may capture larger extent of free charge carriers in UV mode and could be opted for enhanced UV light detection.

A 0.6-V 11-uW PVT tolerant DTMOS inverter based OTA

This paper presents the design of a process-voltage-temperature (PVT) variation tolerant inverter-based operational transconductance amplifier (OTA) employing both a dynamic threshold MOS (DTMOS) technique and a constant voltage biasing (CVB) scheme. The proposed inverter-based OTA offers a higher bandwidth due to implemented DTMOS technique, which realizes higher input transconductance value than a conventional inverter-based OTA design. Simulation results show that the proposed OTA achieves superior slow-slow (SS) corner performance under PVT variations than the conventional inverter-based OTA while consuming only 11-uW and providing a figure of merit (FoM) of 7.0-MHz.pF/uA. As a result, DC gain and unity-gain bandwidth (UGBW) of the proposed OTA improve by 27% and 32% at SS corner under the PVT variations, respectively.

Multiple Adaptive Current Feedback Technique for Small-Gain Stages in Adaptively Biased Low-Dropout Regulator

Adaptive bias scheme, which can be used to provide a current proportional to the current flowing through the power transistor under high current load, avoiding the need for providing additional large fixed bias current to the circuit, has been adopted in many low-dropout regulators (LDO). When an adaptive bias scheme is applied to an LDO with a current mirror buffer, although a low chip area consumption and a better transient response can be achieved, the loop gain of LDO at high-load current and loop bandwidth at low load are still low. In previous works, multiple small-gain stages can effectively improve the gain and bandwidth but may lead to stability problems or even need to consume large currents to ensure stability, thus affecting current efficiency. This article proposes the multiple adaptive current feedbacks technique for small-gain stages in adaptively biased low dropout regulator (AB-LDO) with a current mirror buffer, improving the loop gain and bandwidth and eliminating the need for frequency compensation to meet stability requirements. Moreover, in the case that multiple adaptive bias loops can be introduced after the proposed technique is applied to this design, an intuitive and simple method is adopted to analyze the whole circuit. The designed AB-LDO was fabricated in Semiconductor Manufacturing International Corp (SMIC) 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> m process. The measured results show that the designed LDO realizes 30.75-mV transient performances with a step of 10 ns.

Comparison of the Success Rate of Filled and Unfilled Resin-Based Fissure Sealants: A Systematic Review and Meta-Analysis.

Objectives: Incorporation of fillers might improve the physical properties of sealants. This systematic review and meta-analysis evaluated the retention and caries development rate of filled and unfilled fissure sealants. Materials and Methods: This study was conducted according to the Preferred Reporting Items for Systematic Reviews and Meta-Analysis guidelines. The PubMed, Scopus, Embase, Cochrane Database of Systematic Reviews, and ISI Web of Knowledge were searched until October 24, 2019. The risk of bias (ROB) was assessed for the included studies based on the Cochrane collaboration common scheme for bias, and the meta-analysis was performed through a random effects model. Results: The search resulted in 6,336 unrepeated relevant studies. After the title, abstract and full-text screening, 19 studies with 26 comparing groups were finally included in this systematic review and meta-analysis. According to the included studies, both retention rate and caries development in filled and unfilled resin-based sealants did not significantly differ within 2 years of follow-up. Conclusion: Since there was no significant difference in the retention rate and caries development between filled and unfilled sealants, it seems that the final decision should be made uniquely for each patient according to the type of fissure, patient’s age, habits, etc.

Denial-of-Service Attacks Pre-Emptive and Detection Framework for Synchrophasor Based Wide Area Protection Applications

Synchrophasor technology has been very effective in addressing complex protection problems. Based on the experimental study of the impact of denial-of-service (DoS) cyberattacks on synchrophasor-assisted protection scheme, “adaptive dependability/security bias protection scheme,” a DoS pre-emptive and detection framework is presented in this article. The suggested structure helps in the identification of different types of DoS attacks (targeting data availability) and address resolution protocol (ARP) spoofing (compromising data confidentiality) via unique fingerprints developed using Wireshark network data. Redundant PDC datastream and random data path selector module (RDPS) in the framework help reduce the probability of a successful DoS attack. However, during a successful attack, the framework ensures that a healthy PDC datastream is used by the end application. The proposed methodology's efficacy has been verified using a western system coordinating council 9 bus, and IEEE 39 bus test systems on the real-time digital simulator (RTDS) based cyberphysical wide area measurement system testbed with industrial standard hardware phasor measurement units (PMUs). The results show that the proposed framework can effectively improve the performance of the synchrophasor-based adaptive dependability/security bias scheme during DoS attacks and avoid maloperation of the protective devices, which enhances the power system's stability.

An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing

This brief presents an ultra-low power low-dropout (LDO) regulator with an experimental total quiescent current consumption of only 3.08 nA. The circuit is designed to operate with a load current in the range 0 - 11 mA. A novel adaptive biasing scheme based on a super source follower (SSF) structure is proposed, which measures the absolute voltage difference between the two inputs of the LDO’s error amplifier and modifies the biasing current accordingly. Thus, the transient response of the regulator is improved by counteracting the effect of using such a low bias current. The proposed LDO has been fabricated in a standard CMOS 180 nm process and the experimental characterization showed an outstanding performance in terms of maximum load current over quiescent current consumption ratio.

A Bootstrapped Pseudo Resistor by Reusing OTA-C Filter for Neural Signal Processing

In integrated neural signal monitoring systems, pseudo resistor (PR) is widely used to form very large time constant filters, due to its large impedance within an acceptable die area. However, its linearity (the dependency of the resistance to applied voltage) and impedance are limited by the nonlinear MOS transistors in weak inversion, and suffers from process, voltage and temperature (PVT) variations. In this brief, a PR bootstrapped by reusing the operational transconductance amplifier-capacitor (OTA-C) filter is presented, it substantially increases the impedance and linearity to dynamically support lower frequency neural signal applications. It has no need for extra bias scheme on the gate or bulk, which decreases the circuit complexity, die area and power consumption. The proposed circuit implemented in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process occupies an area of 0.026 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the impedance of the bootstrapped PR is approximately 94 G <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> , and the high-pass cut-off frequency is reduced to 0.5 mHz.

A customizable, low-power, wireless, embedded sensing platform for resistive nanoscale sensors

Customizable, portable, battery-operated, wireless platforms for interfacing high-sensitivity nanoscale sensors are a means to improve spatiotemporal measurement coverage of physical parameters. Such a platform can enable the expansion of IoT for environmental and lifestyle applications. Here we report a platform capable of acquiring currents ranging from 1.5 nA to 7.2 µA full-scale with 20-bit resolution and variable sampling rates of up to 3.125 kSPS. In addition, it features a bipolar voltage programmable in the range of −10 V to +5 V with a 3.65 mV resolution. A Finite State Machine steers the system by executing a set of embedded functions. The FSM allows for dynamic, customized adjustments of the nanosensor bias, including elevated bias schemes for self-heating, measurement range, bandwidth, sampling rate, and measurement time intervals. Furthermore, it enables data logging on external memory (SD card) and data transmission over a Bluetooth low energy connection. The average power consumption of the platform is 64.5 mW for a measurement protocol of three samples per second, including a BLE advertisement of a 0 dBm transmission power. A state-of-the-art (SoA) application of the platform performance using a CNT nanosensor, exposed to NO2 gas concentrations from 200 ppb down to 1 ppb, has been demonstrated. Although sensor signals are measured for NO2 concentrations of 1 ppb, the 3σ limit of detection (LOD) of 23 ppb is determined (1σ: 7 ppb) in slope detection mode, including the sensor signal variations in repeated measurements. The platform’s wide current range and high versatility make it suitable for signal acquisition from resistive nanosensors such as silicon nanowires, carbon nanotubes, graphene, and other 2D materials. Along with its overall low power consumption, the proposed platform is highly suitable for various sensing applications within the context of IoT.

A Frontend for Magnetoresistive Sensors With a 2.2-pA/√Hz Low-Noise Current Source

In this letter, we present an integrated readout chip for magnetoresistive (MR) sensors consisting of a readout chain that comprises a dc-coupled fully differential difference amplifier (FDDA) followed by a programmable gain amplifier (PGA), as well as a low-noise current biasing scheme for the MR sensor. The current bias scheme features a 10-bit digital-to-analog converter (DAC) to compensate for process variations of the MR sensing element as well as to calibrate for variations in the dc bias field of the sensor. The bias current source achieves a very low current noise floor of 2.2 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sqrt {\mathrm {Hz}}$ </tex-math></inline-formula> for bias currents up to 1 mA. The readout chip is manufactured in 180-nm SOI CMOS and consumes a total power of 38 mW. The letter is an extended version of (Mohamed <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">et al.</i> , 2021) incorporating additional modeling details and measurement results.

Current Balancing Random Body Bias in FDSOI Cryptosystems as a Countermeasure to Leakage Power Analysis Attacks

This paper identifies vulnerabilities to recently proposed countermeasures to leakage power analysis attacks in FDSOI systems based on the application of a random body bias. The vulnerabilities are analyzed and the relative difficulty to obtain the secret key, once the vulnerabilities are taken into account, are compared to the original proposals. A new countermeasure, based on a new body bias scheme, is then proposed. The new countermeasure is based on the equalization of asymmetries in static power consumption dependent on data being stored in registers implemented in FDSOI technology. The countermeasure’s effectiveness is theoretically established through the development of a power model based on technological parameters, and further reinforced through numerical simulations of a dummy cryptosystem implementing part of an AES encrypting round.

Two-phase stratified sampling and analysis for predicting binary outcomes.

The two-phase study design is a cost-efficient sampling strategy when certain data elements are expensive and, thus, can only be collected on a sub-sample of subjects. To date guidance on how best to allocate resources within the design has assumed that primary interest lies in estimating association parameters. When primary interest lies in the development and evaluation of a risk prediction tool, however, such guidance may, in fact, be detrimental. To resolve this, we propose a novel strategy for resource allocation based on oversampling cases and subjects who have more extreme risk estimates according to a preliminary model developed using fully observed predictors. Key to the proposed strategy is that it focuses on enhancing efficiency regarding estimation of measures of predictive accuracy, rather than on efficiency regarding association parameters which is the standard paradigm. Towards valid estimation and inference for accuracy measures using the resultant data, we extend an existing semiparametric maximum likelihood ethod for estimating odds ratio association parameters to accommodate the biased sampling scheme and data incompleteness. Motivated by our sampling design, we additionally propose a general post-stratification scheme for analyzing general two-phase data for estimating predictive accuracy measures. Through theoretical calculations and simulation studies, we show that the proposed sampling strategy and post-stratification scheme achieve the promised efficiency improvement. Finally, we apply the proposed methods to develop and evaluate a preliminary model for predicting the risk of hospital readmission after cardiac surgery using data from the Pennsylvania Health Care Cost Containment Council.

Strategy of Mitigating Breakdown Interference and Yield Loss in Crossbar Memory

The fault devices induced by device breakdown (BD) are unavoidable due to defect formation during fabrication or along with device cycling stress. The BD cells not only deteriorate device yield, but they also introduce sneak current and result in cell-to-cell interference in the high density crossbar array, which further produces severe array yield loss. Although the BD interference is important, methods of alleviation is less discussed. In this work, we evaluate the strategy of mitigating the strong interference between normal cells and leaky BD cells. We show that while a sufficiently high device yield is the prerequisite, optimizing cell parameters such as resistance of the BD cell and line resistance are proven crucial. However, the yield loss induced by BD interference is not easily compensated using naive redundancy designs. Therefore, a careful optimization on array partition is thus required. We show that with a device yield of 99% and a total memory capacity of megabits, partitioning into a smaller array size (<128 x 128) provides a higher area density than that into larger array sizes. Finally, we proposed a testing bias scheme to rapidly evaluate the device and array yields with an n-time speedup in test latency for an n x n array. The proposed testing bias scheme provides an effective way of ruling out inappropriate low-yield arrays in a memory bank with multiple array blocks.

Multi-Objective Land Use Allocation Optimization in View of Overlapped Influences of Rail Transit Stations

Taking into consideration the overlapped influences of multiple rail transit stations upon land use characteristics, this study newly develops a multi-objective land use allocation optimization model to decide the land use type and intensity of every undeveloped land block of an urban area. The new model is solved by successively utilizing the non-dominated sorting genetic algorithm and the technique for order performance by similarity to ideal solution to obtain the least biased Pareto-optimal land development scheme. The study area is an urban region around two metro stations in Beijing of China. The influencing scopes of these two stations are overlapped in part, and many of the land blocks in the study area are not yet developed. It is shown that the newly developed land use allocation optimization model is able to rationally achieve multi-objectives in coordination to the most extents for the sustainable urban development in view of the integrated effect of multiple rail transit stations.

The COVID-19 Run on Medical Resources in Wuhan China: Causes, Consequences and Lessons.

The COVID-19 run on medical resources crashed Wuhan’s medical care system, a medical disaster duplicated in many countries facing the COVID-19 pandemic. In a novel approach to understanding the run on Wuhan’s medical resources, we draw from bank run theory to analyze the causes and consequences of the COVID-19 run on Wuhan’s medical resources and recommend policy changes and government actions to attenuate runs on medical resources in the future. Like bank runs, the cause of the COVID-19 medical resource run was rooted in China’s local medical resource context and a sudden realignment of expectations, reflecting shortages and misallocations of hospital resources (inadequate liquidity and portfolio composition); high level hospitals siphoning-off patients from lower level health providers (bank moral hazard and adverse selection problem); patients selecting high-level hospitals over lower-level health care (depositor moral hazard problem); inadequate government oversight and uncontrolled risky hospital behavior (inadequate bank regulatory control); biased medical insurance schemes (inadequate depositor insurance); and failure to provide medical resource reserves (failure as lender of last resort). From Wuhan’s COVID-19 run on medical resources, we recommend that control and reform by government enlarge medical resource supply, improve the capacity of primary medical care, ensure timely virus information, formulate principles for the allocation of medical resources that suit a country’s national conditions, optimize the medical insurance schemes and public health fund allocations and enhance the emergency support of medical resources.

Noise Performance Comparison Between Current- and Voltage-Bias Readout Schemes for DC SQUID

There are two bias schemes, namely current-bias and voltage-bias, for the directly coupled readout circuit of direct current superconducting quantum interference device (dc SQUID). In order to find out the difference between two bias schemes, we present the theoretical analyses on their equivalent circuits, working point locations, and noise performances. The theoretical analysis and experimental validation prove that the voltage-bias scheme achieves a larger transfer coefficient and exhibits a better noise performance than the current-bias scheme in the reading of conventional dc SQUID.

Dependence of Temperature and Back-Gate Bias on Single-Event Upset Induced by Heavy Ion in 0.2-μm DSOI CMOS Technology

The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM). The physical mechanism of single-event effect (SEE) is explained through technology computer-aided design (TCAD) simulations. TCAD simulations were also performed to explain the impact of back-gate bias on charge collection and full width at half maximum (FWHM) of the pulsewidth at various temperatures. Both charge collection and FWHM of the pulsewidth increase significantly with temperature rising from 240 to 400 K. It is demonstrated that the SEU threshold linear energy transfer (LET) for a DSOI 6T SRAM cell decreases with an increase in temperature. Compared with a fully depleted SOI (FDSOI) technology, the unique independent back-gate bias scheme for a DSOI SRAM cell exhibits higher tolerance to SEU. At 400 K, it is found that the SEU threshold LET (LET_th) for a DSOI 6T SRAM cell increases by 12.5&#x0025; with back-gate bias of nMOS reduced from 0 to &#x2212;15 V.

Stable Light‐Emitting Electrochemical Cells Using Hyperbranched Polymer Electrolyte

AbstractThe choice of an adequate electrolyte is a fundamental aspect in polymer light‐emitting electrochemical cells (PLECs) as it provides the in situ electrochemical doping and influences the performance of these devices. In this study, a hyperbranched polymer (Hybrane DEO750 8500) blended with a Li salt is used as a novel electrolyte in state‐of‐the‐art Super Yellow (a polyphenylenevinylene) based LECs. Due to the desirable properties of the hyperbranched polymer and the homogeneous and smooth films that it forms with the emitting polymer, PLEC with excellent electroluminescent properties are obtained using a pulsed current bias scheme. The devices are very stable, with lifetimes in excess of 2000 h with initial luminance values above 450 cd m−2, a peak efficiency of 12.6 lm W−1, and sub‐minute turn‐on times. The stability of the devices is also studied by measuring the photoluminescence (PL) of the semiconductor during electroluminescent operation. The findings suggest that it is possible to observe the quenching of the PL in vertically stacked devices due to the advancement of the doped fronts in the film and an immediate PL recovery when the bias is removed.

A five biases, three layers graphene basedTHzabsorber: Exploiting dual bias periodic arrays of grapheme ribbons

AbstractWave absorbers are considered main operational block for light manipulation. Numerous optical and electromagnetic systems can be realized via wave absorbers such as wave modulators, filters, and detectors. Here in this work, a highly tunable wave absorber is proposed, which includes three layers of grapheme patterns on dielectric. While whole device is placed on top of a relatively thick metallic reflector. Leveraging dual bias scheme for periodic arrays of grapheme ribbons and exploiting impedance matching concept give the opportunity to adjust absorption response via external bias voltages. All consisting parts of the device are modeled by passive circuit elements include resistor, inductor, and capacitor. Compared to conventional methods of full wave numerical modeling like finite element methods, the presented design methodology requires less CPU time and occupied memory. According to the simulation results, proposed wave absorber shows a multi‐band absorption with four peaks, which make it perfect choice for several application from medical imaging to indoor communication.

Multi-bias graphene-based THz super absorber

The terahertz frequency band becomes a growth platform of various applications from medical imaging to indoor communications. Emerging new materials such as graphene and developing reliable models paved the design way for graphene-based microstructures. This paper proposes a relatively comprehensive design methodology for graphene-based multi-layers structures. The procedure includes forming device geometry, finding graphene patterns, material types, and optimizing control parameters. In this way, a reconfigurable THz wave absorber is introduced. Exploiting a multi bias scheme for a single graphene layer provide opportunity to affect device reaction via bias itself and patterns period simultaneously which increase adjustability of device response. Also using two different graphene patterns turns the device complex regarding design optimizations and simulations. So a well-known and simple circuit representation is used to design the proposed methodology and the proposed device. Knowing equivalent circuit models for the device elements triggers developing an evolutionary algorithm to search for a desirable response. In this context, the paper suggests using a weighted binary matrix in the design process. The matrix determines bias schemes for each layer. Then an evolutionary algorithm optimizes whole biases values. The expectation is more in-depth control over the device behavior via biases values. This is verified by exploited circuit model formulations and Finite Element Method (FEM) as numerical simulation for a unique three layers device.

Mimicking associative learning using an ion-trapping non-volatile synaptic organic electrochemical transistor

Associative learning, a critical learning principle to improve an individual’s adaptability, has been emulated by few organic electrochemical devices. However, complicated bias schemes, high write voltages, as well as process irreversibility hinder the further development of associative learning circuits. Here, by adopting a poly(3,4-ethylenedioxythiophene):tosylate/Polytetrahydrofuran composite as the active channel, we present a non-volatile organic electrochemical transistor that shows a write bias less than 0.8 V and retention time longer than 200 min without decoupling the write and read operations. By incorporating a pressure sensor and a photoresistor, a neuromorphic circuit is demonstrated with the ability to associate two physical inputs (light and pressure) instead of normally demonstrated electrical inputs in other associative learning circuits. To unravel the non-volatility of this material, ultraviolet-visible-near-infrared spectroscopy, X-ray photoelectron spectroscopy and grazing-incidence wide-angle X-ray scattering are used to characterize the oxidation level variation, compositional change, and the structural modulation of the poly(3,4-ethylenedioxythiophene):tosylate/Polytetrahydrofuran films in various conductance states. The implementation of the associative learning circuit as well as the understanding of the non-volatile material represent critical advances for organic electrochemical devices in neuromorphic applications.