Bias Stress Conditions Research Articles

Doped Vertical Organic Field-Effect Transistors Demonstrating Superior Bias-Stress Stability.

Bias-stress stability is essential to the practical applications of organic field-effect transistors (OFETs), yet it remains a challenge issue in conventional planar OFETs. Here, the feasibility of achieving high bias-stress stability in vertical structured OFETs (VOFETs) in combination with doping techniques is demonstrated. VOFETs with silver nanowires as source electrodes are fabricated and the device performance is optimized by understanding the influence of device parameters on performance. Then, the bias-stress stability of the optimized PDVT-10 VOFETs is investigated and found to be superior to the corresponding planar OFETs, which is attributed to reduced trapping effects of gate dielectrics in the VOFETs. Moreover, the bias-stress stability can be further improved by doping PDVT-10 to passivate bulk traps. Consequently, the characteristic time of doped PDVT-10 VOFETs extracted from stretched exponential equation is found to be over four times larger than that of the planar PDVT-10 OFETs under the same bias-stress conditions. These results present the promising applications of VOFETs as well as an effective strategy to achieve highly bias-stress stable OFETs.

Modulation of resistive switching properties of non-stoichiometric WO3−x based asymmetric MIM structure by interface barrier modification

The impact of device operation condition and ambient moisture on the interface-type resistive switching (RS) characteristics of a non-stoichiometric polycrystalline tungsten oxide (WO3−x) based metal–insulator–metal device with an Au top electrode and a Pt bottom electrode has been investigated. The device exhibits rectification and stable bipolar RS characteristics without the need for any forming step, where the switching is primarily dominated by the Schottky type Au/WO3−x interface. DC conduction characteristics of the device have been investigated at different temperature, bias stress, and relative humidity conditions. Current conduction through the active layer has been found to be dominated by Schottky emission at low electric field and Poole–Frenkel emission at high electric field. An increase in current and a strong reduction in the rectification characteristic have been observed on subjecting the device to DC bias stress of appropriate polarity as well as increasing ambient moisture. Modification of the Schottky barrier due to defect redistribution when DC bias stress is applied and due to the dipoles induced at the Au/WO3−x interface by water molecules with increasing ambient moisture content have been discussed as a possible mechanism of the observed RS modulation.

(Invited) Achieving Stable Organic Transistors By Eliminating the Major Degradation Pathways

Organic semiconductors (OSCs) have attracted a great deal of attention over the past decades given their unique properties, which provide an opportunity to incorporate electronics in non-traditional areas such as bio-integrated devices, flexible and rollable displays or clothing. Coupled with low-cost processing and chemical versatility, these materials are gradually becoming an integral part of various components in contemporary optoelectronic applications. For example, the organic field-effect transistors (OFETs) represent the basic building blocks of displays, radio frequency identification tags and conformable sensors. Along with a performance that should match the application specific requirements, maintaining this performance during operation is a prerequisite for any technology. Therefore, identifying the sources and mechanisms leading to operational instabilities are crucial in eliminating their impact, to ultimately achieve the much-needed stability to make these devices components in real-life applications. In this presentation, I will discuss the sources of instabilities in organic transistors and how they manifest in device operation. I will then describe a technique which provides a reliable diagnostic tool to identify with high accuracy the environmental and operational degradation pathways occurring in OFETs during operation. By identifying the most probable degradation pathways, we developed new device design rules which resulted in OFETs with unparalleled operational stability in both staggered and coplanar configurations regardless of the active material (small molecule and polymeric OSCs), as confirmed by the constant mobility and exceptionally low threshold voltage shift of ΔVth = 0.1 eV achieved under aggressive bias stress conditions for 500 min in ambient air.The work was done in collaboration with Hamna F. Iqbal, Qianxiang Ai, Karl J. Thorley, Hu Chen, Iain McCulloch, Chad Risko, and John E. Anthony

Degradation modeling with spatial mapping method in low temperature poly silicon thin film transistor aged off-state bias

We conducted experimental and quantitative studies on the effects of off-state bias stress of the p-type polycrystalline silicon thin film transistors, and present a degradation model using spatial mapping simulations. In the off-state bias stress condition, the gate induced drain leakage current (GIDL) is determined by the gate and drain voltage (Vgd), and the gate bias stress above a certain bias is accompanied by a change in Vth. The spatial distributions of the electric field and the electron concentration are considered as degradation factors, and are used in the equations for defect creation (DC) and the charge trapping (CT) model. We had to implement different forms of the aging model in the two regions: 1) CT in the poly-Si/SiOX interface, and 2) DC in the channel bulk. Finally, our degradation model allows us to analyze how the GIDL current decreases with various aging conditions, and provides a quantitative relationship between the amount of charge trapping and the amount of defect creation.

New Degradation Model of LTPs TFT Aged Off-State Bias Stress on Flexible Substrate

We conducted experimental and quantitative studies on the effects of off-state bias stress of the p-type polycrystalline silicon thin film transistors (TFTs) on flexible substrate and presented a new degradation model using TCAD simulation. In the off-state bias stress condition, the gate induced drain leakage (GIDL) current is determined by the gate and drain voltage (Vgd) and gate bias stress above a certain bias is accompanied by a change in Vth. To understand and model the underlying mechanism of these results, we developed a spatial probability analysis model with mapping of physical quantity (SPAM). The spatial distribution the E-field and the electron concentration are considered as degradation factors, and are used in the equations for defect creation (DC) and charge trapping (CT) TCAD model. We had to implement different forms of aging model in the two regions: 1) CT in poly-Si/SiOX interface, and 2) DC in the channel bulk (especially, the grain boundary). Finally, our new degradation model allows us to analyze how the GIDL current decreases with various aging conditions and provides a quantitative relationship between the amount of charge trapping and the amount of defect creationI. Fixed negative charge (-) of interface of poly-Si/SiOx(ε(x,y) > εC,f and n(x,y)> nC,f)Qfix (-) (x,y)=αf *[{ε(x,y)-εC,f}/εm,f ]γf_field *[log{n(x,y)/nC,f }]γfn II. Ionized defect density of channel bulk (Grain and GB)(ε(x,y,z) > εC,tA ) NtA (-) =gtA (ε)*exp[-{(EtA-EGA)/WGA}2 ]gtA (ε)= αtA*[{ε(x,y,z)-εC,tA}/εm,tAm ]γtA Figure 1

A Review on the Recent Advancements in Tin Oxide-Based Thin-Film Transistors for Large-Area Electronics

Amorphous oxide semiconductors have gained significant attention in the past few decades and have emerged as a promising material for thin-film transistors (TFTs) because they offer high carrier mobility (> 10–50 cm2/V s) and uniformity. In particular, amorphous indium-gallium-zinc-oxide (a-IGZO) has been widely employed as an active channel material in TFTs owing to its high mobility. However, indium-based TFTs suffer from stability problems under positive, negative, and illumination bias stress conditions, which limits their applications in flat-panel displays. Moreover, the limited supply of indium and growing demand for high-stability TFTs with better electrical performance has led to the introduction of tin oxide as a promising solution to replace indium in TFTs. This review provides an overview on the progress and recent developments in indium-free tin oxide-based TFTs for large-area electronics, with special emphasis on the sputtering technique. In addition, the source of the dual conductivity of tin oxide is addressed, which will be helpful in designing complementary metal oxide semiconductor devices. The instability problems and approaches to improve the electrical performance of tin oxide TFTs are also discussed.

(Invited) UV and Gate Stress Induced Defects in Amorphous Indium Gallium Zinc Oxide Thin Film Transistors and Self-Repair

Defects were generated in the amorphous indium gallium zinc oxide thin film transistor under combined ultraviolet light illumination and gate bias stress conditions, which showed as the positive shift of the threshold voltage and the increase of the threshold swing. When exposed to the ultraviolent light without or with the positive gate voltage bias, positively charged defects were quickly generated and saturated at the gate dielectric interface. Majority of these defects were self-repaired at room temperature under air exposure within 5 minutes. On the other hand, under the ultraviolent exposure and negative gate voltage bias condition, two types of defects were generated, i.e., those loosely trapped at the interface and those deeply trapped in the bulk of the gate dielectric layer. At room temperature, the former were quickly self-repaired and the latter were slowly self-repaired. All defects were removed when annealed at 200°C. The understanding of the defect generation and removal mechanism is important for practical applications of this type of oxide thin film transistor.

Reliability and performance improvement of InGaZnO thin film transistors with organosilicon passivation layers

In this paper, we report an InGaZnO thin film transistor with organosilicon passivation layer (PVL) which can effectively improve the reliability and performance of the InGaZnO thin film transistor due to its excellent gas barrier property and the hydrogen doping effect of PVL. The TFT with organosilicon PVL exhibits a boosted performance with mobility of 17.78 cm2/v·s, threshold voltage of 2.78 V, subthreshold swing of 0.41 V/decade and Ion/Ioff of 1.37 × 107. Moreover, the proposed PVL for InGaZnO thin film transistor shows a small threshold shift of 0.89 V and −1.14 V for positive bias stress and negative bias stress condition, respectively.

Stable Hysteresis-Free MoS2 Transistors With Low-k/High-k Bilayer Gate Dielectrics

Hysteresis-free and low-voltage operation are essential for low-power-consumption electronics. Herein, MoS2 transistors configured with bilayer-stacked polymethyl methacrylate (PMMA)/poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) gate dielectric are demonstrated, which leverages the advantages of the hysteresis-free characteristic of PMMA and high- ${k}$ property of P(VDF-TrFE). The trap density and the threshold voltage of the devices can be reduced to $7.0\times 10^{11}$ cm $^{-2}\cdot eV^{-1}$ and −2.2 V, respectively. Moreover, the devices maintain stable performance under bias stress conditions. The devices present negligibly changed transfer and output characteristics over 101 cycling tests, indicating excellent stability. The bilayered dielectric engineering strategy provides a promising avenue to achieve hysteresis-free low-power operation in 2D materials based transistors with high stability.

Characterization and analysis of low-temperature time-to-failure behavior in forward-biased Schottky-type p-GaN gate HEMTs

The low-temperature gate reliability of Schottky-type p-GaN gate AlGaN/GaN heterojunction field-effect transistors under forward gate voltage stress is investigated. Both temperature-accelerated and voltage-accelerated time-dependent gate breakdown stress experiments are performed. The p-GaN gate exhibits a shorter time-to-failure at a lower temperature. It is found that the time-to-failure at “use conditions” predicted by acceleration tests at high gate bias stress could be overestimated at low temperatures. Such a discrepancy stems from the distinct dominant gate leakage mechanisms at high/low gate bias stress conditions. The dominant physical mechanism of the low-temperature gate leakage current is identified to be Poole–Frenkel emission at low gate bias and Fowler–Nordheim tunneling at high bias. From the physical model, a more accurate lifetime projection can be obtained for given use conditions.

LRS retention fail based on joule heating effect in InGaZnO resistive-switching random access memory

This study reports the low-resistance state retention fail of InGaZnO resistive-switching random access memory (ReRAM) under constant DC bias stress conditions by Joule heating effect. There were the abrupt state changes of InGaZnO ReRAM devices with high voltage stress over 0.6 V because of thermal energy in conducting filament. In addition, SPICE simulation was conducted with verilog-A to verify this retention fail mechanism. We believe these results are potentially useful to the analysis on the retention fail properties of ReRAM devices as well as the system-level simulations with reliability-awareness.

Worst-Case Bias for High Voltage, Elevated-Temperature Stress of AlGaN/GaN HEMTs

The effects of high-field stress are evaluated for industrial-quality AlGaN/GaN HEMTs as a function of bias and temperature. Positive and negative threshold voltage shifts are observed, depending on stress conditions, indicating the presence of acceptor-like and donor-like traps in these devices. Worst-case transconductance degradation under rated device operating conditions is observed for devices subjected to high-voltage stress in the ON bias condition at elevated temperature. This contrasts with results on earlier-generation devices, which often show worst-case response under semi-ON bias conditions, emphasizing that each technology requires characterization under multiple bias-stress conditions. Neutral and charged oxygen donor-like DX centers and substitutional acceptor-like $\text{N}_{\mathrm{ Ga}}$ centers are the dominant defects contributing to low-frequency noise in these devices. Dehydrogenation of $\text{O}_{\mathrm{ N}}$ -H complexes during ON-bias stress and the resulting increases in densities of $\text{O}_{\mathrm{ N}}$ -related donor-like defects are evidently the reliability-limiting mechanism in these devices.

A Facile Doping Process of the Organic Inter-Layer Dielectric for Self-Aligned Coplanar In-Ga-Zn-O Thin-Film Transistors

A new doping technique to form the conductive source/drain regions of self-aligned coplanar In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) was demonstrated. The electrical resistivity of the IGZO film was reduced to $3.8{\times } {10}^{-{4}} \Omega \cdot $ cm after simply coating the organic inter-layer dielectric thin film. The carrier mobility at the saturation region and subthreshold swing of the fabricated IGZO TFTs were 18.4 cm2/Vs and of 150 mV/dec, respectively. The channel width-normalized contact resistance was estimated to be as low as $12~\Omega \cdot $ cm, verifying the ohmic behaviors. Robust device stabilities were also confirmed under bias-stress and temperature-stress conditions.

Modeling of NBTS Effects in P-Channel Power VDMOSFETs

This paper studies negative bias temperature instability in commercial IRF9520 p-channel power VDMOSFETs under both static and pulsed bias stress conditions in order to model this effect. The pulsed voltage stressing caused generally lower shifts as compared to static stressing performed at the same temperature with equal stress voltage magnitude, as a consequence of partial recovery during the low level of pulsed gate voltage. It was shown that the quantitative differences between static and pulsed NBT stress depend on the duty cycle, and the differences become more significant as the duty cycle decreases. It was found that $25~\mu {\mathrm{ s}}$ off-time of the pulsed stress voltage could suffice to remove the major part of the recoverable component of the degradation created during the foregoing pulse on-time. An equivalent electrical circuit has been proposed and on the basis of these experimental results a modeling of threshold voltage shifts induced by pulsed negative bias temperature stress has been done.

An Ultra‐Flexible Solution‐Processed Metal‐Oxide/Carbon Nanotube Complementary Circuit Amplifier with Highly Reliable Electrical and Mechanical Stability

AbstractHere, high‐performance flexible complementary metal‐oxide–semiconductor (CMOS) amplifiers with extremely stable electro‐mechanical characteristics by employing low‐temperature solution‐processed amorphous indium–gallium–zinc oxide (a‐IGZO) and single‐walled carbon nanotube (SWCNT) thin film transistors (TFTs) is demonstrated. The photochemical‐activated combustion sol–gel a‐IGZO and SWCNT TFTs show average saturation mobility of 6.82 and 0.51 cm2 V−1 s−1, respectively. Based on the devices, a‐IGZO/SWCNT‐based CMOS amplifiers are implemented on ultrathin and flexible substrates (thickness of ≈3 µm), exhibiting small‐signal gain and unity‐gain bandwidth of up to 25 dB and 25 kHz, respectively, with highly reliable characteristics from 1000 bending stress (radius of 125 µm) and positive gate bias stress conditions (for up to 3 h). The underlying mechanisms of the CMOS performance combined with large output impedance of the SWCNT load are investigated in detail via various circuit implementations and automatic integrated circuit modeling Spice simulation and comprehensive electrical analysis. To ensure the viability of the extremely stable electromechanical properties of the flexible amplifier, a numerical analysis is carried out based on finite‐element methods with an integrated circuit emphasis to find the best match of the CMOS architecture and optimized structural integrity, verifying highly reliable and scalable skin‐like electronics.

A physical and versatile aging compact model for hot carrier degradation in SiGe HBTs under dynamic operating conditions

This paper presents a new physics-based compact model implementation for interface state creation due to hot-carrier degradation in advanced SiGe HBTs. This model accounts for dynamic stress bias conditions through a combination of the solution of reaction-diffusion theory and Fick’s law of diffusion. The model reflects transistor degradation in terms of base recombination current parameters of HiCuM compact model and its accuracy has been validated against results from long-term DC and dynamic aging tests performed close to the safe-operating-areas of various HBT technologies.

Novel Degradation Model of Igzo TFT on High Drain Bias Stress

In this paper, the TCAD degradation model of IGZO using spatial distribution (X, Y) of physical parameters is proposed for the first time and is confirmed according to various channel length, active thickness, and bias stress conditions that agree with actual measurements. Oxygen vacancy in the presence of 2+ ionized states (VO 2+) in IGZO is stable. However, when band bending is severe, the electrons are captured, and the structural transition occurs as a neutral VO in the meta-stable state. This process is assumed to be a mechanism of IGZO degradation at high drain bias stress, and the electric field (>0.5M V/cm) and electron concentration (>1x1010 cm-3) in the channel are considered as the main factors of degradation and are modeled using the mapping function provided by Silvaco. Fig.1 show that the flow of development of degradataion model using TCAD. Based on the oxide degradation mechanism, the following mathematical model was proposed to determine the number of electrons captured by the electric field, Ɛ(X,Y) and the electron concentration n(X,Y) at each position in the oxide film according to equation 1. Here, ƐC and nc represent the critical electric field and electron concentration at which the deterioration starts, respectively, and 0.5 M V/cm and 1x1010 /cm3. ƐC represents the minimum energy required for metastable transition to the metastable state, and nc is a threshold value that rapidly increases the probability of occurrence of this event. These parameters can be very important physically, but they are now empirically derived from the measurement results. Figure 1

Impact of Polyimide Film Thickness for Improving the Mechanical Robustness of Stretchable InGaZnO Thin-Film Transistors Prepared on Wavy-Dimensional Elastomer Substrates.

We report on the In-Ga-Zn-O thin-film transistors (IGZO TFTs) with outstanding mechanical stretchability, which were fabricated on ultrathin polyimide (PI) film/prestrained elastomer with a wavy-dimensional structure. The device characteristics of the fabricated devices were evaluated under mechanically strained conditions with various strains. The operational reliabilities against the bias stress conditions and during the cyclic stretching tests were also carefully examined. The stretchable IGZO TFTs exhibited good device operations without any marked degradation under stretching/compressed conditions with a strain of 40%. Under positive bias stress with a prestrain of 50%, the turn-on voltage instabilities for the TFTs prepared on 0.9 and 2.0 μm-thick PI films were estimated to be 1.5 and 3.9 V, respectively. During the cyclic stretching tests with a strain of 50%, the device operations failed after 20,000 and 100,000 stretching cycles for the TFTs fabricated on 2.0 and 0.9 μm-thick PI films, respectively. As a result, the IGZO TFTs fabricated on a thinner PI film presented more reliable operations after the repeated stretching events. The robust mechanical stretchability dependent on the PI film thickness was suggested to be due to the difference in critical values of bending radii and the influence of the local strain induced by the spatial fluctuations of the wavy structures.

Effect of interfacial InZnO conducting layer on electrical performance and bias stress stability of InAlZnO thin-film transistors

InAlZnO (IAZO) thin-film transistors (TFTs) containing an InZnO (IZO) conducting layer at the interface between the IAZO channel layer and the gate insulator layer were fabricated. The electrical characteristics and bias stress stability of the IAZO/IZO TFTs were examined as functions of the thickness of the interfacial IZO conducting layer (which was set as 1, 2, and 3 nm), and optimal performance of the TFTs was achieved when the thickness was 2 nm. The optimized IAZO/IZO TFT showed a saturation mobility of 52.6 cm2/V·s, which is superior to that of a pristine IAZO TFT (29.8 cm2/V·s). Furthermore, the threshold voltage shifts under positive and negative bias stress conditions simultaneously improved from +2.1 V to +1.0 V and from −1.1 V to −1.0 V, respectively. IAZO/IZO interfaces were analyzed by X-ray photoelectron spectroscopy to elucidate the cause of the improved device characteristics.

Investigation on the Lateral Trap Distributions in Nanoscale MOSFETs During Hot Carrier Stress

In this letter, the lateral trap distributions in planar and FinFET devices are experimentally studied under various bias stress conditions of hot-carrier degradation (HCD). In contrast to the traditional understanding that the generated traps are crowded near the drain region during hot-carrier stress, it is found that the peak of the trap distribution profile will gradually move closer to the source region with the increase in ${V}_{\text {ds}}$ stress. The results suggest that the electron–electron scattering and multiple vibrational excitation are important mechanisms for the lateral trap distributions during HCD stress, which is helpful for the physical understanding of HCD.