Bias Stress Conditions Research Articles

Enhanced charge injection in 6, 13-bis(triisopropylsilylethylnyl)-pentacene field-effect transistors with a rhenium oxide buffer layer

We introduce a transition metal oxide, rhenium trioxide (ReO3), as a charge injection buffer layer for 6,13-bis(triisopropylsilylethylnyl)-pentacene (TIPS-pentacene) field-effect transistors (FETs). By inserting a ReO3 layer, a large energy barrier between silver source electrode and TIPS-pentacene layer was significantly reduced. While the TIPS-pentacene FETs showed low hole mobility (μh) of 0.25 cm2 V−1 s−1 and large threshold voltage (VTH) of −25 V due to large contact resistance (RC) of 155 kΩ cm, the TIPs-pentacene FETs with ReO3 decreased RC as low as 28 kΩ cm. Thus, we can improve μh to two times greater (∼0.46 cm2 V−1 s−1) and reduce VTH to around 0 V. Together with these improved electrical characteristics, the TIPS-pentacene with ReO3 shows stable operation under gate voltage bias stress conditions. The shift of VTH and degradation of μh which were shown in the TIPS-pentacene FET without ReO3 is suppressed in the TIPS-pentacene FETs with ReO3 under both positive and negative bias conditions.

Degradation Model of a-IGZO TFT due to High Drain Bias Stress

In this paper, the TCAD degradation model of IGZO using spatial distribution (X, Y) of physical parameters is proposed for the first time and is confirmed according to various channel length, active thickness, and bias stress conditions that agree with actual measurements. The asymmetric degradation phenomenon according to the source/drain sweep direction occurs when high VDS stress (> 40 V) is applied to a-IGZO TFT due to the local strong electric field in the drain edge region in the active channel. In the double side gate (DSG) structure, the degree of degradation varies according to VTG, which is influenced by the concentration of electrons induced in the channel. Oxygen vacancy in the presence of 2+ ionized states (VO2+) in IGZO is stable. However, when band bending is severe, the electrons are captured, and the structural transition occurs as a neutral VO in the meta-stable state. This process is assumed to be a mechanism of IGZO degradation at high drain bias stress, and the electric field (>0.5M V/cm) and electron concentration (>1 × 1010 cm−3) in the channel are considered as the main factors of degradation and are modeled using the mapping function provided by Silvaco.

Flexible vertical-channel thin-film transistors using In-Ga-Zn-O active channel and polyimide spacer on poly(ethylene naphthalate) substrate

A flexible vertical-channel thin-film transistor (VTFT) with a channel length of 400 nm was fabricated on a poly(ethylene naphthalate) substrate. The vertical gate-stack composed of gate electrode/gate insulator/active channel was prepared by a conformal atomic layer deposition and a dry etching process of an organic polyimide spacer. The transfer characteristics of the fabricated flexible VTFT were well confirmed after the postannealing process at 200 °C, in which the on/off ratio was obtained to be 1.8 × 102. The threshold voltage shifts were estimated to be +6.1 and −4.5 V under the positive and negative bias-stress conditions for 104 s, respectively. The device characteristics showed no remarkable degradation when delaminating from the carrier glass substrate. Furthermore, there were no marked changes in transfer curves even when the device was bent with a radius of curvature of 10 mm. A suitable choice of spacer material, optimization of the dry etching process, and employment of ultra-thin flexible film substrate were suggested to appropriate solutions for enhancing the device performance of the proposed flexible VTFTs.

Gate-induced drain leakage current characteristics of p-type polycrystalline silicon thin film transistors aged by off-state stress

Thin film transistors have become crucial components of several electronic display devices. However, high leakage current is a frustrating impediment to increasing the efficiency of these transistors. We have performed an experimental and quantitative study on the effects of off-state bias stress on the characteristics of a p-type polycrystalline silicon (poly-Si) thin film transistor (TFT). The gate-induced drain leakage (GIDL) current under off-state bias stress conditions was investigated by changing gate-source voltage (Vgs) and drain-source voltage (Vds). Off-state bias stress was found to dramatically increase the threshold Vgs from 1 to 11 V, thereby increasing the voltage needed to turn off the TFT, without causing significant changes in on-state current or subthreshold swing. We developed local defect creation and charge trapping models for a technology computer-aided design simulation platform to understand the mechanisms underlying these observed effects. Using the model, we showed that off-state stress induces charge trapping within the local defects of a high electric field region in the TFT channel near the drain. This reduces the electric field and thermionic field-emission current, which in turn lowers the GIDL current by increasing threshold voltage Vgs.

High-Performance and Flexible Neodymium- Doped Oxide Semiconductor Thin-Film Transistors With Copper Alloy Bottom-Gate Electrode

In this letter, copper alloy Cu-0.3 wt.% Cr-0.2 wt.% Zr film was used as bottom-gate electrode for flexible neodymium-doped InZnO thin-film transistor (TFT) applications. The results showed that the sputtering power and annealing temperature of a Cu-Cr-Zr film on a polyimide (PI) substrate greatly affect the resistivity and the adhesion of the gate electrode. And the lowest resistivity as well as the best adhesion was obtained by increasing power and annealing temperature to 150 W and 350°, respectively, which was compatible with the optimum annealing temperature of Nd.IZO channel. Transmission electron microscopy showed the aggregation and migration of Cr and Zr in the Cu-Cr-Zr layer, which results in a high adhesion strength and conductivity. As a result, the Nd.IZO TFT with the Cu-Cr-Zr bottom-gate electrode was fabricated on the PI substrate and demonstrated a saturation mobility (μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) of 27.0 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s, an ON/OFF current ratio (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) of 107, a threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) of -0.1 V, and a subthreshold swing of 0.28 V/decade (no significant deterioration after 10k times repetitive bending stress). Furthermore, it exhibited a good mechanical bending stability of only a AV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift of -0.3/0.43 V after 10k times repetitive bending stress under negative/positive gate bias stress conditions for 5400 s.

A Compact Drain Current Model for Thin-Film Transistor Under Bias Stress Condition

Several basic thin-film transistor (TFT) models have been developed to describe the electrical characteristics of the device, most of them only considering the fundamental instability effects during static mode operation. However, representing the dynamic behavior is also a major concern for circuit design due to the electrical stress changes over time. Under this scenario, empirical models have been previously demonstrated to reproduce the current instability effects under specific conditions, but they do not consider in detail the phenomena taking place when the TFT is under dynamic electrical stress. In this paper, a new semianalytical model is presented to describe the dynamical behavior of the TFT under stress. This model considers the impact of the negative charge trapped at interfacial states as well as the mobility degradation. To validate the model, we compare the results with experimental measurements from our group, (using CdS TFT), and other semiconductor TFTs (a-Si:H, SnO, IZO, and IGZO) reported by other authors.

Effect of Ti Content on Physical Properties and Electrical Characteristics of High-k Yb2TiO5 Gate Dielectrics for InZnSnO Thin-Film Transistors

In this study, we investigated the impact of Ti content on structural properties and electrical characteristics of high-k Yb2TiO5 gate dielectrics for amorphous indium–zinc–tin-oxide (a-InZnSnO) thin-film transistor (TFT) devices. The Yb2TiO5 thin films with different Ti plasma conditions were integrated in metal-insulator-metal structures to check the electrical capabilities. The Yb2TiO5 a-InZnSnO TFT device fabricated at the 120 W condition exhibited excellent electrical characteristics in terms of a small threshold voltage (VTH) of 0.14 V, a low subthreshold swing of 202 mV/decade, a large field-effect mobility of 29.8 cm2/V-s, and a high Ion/Ioff current ratio of 2.7×108. In addition, the VTH stability of Yb2TiO5 a-InZnSnO TFT device was studied under both positive bias stress and negative bias stress conditions. The Yb2TiO5 thin film is a promising gate dielectric material for the fabrication of a-InZnSnO TFTs.

Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor

The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is the optimal device for the backplane of the organic light-emitting diode display. At the end the p-channel LTPS TFT fabrication, a charge-injection stress with a strong negative drain bias and a positive gate bias are applied to reduce the off-current by injecting electrons into the gate insulator near the drain. In this study, the charge density and the length of the charge-injection region in the gate insulator were estimated by comparing the measured TFT characteristics with the simulation models with various charge-injection lengths and charge densities. It was found that the effective length of the charge-injection region was 0.96 µm and the charge density was −3 × 1012/cm2 for the 2-µm-channel-length device when VGS was +20 V and VDS was −10 V under the charge-injection stress condition. It was also found, based on the analysis of the electric field distribution under the bias stress condition, that the charge density and the length of the charge-injection region were invariant against the channel length variation. Therefore, the measured TFT characteristics also accorded closely with the simulation models for different channel lengths, such as 4 and 10 µm, when the same characteristic values of the charge-injection region were employed.

Investigating the impact of the defect dynamic characteristics on the PBTI in the high-κ gate device

Recent device reliability studies on the metal/high-κ device observed the inter-convertible characteristics of the electron trap levels between the shallow and deep defect states under cyclic positive-bias temperature stressing. Although the oxygen vacancy and oxygen interstitial defect, being two typical types of defects in the high-κ oxide, have been criticized as the culprit for the device reliability issue and investigated in many simulations, all results have indicated that the defect levels induced by them were either too shallow or too deep and failed to explain the above experimental observation. Nevertheless, studies on the static characteristics of vacancy-interstitial (VO-Oi) model showed scattering distributed electron trap levels within the bandgap, making it as a promising defect type that can account for the above experimental observation. In this work, we investigated the dynamic characteristics of the VO-Oi defect pair under PBTI stress by tuning the relative position of VO and Oi. Our simulation results show multiple energy barriers for the structure transformation along the Oi migration path, and the charge trap level of the specific defect pair during the Oi migration is shown to be adjustable within the HfO2 band gap, depending on the Oi positions. These results depict an atomic picture to help us understand the defect electrical behavior under cyclic positive bias stress condition.

Systematic analysis of oxide trap distribution of 4H-SiC DMOSFETs using TSCIS and its correlation with BTI and SILC behavior

The spatial position and energy level of the effective oxide trap in SiC DMOSFET were investigated using Trap Spectroscopy by Charge Injection and Sensing (TSCIS) method. It was found that the oxygen vacancy traps at 1.7 eV above from the valence band of SiO2 make threshold voltage (Vth) shift under high negative gate bias stress condition. To further understanding the extracted oxide trap, the repetitive negative stress and recovery test at VG= ±40 V were executed. The results confirm that Vth and subthreshold swing (SS) change were caused by the process induced pre-existed hole traps instead of the stress induced trap generation. This hole trapping also reduced the Stress Induced Leakage Current (SILC) after the negative bias stress.

Impact of transient currents caused by alternating drain stress in oxide semiconductors

Reliability issues associated with driving metal-oxide semiconductor thin film transistors (TFTs), which may arise from various sequential drain/gate pulse voltage stresses and/or certain environmental parameters, have not received much attention due to the competing desire to characterise the shift in the transistor characteristics caused by gate charging. In this paper, we report on the reliability of these devices under AC bias stress conditions because this is one of the major sources of failure. In our analysis, we investigate the effects of the driving frequency, pulse shape, strength of the applied electric field, and channel current, and the results are compared with those from a general reliability test in which the devices were subjected to negative/positive bias, temperature, and illumination stresses, which are known to cause the most stress to oxide semiconductor TFTs. We also report on the key factors that affect the sub-gap defect states, and suggest a possible origin of the current degradation observed with an AC drive. Circuit designers should apply a similar discovery and analysis method to ensure the reliable design of integrated circuits with oxide semiconductor devices, such as the gate driver circuits used in display devices.

The Effect of the Rotary Steerable Spindle Structure Parameters on the Characteristics of Cantilever Bearing

In point-the-bit rotary steerable drilling system, the internal and outer diameter of the spindles and the fillet radius of the shaft shoulder have a great influence on the life of the cantilever bearing. According to the stress bias condition of the spindle, the 3D model of the cantilever bearing was established. Simulation analysis was conducted by loading boundary condition of the spindle under bias force. Therefore, the relationship between the internal and outer diameter of the spindle, the fillet radius of the shaft shoulder and the mechanical properties of the cantilever bearing were obtained. The results show that when the outer diameter of the spindle is constant, the deformation, the equivalent stress and the contact stress of the cantilever bearing reduce gradually with the increasing of the internal diameter of the spindle. When the internal diameter of the spindle is greater than 72 mm, the deformation of the roller shows a great fluctuation with the increasing of the fillet radius of the shaft shoulder. The life of the cantilever bearing first increases and then decreases with the increasing of the internal diameter of the spindle under the different fillet radius of the shaft shoulder. When the internal diameter of the spindle is constant, the life of the cantilever bearing first increases and then decreases with the increasing of the fillet radius of the shaft shoulder. The life of the cantilever bearing decreases gradually with the increasing of the outer diameter of the spindle. According to the research results, the optimal combination of internal diameter of the spindle and fillet radius of the shaft shoulder, outer diameter of the spindle and fillet radius of the shaft shoulder was offered, which can provide basis for the design of the spindle system.

Structural and electrical properties of high-κ CeTixOy, ErTixOy and YbTixOy gate dielectrics for InZnSnO thin film transistors

The structural properties and electrical characteristics of high–κ CeTixOy, ErTixOy and YbTixOy gate dielectrics for indium–zinc–tin–oxide (IZTO) thin-film transistors (TFTs) were investigated in this paper. We employed X-ray diffraction to determine the material phase and crystallinity, atomic force microscopy to examine the surface morphology of the dielectric films, and X-ray photoelectron spectroscopy to analyze the chemical feature of three films. The IZTO TFT incorporating a YbTixOy gate dielectric exhibited better electrical characteristics, such as a low threshold voltage (VTH) of 0.17 V, a large field-effect mobility of 20.8 cm2/V-s, a high Ion/Ioff ratio of 3 × 108, and a low subthreshold slope of 108 mV/decade, in comparison with those of other dielectrics. This result suggests that the YbTixOy dielectric possesses a smoother surface as well as a lower oxygen vacancy (or defect). Moreover, the VTH stabilities of IZTO TFT devices were investigated for positive bias stress and negative bias stress conditions.

Improved stability of aluminum co-sputtered indium zinc oxide thin-film transistor

Abstract 1 The electrical performance and bias stability of radio-frequency magnetron co-sputtered aluminum-indium-zinc oxide (Al-IZO) thin-film transistors (TFTs) were investigated, with respect to the atomic proportions of Al. Other parameters such as the indium-zinc oxide (IZO) target power, oxygen partial pressure, and initial and process pressures of the chamber were fixed. At a low Al atomic ratio (0.62 wt.%), the electrical performance and bias stability of the Al-IZO TFT were optimized because of the suppression of the generation of oxygen vacancies and the strong bond between Al and oxygen atoms (Al–O; 501.9 kJ/mol). Compared to pure IZO TFTs, the Al-IZO TFT exhibited a small shift in the threshold voltage under bias stress conditions. A higher threshold voltage of −2.24 V and an improved subthreshold swing of 1.35 V/dec were also observed. We demonstrated that the Al-IZO TFT could be a promising candidate for switching and driving operations in mass-produced display applications.

Recovery of Bias-Stress Ionized Igzo/SiO2 Interface States Via Cryogenic Relaxation

Indium gallium zinc oxide (IGZO) has been considered a potential replacement for hydrogenated amorphous silicon in TFT applications due to process compatibility and an order of magnitude improvement in electron channel mobility. However the mechanisms responsible for instability under bias-stress remain an active research topic. Silicon dioxide serving as the gate dielectric and back-channel passivation layer in bottom-gate IGZO TFTs results in high quality interfaces. Applied bias-stress conditions demonstrate a voltage shift that can be attributed to ionization and/or alteration of oxygen-related defects at these IGZO/SiO2interfaces. Bottom-gate IGZO TFTs with SiO2 gate dielectric and passivation layers were fabricated and tested under rigorous positive bias-stress (PBS) and negative bias-stress (NBS) conditions. The devices demonstrate good stability under PBS (t > 104 s), with minor distortion in the subthreshold region and a slight characteristic left-shift from an initial pre-stress state. This PBS-shift is attributed to a change in the energy distribution of defect states at the front-channel interface. During NBS the devices exhibited a significant left-shift (ΔV ~ 1-2 V), which is attributed to the transformation of neutral oxygen vacancies to ionized donor states at the back-channel interface. This transformation appears to improve the electrical homogeneity of the back-channel interface, inferred by a suppression of DIBL-like behavior. The NBS-shift was found to be reversible over long recovery times at room temperature. The recovery time was dramatically reduced when samples were subjected to cryogenic temperature (77 K), which represents an accelerated return to the pre-stress condition. TCAD simulation provides additional support to the interpretation of bias-induced stress on IGZO TFTs.

Bias stress effects in pentacene thin-film transistors with poly(methyl methacrylate) gate insulator

ABSTRACTWe demonstrated a bias stress effect on organic thin-film transistors (OTFTs) that causes device degradation, including a large shift in the threshold voltage and hysteresis in the transfer characteristics. Specifically, we analyzed the electrical characteristic variations in pentacene TFTs with a poly(methyl methacrylate) gate insulator under different bias stress conditions. We found that bias stress between the gate electrode and source/drain electrodes affects the charge transport properties, whereas bias stress between the source and drain electrodes influences the charge injection properties.

Drain-current Modeling of Sub-70-nm PMOSFETs Dependent on Hot-carrier Stress Bias Conditions

Stress drain bias dependent current model is proposed for sub-70-nm p-channel metal-oxide semiconductor field-effect transistors (pMOSFETs) under drain-avalanche-hot-carrier (DAHC-) mechanism. The proposed model describes the both on-current and off-current degradation by using two device parameters: channel length variation (ΔLSUBch/SUB) and threshold voltage shift (ΔVSUBth/SUB). Also, it is a simple and effective model of predicting reliable circuit operation and standby power consumption.

Modeling of asymmetric degradation based on a non-uniform electric field and temperature in amorphous In–Ga–Zn–O thin film transistors

We propose a new local degradation model based on a non-uniform increase in donor-like traps (DLTs) determined by distributions of an electric field and measured device temperature in amorphous In–Ga–Zn–O (a-IGZO) thin film transistors (TFTs). A systematic investigation of the degradation model reveals that vertical field-dependent DLTs are essential for modeling of measured asymmetric electrical characteristics between the source and drain after positive gate and drain bias stressing. An increased temperature due to self-heating is found to play a role in intensifying the asymmetric degradation. From the individual simulation of measured transfer curves at different stress times, the model parameters and an asymmetry index as a function of stress time are extracted. It is expected that this novel methodology will provide new insight into asymmetric degradation and be utilized to predict the influence of electric field and heat on degradation under various bias-stress conditions in a-IGZO TFTs.

Effects of various bias and temperature stresses on low-frequency noise properties of amorphous InGaZnO thin-film transistors

The authors investigate the low-frequency noise (LFN) properties of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under various bias and temperature stress conditions. After application of a gate-to-source bias (VGS) stress, the LFN properties hardly change. However, the LFN increases (especially, at low drain currents) after application of simultaneous VGS and drain-to-source bias (VDS) stresses. The LFNs measured before and after the stresses are well-fitted using the correlated number fluctuation-mobility fluctuation (Δn-Δμ) model, and the extracted values of the border trap density (NT) and the Coulomb scattering coefficient (αS) increase from 1018 eV−1 cm−3 and 105 V s/C to 1.53 × 1019 eV−1 cm−3 and 106 V s/C, respectively, after application of simultaneous gate- and drain-bias stresses (VGS = VDS = 20 V) for 1000 s at room temperature. This phenomenon is mainly attributed to the high electric-field-induced electronic trap generation inside the a-IGZO active layer. The increase in temperature during application of the simultaneous gate- and drain-bias stress accelerates the increase of LFN after the stress. The values of NT and αS are increased to 9.53 × 1019 eV−1 cm−3 and 8 × 106 V s/C, respectively, after the application of simultaneous gate- and drain-bias stresses for 1000 s at 80 °C, which are much higher than those extracted after the application of simultaneous gate- and drain-bias stresses at room temperature. This result shows that a high electric field combined with a high temperature significantly increases the density of electronic trap states which degrades the LFN properties in a-IGZO TFTs.

Impact of dual field plates on drain current degradation in InAlN/AlN/GaN HEMTs

InAlN/AlN/GaN HEMTs with both source and gate dual field-plates (FPs) are proposed. To investigate the influence of dual FPs on the devices characteristics, two types of devices with gate FP and without FPs were fabricated and tested. The devices were subjected to different kinds of short-term direct current bias (DC-bias) stress conditions. The results show that after the off-state bias stress, the drain current reduction rate of the devices with dual FPs was 3.32%, which was less than that in both devices with a gate FP of 7.57% and devices without FPs of 14.63%. The current collapse of the HEMTs with dual FPs was relieved due to the increase of electric field uniformity between the gate and drain. The degradation of the output characteristics was more serious after the on-state bias stress. In addition, the effects of bias stress on the transfer characteristics of the devices were studied, and the trapping processes under different stress conditions in the devices were discussed.