Recent technology advances have moved nonvolatile memory (NVM) to the forefront as key enablers of computing-in-memory for AI chips and nonvolatile logics for IoT devices. Among the family of NVMs, charge trapping memory (CTM) devices has been widely used to realize low power consumption and high speed. In conventional SONOS-type CTM, it becomes hard to improve the program and erase (P/E) speed by optimizing tunneling oxide thickness while still maintaining the retention properties [1]. To confront the challenges faced by SONOS memory, various high-κ dielectrics (Ta2O5, ZrO2, Y2O3, HfO2, etc.) with reduced equivalent oxide thickness (EOT) and improved charge-trapping density are proposed to achieve better memory performance [2-3]. Apart from the adoption of high-κ dielectrics for CTM, the adoption of channel material can also improve memory performance. Recently, some efforts on the utilization of SiGe channel with high electron/hole injection rate have been reported to improve P/E efficiency [4-5]. Electron/hole injection increased because SiGe has a smaller bandgap than silicon. As the electron/hole injection located at tunneling oxide/SiGe channel increases, the number of electrons tunneling through the tunneling oxide is increased and the P/E speed is improved. In this paper, we proposed a novel memory device with high-κ Al2O3/HfO2/Al2O3 nanolaminate, SiGe channel and high work function tungsten metal gate. Finally, a novel charge trapping memory with the structure of [W/TiN]/Al2O3/HfO2/Al2O3/SiGe (named as MAHASG in short) is obtained. MAHASG memory devices with SiGe buried channel, as shown in Fig. 1, were fabricated on p-type Si wafer. Prior to SiGe epitaxial growth, the surface oxide was removed by using a dilute HF 1% solution. Then a 20 nm-thick SiGe epi-layer with 30% Ge content was deposited using reduced pressure chemical vapor deposition (RPCVD). After SiGe epitaxial growth, a 3 nm Al2O3 tunneling layer was deposited by atomic layer deposition (ALD) at a substrate temperature of 300℃. Subsequently, the 7 nm HfO2 film was grown by ALD as the charge trapping layer. Then, another 6-nm thick Al2O3 layer was deposited by ALD in situ as the blocking layer. After that high-κ dielectrics deposition, a post deposition anneal was performed for 15 s at the temperature of 450 °C in N2 atmosphere to improve the material quality of the high-κ dielectrics. Afterwards, TiN/W was deposited as the control gate by ALD and patterned by dry etch, followed by sputtering aluminum as the backside contact. Finally, a metallization process by using forming gas (5% H2, 95% N2) was applied for 30 min and at 400℃. Control samples without HfO2 layer were also fabricated using identical procedure. The resulting structure is shown in Fig 1. It should be noted that the whole process is simple and fully compatible with conventional CMOS technology. The memory characteristics for the MAHASG memory devices were investigated by a Keithley 4200 semiconductor characterization system. In order to study the charge trapping characteristics, bi-directional capacitance-voltage (C-V) curves were obtained by applying different sweeping gate voltages ranging from ±3 V to ±10 V at a frequency of 800 KHz, as shown in Fig. 2. A counterclockwise hysteresis was obtained during voltage sweep from inversion region to accumulation region and then back to inversion region. The memory window is defined as the flat-band voltage shift (ΔVFB) between the forward and backward sweep curves. There is no obvious memory window in the voltage sweep of ±3 V, indicating that charge trapping and de-trapping hardly take place in this voltage sweep range. When the voltage sweep range increases to ±6 V, the memory window is obvious. In a voltage sweep range of ±10 V, a large memory window of about 4 V can be obtained, as indicated in Fig 3. The energy band diagram of the MAHASG memory device is shown in Fig 4. The barrier height for electron injection from the SiGe channel to the HfO2 layer is about 2.74 eV, which is slightly smaller than that of the normal Si-SiO2 system (3.25 eV). This means that a higher charge tunneling probability and program efficiency occurred in this memory structure. In conclusion, this study provides a promising route of future nano-scaled flash memory operation, utilizing high-mobility channel and high-κ materials.
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Apr 5, 2022
Takuya Izumi + 3
Open Access
