Back-gated Graphene Field-effect Transistors Research Articles

CMOS-Compatible Synthesis of Large-Area, High-Mobility Graphene by Chemical Vapor Deposition of Acetylene on Cobalt Thin Films

We demonstrate the synthesis of large-area graphene on Co, a complementary metal-oxide-semiconductor (CMOS)-compatible metal, using acetylene (C(2)H(2)) as a precursor in a chemical vapor deposition (CVD)-based method. Cobalt films were deposited on SiO(2)/Si, and the influence of Co film thickness on monolayer graphene growth was studied, based on the solubility of C in Co. The surface area coverage of monolayer graphene was observed to increase with decreasing Co film thickness. A thorough Raman spectroscopic analysis reveals that graphene films, grown on an optimized Co film thickness, are principally composed of monolayer graphene. Transport properties of monolayer graphene films were investigated by fabrication of back-gated graphene field-effect transistors (GFETs), which exhibited high hole and electron mobility of ∼1600 cm(2)/V s and ∼1000 cm(2)/V s, respectively, and a low trap density of ∼1.2 × 10(11) cm(-2).

Graphene field effect transistor improvement by graphene–silicon dioxide interface modification

The dependence of the electrical properties of backgate graphene field effect transistor on the silicon surface preparation techniques prior to graphene exfoliation was studied. The influence of standard wet chemical cleaning, with and without a finishing step in an oxygen plasma are compared to a surface preparation finished by hexamethyldisilazane deposition. The carrier drift mobility of backgate p-channel graphene transistors was determined from the measured transconductance. The backgate graphene field effect transistor fabricated by bonding graphene on silicon dioxide modified with hexamethydisilazane showed an improved carrier drift mobility at low electric fields and higher transconductance.

Compact Virtual-Source Current–Voltage Model for Top- and Back-Gated Graphene Field-Effect Transistors

This paper presents a compact model for the current-voltage characteristics of graphene field-effect transistors (GFETs), which is based on an extension of the “virtual-source” model previously proposed for Si MOSFETs and is valid for both saturation and nonsaturation regions of device operation. This GFET virtual-source model provides a simple and intuitive understanding of carrier transport in GFETs, allowing extraction of the virtual-source injection velocity <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VS</sub> , which is a physical parameter with great technological significance for short-channel graphene transistors. The derived <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characteristics account for the combined effects of the drain-source voltage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VDS</i> , the top-gate voltage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VTGS</i> , and the back-gate voltage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VBGS</i> . With only a small set of fitting parameters, the model shows excellent agreement with experimental data. It is also shown that the extracted virtual-source carrier injection velocity for graphene devices is much higher than in Si MOSFETs and state-of-the-art III-V heterostructure FETs with similar gate length, demonstrating the great potential of GFETs for high-frequency applications. Comparison with experimental data for chemical-vapor-deposited GFETs from our group and epitaxial GFETs in the literature confirms the validity and flexibility of the model for a wide range of existing GFET devices.

Effect of Top Dielectric Medium on Gate Capacitance of Graphene Field Effect Transistors: Implications in Mobility Measurements and Sensor Applications

We have carried out Hall measurement on back-gated graphene field effect transistors (FET) with and without a top dielectric medium. The gate efficiency increases by up to 2 orders of magnitude in the presence of a high κ top dielectric medium, but the mobility does not change significantly. Our measurement further shows that the back-gate capacitance is enhanced dramatically by the top dielectric medium, and the enhancement increases with the size of the top dielectric medium. Our work strongly suggests that the previously reported top dielectric medium-induced charge transport properties of graphene FETs are possibly due to the increase of gate capacitance, rather than enhancement of carrier mobility.

A high-performance top-gate graphene field-effect transistor based frequency doubler

A high-performance top-gate graphene field-effect transistor (G-FET) is fabricated, and used for constructing a high efficient frequency doubler. Taking the advantages of the high gate efficiency and low parasitic capacitance of the top-gate device geometry, the gain of the graphene frequency doubler is increased about ten times compared to that of the back-gate G-FET based device. The frequency response of the frequency doubler is also pushed from 10 kHz for a back-gate device to 200 kHz, at which most of the output power is concentrated at the doubled fundamental frequency of 400 kHz.

Ambient and temperature dependent electric properties of backgate graphene transistors

AbstractThe electrical behavior of backgate graphene field effect (GFET) transistor was studied at different ambient conditions. Backgate p‐channel GFET transistors were fabricated on oxidized silicon wafers by exfoliation of graphite. The carrier mobilities were determined from the measured transconductance. For all ambients investigated (N2, Ar, and air), the graphene transistors show enhanced mobilities at elevated temperatures. This behavior can be explained by a stronger screening of scattering centers, i.e., defects in graphene and at the graphene oxide interface, with increasing temperature. For operation in air the transistors showed a higher transconductance compared to the operation in nitrogen and argon due to the strong acceptor‐like behavior of gases adsorbed on the graphene surface. magnified image Effect of temperature and ambient on the output characteristic of a backgate GFET.

Contact resistance in few and multilayer graphene devices

The contact resistance of metals on backgated graphene field-effect transistors is studied. The residual resistance obtained at high backgate voltage is found to be in excellent agreement with the extracted values of contact resistance from transfer length measurements on graphene flakes. The contact resistance is found to be a significant contributor to the total resistance of graphene-based devices. The specific contact resistance is shown to be independent of the applied backgate voltage and the number of graphene layers.

N-Type Behavior of Graphene Supported on Si/SiO2 Substrates

Results are presented from an experimental and theoretical study of the electronic properties of back-gated graphene field effect transistors (FETs) on Si/SiO(2) substrates. The excess charge on the graphene was observed by sweeping the gate voltage to determine the charge neutrality point in the graphene. Devices exposed to laboratory environment for several days were always found to be initially p-type. After approximately 20 h at 200 degrees C in approximately 5 x 10(-7) Torr vacuum, the FET slowly evolved to n-type behavior with a final excess electron density on the graphene of approximately 4 x 10(12) e/cm(2). This value is in excellent agreement with our theoretical calculations on SiO(2), where we have used molecular dynamics to build the SiO(2) structure and then density functional theory to compute the electronic structure. The essential theoretical result is that the SiO(2) has a significant surface state density just below the conduction band edge that donates electrons to the graphene to balance the chemical potential at the interface. An electrostatic model for the FET is also presented that produces an expression for the gate bias dependence of the carrier density.