Back-end Module Research Articles

Metallization requirements for sub-micron CMOS logic

DRAM memory fabrication has been the driving force behind CMOS technology development until now. The emphasis in process development has mostly been on the enhancement of lithographic resolution and transistor definition. With the emergence of more complicated CMOS logic devices, however, an increasing fraction of the resources spent on process development is being allocated to so-called back-end features, such as interconnection and planarization. Some aspects of CMOS logic as a technology driver are discussed. Attention is paid to the role of European projects (JESSI, ESPRIT) in the generation and assessment of new technologies. Various application fields are reviewed. The various back-end modules (pre-metal and inter-metal planarization, contacts and vias, interconnect metal, silicides, barrier layers, anti-reflective coatings) are considered.

Application-specific architectural methodologies for high-throughput digital signal and image processing

An attempt has been made to classify the architectural styles suited for application-specific high-throughput DSP (digital signal processing) applications. In principle, they can be classified between the two extremes of cooperating multiplexed data paths and regular arrays which adopt hard-wired control flow with low hardware sharing. Three DSP subclasses have been identified according to the required sample rate in combination with the regularity and modularity of the flowgraph and the types of operation which are involved, such as straightforward arithmetic or complex decision making with loops and branches. Correspondingly, three architectural strategies have been identified as efficient candidates for realization, namely, microcoded multiprocessors, cooperating multiplexed data paths, and regular arrays. Architectures exploiting large hardware-sharing ratio's which are more suited for the back-end modules in the target DSP system are investigated. Realistic test vehicles are discussed in order to evaluate the alternatives. Moreover, guidelines have been extracted to select such an ASIC (application-specific integrated circuit) architecture. These are dependent on the required throughput, the structure of the algorithm, and the corresponding signal flowgraph.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>