Back-channel Interface Research Articles

Impact of Al2O3 spacers on the improvement in short-channel effects for the mesa-shaped vertical-channel In-Ga-Zn-O thin-film transistors with a channel length below 100 nm

To achieve a channel length scaling and an improvement in short-channel effect (SCE) for the mesa-shaped vertical thin-film transistors (VTFTs) using In-Ga-Zn-O (IGZO) channels prepared by atomic layer deposition (ALD), the impacts of two strategic approaches were investigated: the introduction of an ALD Al2O3 spacer and the modulation of ALD oxidants. The Al2O3 spacers were patterned with sound profiles by means of a hybrid-etching technique combining a wet- and plasma dry-etching processes to form vertical sidewalls corresponding to a channel length. For the cases when the Al2O3 spacers were prepared with H2O oxidant, the IGZO VTFT with an In/Ga ratio of 1.7 showed the degradations in device characteristics including a turn-on voltage (VON) of −8.0 V and a subthreshold swing (SS) of 1.50 V/dec. When the In/Ga ratio was increased to 2.9, the device failed to be operated with conductive properties. The excess hydrogen contained within the Al2O3 spacer was suggested to be thermally diffused into the IGZO from the back-channel interface, leading to marked increase in the number of conduction carriers within the channel. To suppress the doping effect of hydrogen from the spacer, the ALD oxidant was strategically modulated to O3. As results, the VON and SS of the IGZO VTFT were markedly improved to be −2.0 V and 0.483 V/dec, respectively. Additionally, the drain induced barrier lowering coefficient was also significantly enhanced from 2.9 to 0.13 V/V, demonstrating the excellent immunity against the SCE for the IGZO VTFTs with nanoscale channel lengths. It was concluded from these findings that the spacer engineering can be one of the most important guides for the implementation of IGZO VTFTs with channel lengths below 100 nm.

Effect of N <sub>2</sub>O treatment on performance of back channel etched metal oxide thin film transistors

In this paper, the rare earth element praseodymium-doped indium tin zinc oxide semiconductor is used as the channel layer of the thin film transistor, and the aluminum oxide-based wet back channel etched thin film transistor is successfully prepared. The effect of N <sub>2</sub>O plasma treatment on the back-channel interface of thin film transistor is studied, and the effect of treatment power and time on device performance are studied in detail. The results show that the good device performance can be obtained under certain power and time treatment, and the prepared device has good thermal stability of positive bias and negative bias under light conditions. The results from high-resolution transmission electron microscopy show that the amorphous structure of the metal oxide semiconductor material can effectively resist the wet etchant, and that no obvious component segregation phenomenon is found. Further, X-ray photoelectric spectroscopy tests show that N <sub>2</sub>O plasma treatment can form an oxygen-rich, low-carrier-concentration interface layer at the interface. On the one hand, it can effectively resist the damage of the back channel caused by the plasma of plasma enhanced chemical vapor deposition (PECVD), and on the other hand, it acts as a passivation body of hydrogen from PECVD plasma, suppressing the generation of low-level donor state of hydrogen. This study provides an important reference for low-cost, high-efficiency thin film transistor performance optimization methods.

Improving the electrical performance of vertical thin-film transistor by engineering its back-channel interface

This paper reports the effect of the properties of a back-channel region of a vertical thin-film transistor (VTFT) on its electrical performance. The deposition of a thin layer of SiO2 on a damaged back-channel region was found to improve the subthreshold swing (SS) from 0.25 to 0.12 V/dec, while maintaining the field-effect mobility. Detailed analysis of the surface morphology of the back-channel region revealed that the application of advanced photolithography resulted in a significantly smoother back-channel interface, yielding higher-performing VTFTs. The VTFT fabricated using a high-resolution, stepper photolithography system exhibited a linear mobility (μlin) of 14.60 cm2/Vs, a saturation mobility (μsat) of 23.69 cm2/Vs, and an SS value of 0.13 V/dec. Meanwhile, the VTFT fabricated using a standard projection aligner displayed μlin, μsat, and SS values of 5.74 cm2/V·s, 13.87 cm2/V·s, and 0.27 V/dec, respectively. These results revealed the electrical performance of the VTFT to be strongly influenced by the properties of the back-channel region.

A Unified Degradation Model of Elevated-Metal Metal Oxide (EMMO) TFTs Under Positive Gate Bias With or Without an Illumination

Degradations of elevated-metal metal oxide (EMMO) thin-film transistors (TFTs) under positive bias stress (PBS) and positive bias illumination stress (PBIS) are systematically investigated and compared. An intrinsic correlation between PBS and PBIS degradation is demonstrated. Continuous negative threshold voltage ( ${V}_{\text {th}}$ ) shift is observed under both stresses, with similar time-dependent $V_{\text {th}}$ shift and recovery behavior. Characterization parameters for dependencies of ${V}_{\text {th}}$ shift on both stress ${V}_{G}$ and temperature are also very close for the two degradations. PBS and PBIS degradation of EMMO TFTs and their correlation can be consistently understood based on a unified model, which emphasizes stress-induced accumulation of doubly-ionized ${V}_{O}$ traps at the back-channel interface, and is verified with simulation.

Abnormal threshold voltage shift caused by trapped holes under hot-carrier stress in a-IGZO TFTs

In the investigation of the reliability of a back-channel-etching type amorphous InGaZnO thin film transistor, we found that hot carrier stress has caused an abnormal parallel negative threshold voltage shift in the ID–VG measurement. An electrical measurement method named drain stress was established to investigate this instability. Through the analysis of recovery behavior, gate bias stress and Silvaco simulation, we confirmed that holes from the drain side inject into the passivation layer and/or back-channel interface region rather than into the gate insulator under the transverse electric field. A physical model is proposed to verify this electrical degradation behavior. This work demonstrates that drain stress is valuable in examining the quality of the passivation layer in thin film transistors.

Flash Lamp Annealed Polycrystalline Silicon TFT Dependence on Surface Morphology and the Back-Channel Material Interface

This work studies the operation of polycrystalline silicon p-channel TFTs prepared via Flash Lamp Annealing (FLA). Silicon nitride was investigated as a back-channel interface layer to suppress void formation via dewetting of molten silicon. Predefined polygons of amorphous silicon were crystallized on display glass using single-pulse FLA exposure. Two distinct surface morphologies were realized within the same exposed region as a result of the underlying silicon nitride film and localized variation in the substrate thermal contact during PECVD deposition of amorphous silicon. While both resulting morphologies have polysilicon grains on micron scale, differences in TFT electrical behavior appear to coincide with differences in grain structure and boundary regions. The electrical results also indicate inferior electrical performance in response to the back-channel silicon nitride in comparison to results demonstrated on SiO2. Extracted parameters provide a quantitative assessment of the device operation as related to surface morphology and the back-channel material interface.

Channel-Length Dependent Performance Degradation of Thermally Stressed IGZO TFTs

The focus of this work is on the performance degradation of thermally stressed IGZO TFTs with SiO2 for both the gate dielectric and back-channel passivation material. The TFT fabrication process included a post-passivation 400 °C O2 anneal to adjust the IGZO semiconductor properties. I-V characteristics of TFTs with bottom-gate (BG) and double-gate (DG) electrode configurations were observed to left-shift and degrade with 200 °C hotplate treatments as shown in Fig. 1. The mechanism causing the instability is not completely understood, however experimental results indicate the instability occurs either directly or indirectly due to the influence of H2O within the passivation oxide above the IGZO channel region. The instability of DG devices was consistently more pronounced, suggesting a reaction between H2O and the aluminum top-gate electrode resulting in the liberation of monatomic hydrogen. This interpretation is supported by complementary experiments on MOS capacitors fabricated on bulk silicon substrates. The application of an alumina capping layer deposited by atomic layer deposition (ALD) was successful in improving thermal stability, with representative results shown in Fig. 2. While most BG capped devices remained stable over several successive thermal treatments, DG devices demonstrated the onset of degradation with noted variation in both the time required and occurrence frequency. The analysis revealed an unanticipated dependence on channel length, with long-channel devices (L = 48 µm) being much more prone to an early onset of degradation compared to shorter devices (L = 12 µm) as shown in Fig. 2. With H2O remaining as the expected origin of thermal instability, a hypothesis has been developed to explain the observed channel length dependence. The results are consistent with the molybdenum source/drain contact regions acting as gettering sites for H2O molecules during the 400 °C annealing process. The removal of H2O from the back-channel region is a two dimensional process limited by the diffusivity of water, with the process more complete in short channel devices. Remaining H2O molecules at or near the back-channel interface in long-channel devices are able to migrate during thermal stress treatments, establishing complete coverage on devices that experience degradation. Experiments which explore the addition of getter features on or adjacent to the back-channel region, as illustrated in Fig. 3, in addition to localized materials analysis techniques such as secondary ion mass spectroscopy (SIMS) will provide additional evidence either in support or denial of the proposed hypothesis. Figure 1

Drain Current Stress-Induced Instability in Amorphous InGaZnO Thin-Film Transistors with Different Active Layer Thicknesses.

In this study, the initial electrical properties, positive gate bias stress (PBS), and drain current stress (DCS)-induced instabilities of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with various active layer thicknesses (TIGZO) are investigated. As the TIGZO increased, the turn-on voltage (Von) decreased, while the subthreshold swing slightly increased. Furthermore, the mobility of over 13 cm2·V−1·s−1 and the negligible hysteresis of ~0.5 V are obtained in all of the a-IGZO TFTs, regardless of the TIGZO. The PBS results exhibit that the Von shift is aggravated as the TIGZO decreases. In addition, the DCS-induced instability in the a-IGZO TFTs with various TIGZO values is revealed using current–voltage and capacitance–voltage (C–V) measurements. An anomalous hump phenomenon is only observed in the off state of the gate-to-source (Cgs) curve for all of the a-IGZO TFTs. This is due to the impact ionization that occurs near the drain side of the channel and the generated holes that flow towards the source side along the back-channel interface under the lateral electric field, which cause a lowered potential barrier near the source side. As the TIGZO value increased, the hump in the off state of the Cgs curve was gradually weakened.

Effects of Backchannel Passivation on Electrical Behavior of Hetero-Stacked a-IWO/IGZO Thin Film Transistors

This study investigates the effects of positive gate-bias stress (PGBS) on the electrical instability of amorphous InWO/InGaZnO (a-IWO/IGZO) stacked thin-film transistors (TFTs) with a backchannel passivation layer of SiO2 or Al2O3 film. After the application of PGBS to a-IWO/IGZO TFTs with an SiO2 passivation layer, abnormal negative threshold voltage (Vth) shifts were observed, while positive Vth shifts were observed in the TFTs with an Al2O3 passivation layer. This unusual positive bias instability is explained using a two-step electrical degradation behavior model, including both electron trapping and moisture absorption at the damaged back channel interface between a-IWO/IGZO TFTs and the SiO2 passivation layer.

Positive gate bias stress-induced hump-effect in elevated-metal metal–oxide thin film transistors**Project supported by the Science and Technology Program of Suzhou City, China (Grant No. SYG201538) and the National Natural Science Foundation of China (Grant No. 61574096).

Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium–gallium–zinc oxide thin film transistor, which adopts an elevated-metal metal–oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction. The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the backchannel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device (L = 2 μm). It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.

High Mobility Amorphous Indium-Gallium-Zinc-Oxide Thin-Film Transistor by Aluminum Oxide Passivation Layer

This letter demonstrates a high-mobility amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) with aluminum oxide (Al2O3) passivation layer by radio frequency (RF) magnetron sputtering and copper (Cu) source/drain electrodes. The fabricated a-IGZO TFT exhibited 20 times higher saturation mobility (142.0 cm2/Vs) than the reference device without Al2O3 passivation layer. The generation of metallic indium at the back-channel interface caused by the bombardment of the sputtered Al2O3 is the main principle for the remarkable enhancement of saturation mobility. Furthermore, the a-IGZO TFT maintains high mobility and air-ambient-stable characteristics up to four months in ambient conditions.

Recovery of Bias-Stress Ionized Igzo/SiO2 Interface States Via Cryogenic Relaxation

Indium gallium zinc oxide (IGZO) has been considered a potential replacement for hydrogenated amorphous silicon in TFT applications due to process compatibility and an order of magnitude improvement in electron channel mobility. However the mechanisms responsible for instability under bias-stress remain an active research topic. Silicon dioxide serving as the gate dielectric and back-channel passivation layer in bottom-gate IGZO TFTs results in high quality interfaces. Applied bias-stress conditions demonstrate a voltage shift that can be attributed to ionization and/or alteration of oxygen-related defects at these IGZO/SiO2interfaces. Bottom-gate IGZO TFTs with SiO2 gate dielectric and passivation layers were fabricated and tested under rigorous positive bias-stress (PBS) and negative bias-stress (NBS) conditions. The devices demonstrate good stability under PBS (t > 104 s), with minor distortion in the subthreshold region and a slight characteristic left-shift from an initial pre-stress state. This PBS-shift is attributed to a change in the energy distribution of defect states at the front-channel interface. During NBS the devices exhibited a significant left-shift (ΔV ~ 1-2 V), which is attributed to the transformation of neutral oxygen vacancies to ionized donor states at the back-channel interface. This transformation appears to improve the electrical homogeneity of the back-channel interface, inferred by a suppression of DIBL-like behavior. The NBS-shift was found to be reversible over long recovery times at room temperature. The recovery time was dramatically reduced when samples were subjected to cryogenic temperature (77 K), which represents an accelerated return to the pre-stress condition. TCAD simulation provides additional support to the interpretation of bias-induced stress on IGZO TFTs.

Investigation on the Gate Electrode Configuration of IGZO TFTs for Improved Channel Control and Suppression of Bias-Stress Induced Instability

The classic bottom-gate IGZO TFT structure requires a passivation layer application over the back-channel for stability and process integration. However, the passivation material deposition process usually degrades the interface quality and presents defect states at the back-channel interface which are difficult to compensate by a controlling gate electrode positioned on the opposite side of the semiconductor. A top-gate configuration takes advantage of a superior back-channel interface between the substrate and the sputtered IGZO film. The gate dielectric must be deposited on the IGZO which presents an inferior interface, however the influence of defect states can be reduced by annealing in an oxidizing ambient prior to the gate electrode deposition. As positioned directly above the inferior interface, there is an improvement in the ability of the gate potential to control the device operation in the presence of remaining defect states. This work presents an investigation on TFTs which have been fabricated with very similar process flows with the exception of the placement of the gate electrode. Bottom-gate TFTs with back-channel passivation that demonstrate good performance and resistance to aging have been realized, however bias-stress stability continues to remain a challenge. Top-gate TFTs have demonstrated improvement in the uniformity of device operation as well as bias-stress stability, and have the potential to offer an advantage in off-state performance (see fig. 1). Double-gate TFTs take further advantage of improved electrostatics, but present additional challenges in process integration. Results from all three gate electrode configurations will be compared. Device testing performed over a temperature range from 10 K to 400 K allows a comprehensive assessment of transport behavior (see fig. 2), with results used to refine a material and device model for TCAD simulation. Figure 1

Influence of Carrier Concentration at Front- and Back-Channel on Transfer Characteristics of Bottom-Gate Ιn-Ga-Zn-O Thin-Film Transistors

High drain current (I DS) is required for thin-film transistors (TFTs) to drive next-generation high-definition and large-screen flat panel displays (FPDs). An In-Ga-Zn-O (IGZO) TFT has received considerable attention for the next-generation FPDs because it has high electron mobility (µ >10 cm2V-1s-1) and large area uniformity [1]. Previously, we reported that the I DS and an apparent field-effect mobility (µ FE) of IGZO TFT was enhanced owing to a reduction of an effective channel length (L eff) when the sheet carrier concentration (N s) at back-channel interface increased [2]. However, it has not clarified the influence of carrier concentration at either front- or back-channel on transfer characteristics of the IGZO TFT. In this research, an influence of N s at front- and back-channel on transfer characteristics of bottom-gate IGZO TFT was analysed by device simulator (ATLAS). First, physical parameters of the IGZO TFT was defined to reproduce the transfer characteristics of actual fabricated TFT which was used as reference [3] (denoted hereafter as ref.-TFT). Next, a thin layer, that was modulated the N s from 6.8×1011 to 2.5×1014 cm-2, was set at the back-channel region of the TFT as shown in Fig.1 (a) (denoted hereafter as MD-TFTs). Fig.1 (b) shows the comparison of transfer characteristics of the TFTs. From Fig.1 (b), the I DS of MD-TFTs drastically increased as compared with the ref.-TFT. In addition, it can be seen that the I DS enhancement was increased with increasing N s at back-channel. From these I DS enhancement, an apparent µ FE calculated from transfer characteristics enhanced for the MD-TFTs as shown in Fig1 (c). For the case of the N s was 6.8×1011 cm-2, an apparent µ FE was increased to 29.8 cm2V-1s-1 for sub-threshold region, whereas an apparent µ FE was almost the same as ref.-TFT at on (V GS=+20 V) region. When the N s further increased to 2.5×1013 cm-2, the overestimation of an apparent µ FE was observed for both sub-threshold and on (V GS=+20 V) region. To investigate the reason for changing apparent µ FE of MD-TFT with 6.8×1011 cm-2 with gate-voltage, current density in MD-TFT with N s of 6.8×1011 cm-2 was simulated as shown Figs.2 (a) and 2 (b). In case of sub-threshold region (V GS=+3 V), the L eff at front-channel interface drastically reduce as compared with the mask-defined channel length (L m). On the other hand, the L eff at the on (V GS=+20 V) region was unchanged to the L m. As a consequence of reduction of the L eff, it was increased to apparent µ FE of MD-TFT with 6.8×1011 cm-2 at the sub-threshold region. These results suggested that N s difference between back- and front-channel interfaces are strongly related to the carrier transport mechanism in MD-TFTs, because the carrier transport path was changed by increasing N s at front-channel with gate-voltage. As a results of further analysis by device simulator, it was revealed that the enhancement of I DS and an apparent µ FE were induced owing to the difference of N s between back- and front-channel interfaces. Detail of the results will be presented at the conference. [1] T. Kamiya, K. Nomura and H. Hosono, “Present status of amorphous In-Ga-Zn-O thin-film transistors” Sci. Technol. Adv. Mater, Vol.11, pp.044305-044328, Sept. 2010. [2] D. Koretomo, T. Toda, D. Wang and M.Furuta, “Anomalous Increase of Field-Effect Mobility in In-Ga-Zn-O Thin-Film Transistors Caused by Dry-Etching Damage Through Etching-Stopper” presented at 35-4, 15th Int. Conf. IMID, 2015.[3] Mutsumi Kimura, “Practical Guidance of Parameter Extraction for Device Simulation of Thin-Film Transistors”, J. Appl. Phys., vol.51, pp.054302-1-054302-5, April 2012 Figure 1

Investigation on Alumina Passivation for Improved IGZO TFT Performance

A study of the influence of back-channel alumina passivation on the operation of bottom-gate IGZO TFTs is presented. TFTs without any passivation material deposited typically exhibit best-case initial results. Regardless a passivation layer is required for device stability and process integration. The impact of passivation using alumina deposited via electron beam evaporation and atomic layer deposition (ALD) has been investigated. A decrease in subthreshold slope and channel mobility on certain treatment combinations is attributed to an inferior IGZO/alumina back-channel interface. A two-step passivation process has been developed which offers back-channel protection during device fabrication, and remains compatible with an oxidizing ambient anneal. Modifications in the passivation and annealing procedures and process integration details have resulted in a marked improvement in the performance of alumina passivated devices, with demonstrated resistance to aging.

Investigation on Alumina Passivation for Improved IGZO TFT Performance

A study on the influence of the back-channel interface on the operation of bottom-gate indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) is presented. TFTs without any passivation material deposited typically exhibit best-case initial results. However a passivation layer is required for device stability and process integration. The surface of IGZO is very sensitive to deposition conditions of passivation materials; in general additional oxygen vacancies are created which renders the IGZO conductive. Annealing in an oxidizing ambient may reverse this effect and result in devices which exhibit appropriate semiconducting properties. The impact of passivation using alumina deposited via electron beam evaporation and atomic layer deposition (ALD) has been investigated. A decrease in TFT channel mobility is attributed to the IGZO/alumina back-channel interface degradation associated with the alumina passivation process. Low temperature ALD (e.g. T ≤ 150°C) has been explored to minimize this degradation effect. Pre-passivation and post-passivation anneal treatments have also been explored to better understand the mechanisms involved. Improvements in the back-channel interface were shown to depend on the thickness and deposition method of the alumina passivation layer. Temperature-dependent measurements reveal differences in electrical characteristics including bias-stress stability. Modifications in the passivation and annealing procedures and process integration details have resulted in a marked improvement in the performance of passivated devices.

Performance and Stability Improvements of Back-Channel-Etched Amorphous Indium–Gallium–Zinc Thin-Film-Transistors by CF4+O2 Plasma Treatment

The performance and stability improvement of back-channel-etched amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs) by post CF4+O2 plasma treatment is investigated. It is revealed that the metal residue of the wet-etching of source/drain electrodes degrades TFT performance and aggravates the positive threshold voltage ( $V_{\mathrm {th}})$ shift under positive gate bias stress. It is demonstrated that the CF4+O2 plasma treatment effectively removes the metal residue and remarkably improves device performance and the $V_{\mathrm {th}}$ stability. This improvement is attributed to oxygen vacancy repairing at the back channel interface of the a-IGZO TFT by the O free radicals generated by the O2 plasma.

Back-channel-etch amorphous indium–gallium–zinc oxide thin-film transistors: The impact of source/drain metal etch and final passivation

We report on the impact of source/drain (S/D) metal (molybdenum) etch and the final passivation (SiO2) layer on the bias-stress stability of back-channel-etch (BCE) configuration based amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs). It is observed that the BCE configurations TFTs suffer poor bias-stability in comparison to etch-stop-layer (ESL) TFTs. By analysis with transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS), as well as by a comparative analysis of contacts formed by other metals, we infer that this poor bias-stability for BCE transistors having Mo S/D contacts is associated with contamination of the back channel interface, which occurs by Mo-containing deposits on the back channel during the final plasma process of the physical vapor deposited SiO2 passivation.

Comparative study of source–drain contact metals for amorphous InGaZnO thin‐film transistors

AbstractIn this work, we compared the thin‐film transistor (TFT) characteristics of amorphous InGaZnO TFTs with six different source–drain (S/D) metals (MoCr, TiW, Ni, Mo, Al, and Ti/Au) fabricated in bottom‐gate bottom‐contact (BGBC) and bottom‐gate top‐contact (BGTC) configurations. In the BGTC configuration, nearly every metal can be injected nicely into the a‐IGZO leading to nice TFT characteristics; however, in the BGBC configuration, only Ti/Au is injected nicely and shows comparable TFT characteristics. We attribute this to the metal‐containing deposits in the channel and the contact oxidation during a‐IGZO layer sputtering in the presence of S/D metal. In bias‐stress stability, TFTs with Ti/Au S/D metal showed good results in both configurations; however, in the BGTC configuration, not all the TFTs showed as good bias results as Ti/Au S/D metal TFTs. We attribute this to backchannel interface change, which happened because of the metal‐containing deposits at the backchannel during the final the SiO2 passivation.

Negative Bias and Illumination Stress Induced Electron Trapping at Back-Channel Interface of InGaZnO Thin-Film Transistor

Double-sweeping gate voltage mode and positive gate pulse mode were used to investigate the mechanism of negative bias and illumination stress (NBIS) induced hysteresis in bottom-gate InGaZnO TFTs. Threshold voltages (Vth) in reverse measurement shifted positively and were well fitted to a stretched-exponential equation under various gate bias stress conditions. “Hump” effect appeared in the forward measurement and hysteresis gradually increased with stress time. The results indicate that trapped electrons at back interface, trapped holes at front interface and the generation of donor-like states in IGZO bulk channel were reasons for instability of IGZO TFTs under NBIS. © 2014 The Electrochemical Society. [DOI: 10.1149/2.010403ssl] All rights reserved.