Auxiliary Path Research Articles

PhaseDCN: A Phase-Enhanced Dual-Path Dilated Convolutional Network for Single-Channel Speech Enhancement

Recent deep neural network (DNN) based single-channel speech enhancement methods have achieved remarkable results in the time-frequency (TF) magnitude domain. To further improve the quality and intelligibility of enhanced speech, the attention to phase enhancement is also increasing. In this paper, we propose a novel dilated convolutional network (DCN) model to simultaneously enhance the magnitude and phase of noisy speech. Unlike the direct complex spectral mapping methods, we take the complex spectrum of the signal as the main target and the ideal ratio mask (IRM) as the auxiliary target in a multi-target learning framework to achieve their complementary advantages. Firstly, a feature extraction module is introduced to achieve the fusion of local and long-term features. Two different targets are learned separately, but share the common feature extraction module, which is helpful to extract more general and suitable features. During the joint learning, the intermediate estimation of the IRM target in the auxiliary path, contributing as the attention gating factors, helps to distinguish the speech or non-speech components of the complex-valued signals in the main path. To leverage more fine-grained long-term contextual information, we introduce a multi-scale dilated convolution approach for feature encoding. Moreover, the proposed model is a causal system, which can fully meet the low latency requirements of real-time speech products. Experimental results show that, compared with other advanced systems, the proposed model not only has better speech denoising performance and phase estimation accuracy, but also generalizes better in the speaker, noise, and channel mismatch cases.

Dual-Path Attention Compensation U-Net for Stroke Lesion Segmentation.

For the segmentation task of stroke lesions, using the attention U-Net model based on the self-attention mechanism can suppress irrelevant regions in an input image while highlighting salient features useful for specific tasks. However, when the lesion is small and the lesion contour is blurred, attention U-Net may generate wrong attention coefficient maps, leading to incorrect segmentation results. To cope with this issue, we propose a dual-path attention compensation U-Net (DPAC-UNet) network, which consists of a primary network and auxiliary path network. Both networks are attention U-Net models and identical in structure. The primary path network is the core network that performs accurate lesion segmentation and outputting of the final segmentation result. The auxiliary path network generates auxiliary attention compensation coefficients and sends them to the primary path network to compensate for and correct possible attention coefficient errors. To realize the compensation mechanism of DPAC-UNet, we propose a weighted binary cross-entropy Tversky (WBCE-Tversky) loss to train the primary path network to achieve accurate segmentation and propose another compound loss function called tolerance loss to train the auxiliary path network to generate auxiliary compensation attention coefficient maps with expanded coverage area to perform compensate operations. We conducted segmentation experiments using the 239 MRI scans of the anatomical tracings of lesions after stroke (ATLAS) dataset to evaluate the performance and effectiveness of our method. The experimental results show that the DSC score of the proposed DPAC-UNet network is 6% higher than the single-path attention U-Net. It is also higher than the existing segmentation methods of the related literature. Therefore, our method demonstrates powerful abilities in the application of stroke lesion segmentation.

Adaptive leakage signal cancellation algorithm in heterodyne FMCW system

To mitigate the leakage signal that obstructs the target information extraction in miniatured frequency modulated continuous wave (FMCW) radar system, an adaptive leakage signal cancellation algorithm is proposed in this paper. Without any help of the additional auxiliary path, all the processing for the intermediate frequency (IF) signal can be conducted in the digital domain. The basic principle to cancel leakage signal is to produce a cancelling signal, which has the same amplitude and anti-phase with the leakage signal. Differently, in this paper, the input phase parameter of the proposed method can be arbitrary and it can be modified by the corresponding corrected function. Besides, to acquire the phase noise in the leakage signal conveniently when generating cancelling signal, the information geometry theory is applied to transform the complex phase noise model into statistical characteristics calculation of the input signal. The effectiveness of the model and the proposed algorithm is verified by simulated results. Furthermore, a real FMCW system is designed to collect the practice echo signals. The resulting data denotes that the leakage signal in the received signal is greatly suppressed and the leakage signal power drops by −15.92 dB.

ADAPT: An auxiliary storage data path toolkit

The legacy storage data path is largely structured in black-box layers and has four major limitations: (1) functional redundancies across layers, (2) poor cross-layer coordination and data tracking, (3) presupposition of high-latency storage devices, and (4) poor support for new storage data models. While addressing all these limitations is a daunting challenge, we introduce ADAPT, an auxiliary storage data path toolkit that complements the legacy storage data path to help mitigate these limitations. This toolkit enables all storage layers to coordinate and track data using shared data structures constructed through the ADAPT API. Our case studies have shown that we can directly support applications such as a key-value store without going through the file system. We also built an ADAPT-based file system and prioritized caching to demonstrate the usability, extensibility, and robustness of ADAPT. In addition, we built per-file secure deletion via our ADAPT-based file system to demonstrate data-path-wide coordination and data tracking.

Combining target sampling with within field route-optimization to optimise on field yield estimation in viticulture

This paper describes a new approach for yield sampling in viticulture. It combines approaches based on auxiliary information and path optimization to offer more consistent sampling strategies, integrating statistical approaches with computer methods. To achieve this, groups of potential sampling points, comparable according to their auxiliary data values are created. Then, an optimal path is constituted that passes through one point of each group of potential sampling points and minimizes the route distance. This part is performed using constraint programming, a programming paradigm offering tools to deal efficiently with combinatorial problems. The paper presents the formalization of the problem, as well as the tests performed on nine real fields were high resolution NDVI data and medium resolution yield data were available. In addition, tests on simulated data were performed to examine the sensitivity of the approach to field data characteristics such as the correlation between auxiliary data and yield, the spatial auto-correlation of the data among others. The approach does not alter much the results when compared to conventional approaches but greatly reduces sampling time. Results show that, for a given amount of time, combining model sampling and path optimization can give estimation error up to 30% lower for a given amount of time compared to previous methods.

Frequency-range enhanced delay locked loop based on varactor-loaded and current-controlled delay elements

In this paper, some building blocks of the conventional delay-locked-loops are modified to achieve a higher frequency range and smaller jitter on generated phases. A novel sensitive and dead-zone free phase detector is proposed with a reduced number of MOS transistors. A voltage-controlled capacitive load is added to the basic delay elements to expand the lower limit of the locking frequency range from 50 MHz to 10 MHz. Besides, the upper limit of the operating frequency is improved from 1 GHz to 1.5 GHz, by reducing the input capacitance of the delay cells via an auxiliary shortening path. Rigorous theoretical analysis is provided on the capacitance variations and the expanded frequency range. Post-layout simulation results confirm that RMS and peak-to-peak jitter of 0.83 pS and 6.85 pS are achieved at 1 GHz operating frequency when 1.8 V supply is subject to random noise components with peak-to-peak variations of 66 mV. The proposed strategy consumes the maximum power of 6.3 mW at TT conditions, within the frequency range of 10 MHz-to-1.5 GHz, and occupies 0.0036 µm2 active area. Simulation results are presented using the BSim3v3 model of MOS transistors in a 0.18 µm CMOS process.

A 4.5 GΩ-Input Impedance Chopper Amplifier With Embedded DC-Servo and Ripple Reduction Loops for Impedance Boosting to Sub-Hz

Achieving a high input impedance Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> is important for the instrumentation amplifier (IA) performing neural and biopotential signal sensing. Previously, impedance boosting techniques have been used with a positive feedback loop (PFL) driven by the output or auxiliary (AUX) path driven by the input. We propose that the conventional approach to DC-servo loop (DSL), which blocks the electrode offset (EOS), does not fully enable the function of a PFL or AUX path. This results in either limited impedance boosting or reduction of a low-frequency Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> in the sub-Hz band. To solve this problem and achieve Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> boosting down to sub-Hz, we propose a new approach to DSL for a capacitively-coupled chopper instrumentation amplifier (CCIA). The proposed DSL is realized using a 30-nA opamp, and the AUX path is designed using a 450-nA duty-cycled buffer. The CCIA achieves a gain of 40 dB and is implemented using a 0.18 μm CMOS process with an area of 0.19 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured results show that Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> is increased by 184 times up to 4.6 GQ at 0.01 Hz. Compared to the CCIA using conventional DSL, Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> is improved by 7.8 times. An input-referred noise of 2.1 μVrms is achieved at 2.14 μW.

Analysis of load mismatch effect compensation in Doherty power amplifier

AbstractThis paper presents a theoretical and experimental analysis of the capabilities of the dual-input Doherty power amplifier (DPA) architecture to mitigate efficiency and output power degradations when used in a mismatched load environment. Following a simplified linear piecewise approach, an analytical demonstration is proposed to derive optimal radio frequency drives applied to the Auxiliary path of the DPA to restore power performances while avoiding large signal voltage clipping of active cells. The proposed analytical study is corroborated with harmonic balance simulated results of a C-band, 20-W GaN DPA prototype. The fabricated dual-input DPA prototype has been measured under 1.5-VSWR mismatch configurations to validate the proposed analysis.

A 0.2–3.3 GHz 2.4 dB NF 45 dB gain CMOS current-mode receiver front-end

A CMOS fully differential current-mode front-end for SAW-less receivers is proposed. The noise-canceling LNTA has a main path of the common-gate (CG) stage and an auxiliary path of the inverter stage. A current mirror is used to combine the signals from the main and auxiliary paths in current mode. The stacked nMOS/pMOS configurations improve their power efficiency. The traditional stacked tri-state inverter as D-latch replaced by the discrete inverter and transmission gate enables a reduced supply voltage of divider core. LO generator based on the improved divider provides quarter LO signals to drive the proposed LNTA-shared receiver front-end. Simulation results in 180 nm CMOS indicate that the integrated receiver front-end provides an NF of 2.4 dB, and a maximum gain of 45 dB from 0.2 to 3.3 GHz. The in-band (IB) and out-of-band (OB) IIP3 of 2.5 dBm and 4 dBm, are obtained, respectively. With CMOS scaling down continuously, CMOS devices are providing increased transit frequency and reduced intrinsic parasitics which are important for radio frequency (RF) and millimeter-wave applications. As a promising solution, CMOS RF delivers comparable performance to silicon bipolar and GaAs devices but at a much lower cost and higher integration level. Supply voltage reduction with CMOS scaling down also poses a stringent linearity requirement. Avoiding the conventional trade-off between the supply voltage and linearity headroom, the proposed receiver front-end based on the current mode principle is with weak linearity dependency on the supply voltage and provides excellent anti-blocker interference capability.

Motion path planning of soccer training auxiliary robot based on genetic algorithm in fixed-point rotation environment

Soccer training assisted robot system is a combination of robotics and artificial intelligence. Motion path planning is an important part of soccer training assisted robot decision system. Path planning aims to find an optimal path, complete dynamic and static obstacle avoidance, and thus can timely and quickly carry out the path planning of the soccer training assisted robot cooperation strategy. Aiming at the problem of soccer training auxiliary robot motion path planning, this paper proposes a global path planning method based on genetic algorithm, which avoids the problem of unsmooth path and large computation. Under the premise of ensuring the completeness of search, this method transforms the soccer training assisted robot path planning problem into the path search problem of the soccer training assisted robot system center. Under the premise of using the fixed-point rotation method on a large scale, the genetic algorithm is adopted for the case of some special narrow-channel environments, and the action area is determined by simple search. Finally, the planning path of each soccer training-assisted robot in the system is obtained. Finally, the simulation results verify the effectiveness of the algorithm.

An Energy-Efficient Three-Stage Amplifier Achieving a High Unity-Gain Bandwidth for Large Capacitive Loads Without Using a Compensation Zero

This letter presents a high-gain energy-efficient three-stage amplifier, which employs buffering-based pole relocation and dual-path structure. The proposed design does not rely on the introduction of compensation zero and preserves the unity-gain bandwidth (GBW) of the local feedback loop (LFL). Compared to the topologies using active-zero insertion, the 3rd pole is formed with a much smaller capacitance (parasitic capacitance), enabling it to be placed at a significantly higher frequency while consuming lower power. Moreover, the parasitic pole at the main path is bypassed by using an auxiliary path. Thus, the 3rd pole can be pushed to a higher frequency more easily than the topologies using an active zero. As a result, the GBW of the LFL in the proposed work is less limited. The proposed design improves the state-of-the-art FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>L</i></sub> by 36%, LC-FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>S</i></sub> by 26%, and LC-FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>L</i></sub> by 218%, while preserving robustness of the performance.

Design and Development of Unmanned Surface Vehicle for Meteorological Monitoring

In view of the paucity of hydrometeorological data, inefficiency and high cost of manual detection, a design scheme of meteorological monitoring unmanned surface vehicle (USV) based on STM32 MCU (Microcontroller Unit, which is also known as Single Chip Microcomputer) is proposed in this paper. The path planning is designed by combining the image data acquired by camera with improved RRT-path algorithm (rapidly-exploring random tree algorithm based on auxiliary path), and then motors are controlled so as to realize autonomous cruise control of USV using the incremental PID algorithm. In addition, the design can also realize real-time monitoring of meteorological data detected by meteorological sensors on the USV through upper computer. Compared with the traditional scheme, the path planning, autonomous cruise is as well as online monitoring function of the scheme presented below enable USVs have full autonomous capability to realize on-line monitoring of meteorological data.

Highly-linear wide-range voltage-controlled delay element with body bias technique

A highly-linear wide-range voltage-controlled delay element in 55 nm CMOS technology at 1.2 V supply is presented. Unlike traditional voltage-controlled delay unit, the proposed delay unit utilizes two transistors as auxiliary current path and employs body bias technique to widen applicable range of control voltage. At the same time, it guarantees correct output logic voltage and high linearity. Moreover, a simple model is proposed to get a better understanding of circuit characteristics. The unit delay ranges from 110ps to 236 ps. When sweeping control voltage from 0 to 1.2 V at 200 MHz (TT corner 27 °C), calculated gain is 14.2ps/mv and delay quadrature error (DQE) is 6.6%. While operating at 200 MHz, the maximum simulated power consumption is 15.09μW.

Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Amplifier

A wideband hybrid Envelope tracking (ET) modulator utilizing a hysteretic-controlled three-level switching converter (3L-SWC) and a slew-rate enhanced linear amplifier (LA) are presented. In addition to smaller ripple and lower losses of 3L-SWCs, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80 MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage $V_{\mathrm{ CF}}$ and eliminates the conventionally required calibration loop to control it. The hysteretic-controlled 3L-SWC provides a high percentage of power amplifier (PA) supply load current with lower ripple, reducing the LA high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the LA, resulting in slew rate of over 307 V/ $\mu \text{s}$ and bandwidth of over 275 MHz for the LA. The SRE circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of output without modifying the operating point of the remaining LA, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in a 65-nm CMOS process. The measurement results show the tracking of long-term evolution (LTE)-40-MHz envelope with 93% peak efficiency at 1-W output power, while the SRE is disabled. Enabling the SRE, it can track LTE-80-MHz envelope with peak efficiency of 91%.

A 10 Gb/s noise-canceled transimpedance amplifier for optical communication receivers

This study presents a noise-canceled transimpedance amplifier (TIA) for optical receivers. The proposed structure consists of a shunt feedback common source amplifier as an input stage followed by two regulated cascodes (RGC) and finally a differential to the single-ended amplifier at the output stage. By exploiting the noise-canceling technique at the input stage, 31.8% of the total output noise is canceled. In addition, the auxiliary path’s RGC circuit, as it has a low input impedance, is utilized to cancel out the photodiode (PD) large parasitic capacitance at the input stage. The proposed TIA along with post amplifiers, including packaging components, are simulated in TSMC 90 nm RF CMOS technology at the post-layout level. The TIA average input-referred current noise is equal to $$9.5\;{\text{pA}}/\sqrt {\text{Hz}}$$. The PD capacitance is considered as 325 fF for all simulations. The transimpedance gain is equal to 60 dBΩ and the 3-dB bandwidth is equal to 7 GHz. The power consumption of the proposed TIA is 3.6 mW from a 1.2 V supply voltage. The TIA occupies a chip area of 0.036 mm2.

Dual-Resolution Dual-Path Convolutional Neural Networks for Fast Object Detection.

Downsampling input images is a simple trick to speed up visual object-detection algorithms, especially on robotic vision and applied mobile vision systems. However, this trick comes with a significant decline in accuracy. In this paper, dual-resolution dual-path Convolutional Neural Networks (CNNs), named DualNets, are proposed to bump up the accuracy of those detection applications. In contrast to previous methods that simply downsample the input images, DualNets explicitly take dual inputs in different resolutions and extract complementary visual features from these using dual CNN paths. The two paths in a DualNet are a backbone path and an auxiliary path that accepts larger inputs and then rapidly downsamples them to relatively small feature maps. With the help of the carefully designed auxiliary CNN paths in DualNets, auxiliary features are extracted from the larger input with controllable computation. Auxiliary features are then fused with the backbone features using a proposed progressive residual fusion strategy to enrich feature representation.This architecture, as the feature extractor, is further integrated with the Single Shot Detector (SSD) to accomplish latency-sensitive visual object-detection tasks. We evaluate the resulting detection pipeline on Pascal VOC and MS COCO benchmarks. Results show that the proposed DualNets can raise the accuracy of those CNN detection applications that are sensitive to computation payloads.

A Wideband Blocker-Tolerant Receiver With Frequency-Translational Resistive Feedback

This paper presents a wideband frequency-translational resistive-feedback receiver (RX), operational from 0.1 to 2.2 GHz. Different blocker suppression techniques are proposed to improve both out-of-band (OOB) compression and weakly nonlinear distortion of the RX. The blockers are first rejected at the RX input using an $N$ -path filter. Then, a blocker current cancellation (BCC) technique is used to mitigate the effect of nonlinearity in the transimpedance amplifier. By introducing an auxiliary path in the RX, the OOB linearity of the RX is further improved by means of frequency-translational noise cancellation (FTNC) and split-BCC. The RX prototype fabricated in a 130-nm CMOS process achieves 2.6–3.2-dB noise figure (NF) and tolerates a 0-dBm blocker at a 50-MHz offset with an NF of 4.9 dB. At 40-MHz offset from the local oscillator (LO), the RX exhibits higher +23-dBm out-of-band input-referred inter modulation product of order 3 (OB-IIP3) without FTNC and higher +26 dBm OB-IIP3 with FTNC.

A Comparative Study of 8-Phase Feedforward-Coupling Ring VCOs

This brief studies comparatively the different 8-phase feedforward-coupling (FC) ring voltage-controlled oscillators in terms of their oscillation modes, oscillation frequency, and phase noise. Among the 3 feasible topologies, the one with sub-feedback loops containing 2 direct-path inverters + 1 feedforward-path inverter (i.e., 2D + 1F) can achieve a better phase noise than the common 4D + 1F topology at the same frequency and power budget. It is also shown that the bimodal oscillation problem of the 2D + 1F topology can be eliminated by inserting an auxiliary FC path. Prototyped in 65-nm CMOS, the proposed 2D + 1F topology at 3.1 GHz shows a phase noise of −95.1 dBc/Hz at a 1-MHz offset, corresponding to a 159.9-dBc/Hz figure-of-merit that is 4.2 dB higher than the common 4D + 1F topology.

Design and simulation of bi-directional DC-DC converter with dual switch forward snubber

A novel isolated bi-directional buck-boost converter is presented for energy storage application. Isolated boost bi-directional DC-DC converters are required to meet the wide voltage variation demand. The conventional isolated boost converters have some auxiliary circuits to provide an auxiliary path for mismatch current between source inductance and leakage inductance of the transformer. The dual switch forward snubber circuit is adopted as auxiliary circuits along with dual active bridge (DAB) converter in the proposed converter. The proposed converter has distinct advantages like zero voltage switching starting (ZVS), no voltage stress on main switches, no additional conduction losses and improved efficiency as compared to RCD snubber-based converter system. The wide voltage variation in output side for 45V to 320V bi-directional DC-DC converter has been simulated with PSIM. The charging mode and discharging mode with energy storing mode has been explained in detail. The simulation results show the effective performance of proposed converter system. The loss comparison has been shown between RCD snubberbased converter and dual switch forward snubber which proves that dual switch forward snubber has high efficiency compared to RCD snubber circuit.

Design and simulation of bi-directional DC-DC converter with dual switch forward snubber

A novel isolated bi-directional buck-boost converter is presented for energy storage application. Isolated boost bi-directional DC-DC converters are required to meet the wide voltage variation demand. The conventional isolated boost converters have some auxiliary circuits to provide an auxiliary path for mismatch current between source inductance and leakage inductance of the transformer. The dual switch forward snubber circuit is adopted as auxiliary circuits along with dual active bridge (DAB) converter in the proposed converter. The proposed converter has distinct advantages like zero voltage switching starting (ZVS), no voltage stress on main switches, no additional conduction losses and improved efficiency as compared to RCD snubber-based converter system. The wide voltage variation in output side for 45V to 320V bi-directional DC-DC converter has been simulated with PSIM. The charging mode and discharging mode with energy storing mode has been explained in detail. The simulation results show the effective performance of proposed converter system. The loss comparison has been shown between RCD snubberbased converter and dual switch forward snubber which proves that dual switch forward snubber has high efficiency compared to RCD snubber circuit.