Automatic Gain Control Scheme Research Articles

An Ultralow Leakage Synaptic Scaling Homeostatic Plasticity Circuit With Configurable Time Scales up to 100 ks.

Homeostatic plasticity is a stabilizing mechanism commonly observed in real neural systems that allows neurons to maintain their activity around a functional operating point. This phenomenon can be used in neuromorphic systems to compensate for slowly changing conditions or chronic shifts in the system configuration. However, to avoid interference with other adaptation or learning processes active in the neuromorphic system, it is important that the homeostatic plasticity mechanism operates on time scales that are much longer than conventional synaptic plasticity ones. In this paper we present an ultralow leakage circuit, integrated into an automatic gain control scheme, that can implement the synaptic scaling homeostatic process over extremely long time scales. Synaptic scaling consists in globally scaling the synaptic weights of all synapses impinging onto a neuron maintaining their relative differences, to preserve the effects of learning. The scheme we propose controls the global gain of analog log-domain synapse circuits to keep the neuron's average firing rate constant around a set operating point, over extremely long time scales. To validate the proposed scheme, we implemented the ultralow leakage synaptic scaling homeostatic plasticity circuit in a standard 0.18m complementary metal-oxide-semiconductor process, and integrated it in an array of dynamic synapses connected to an adaptive integrate and fire neuron. The circuit occupies a silicon area of 84 m 22m and consumes approximately 10.8nW with a 1.8V supply voltage. We present experimental results from the homeostatic circuit and demonstrate how it can be configured to exhibit time scales of up to 100 ks, thanks to a controllable leakage current that can be scaled down to 0.45aA (2.8 electrons per second).

A DC-to-12.5 Gb/s 9.76 mW/Gb/s All-Rate CDR With a Single <italic>LC</italic> VCO in 90 nm CMOS

A dual-lane DC-to-12.5 Gb/s all-rate clock and data recovery (CDR) IC with a single LC voltage-controlled oscillator is fabricated in a 90 nm CMOS. An all-rate clock divider with an asynchronous phase calibration scheme is employed to generate all-rate clock signals without a phase mismatch or duty cycle distortion. The IC features an automatic loop gain control scheme that adjusts the bandwidth of a CDR in the background for optimal bit error rate (BER) performance by monitoring the phase difference between the incoming data and the recovered clock signal. The proposed CDR consumes 244 mW at 12.5 Gb/s under dual-lane operation with an input sensitivity of 12 mVpp,diff. The CDR supports referenceless allrate operation with a BER <; 10 -12 on PRBS31 and compensates for 20 dB of channel loss using a continuous-time linear equalizer (CTLE), a one-tap decision feedback equalizer (DFE), and a three-tap pre-emphasis filter. The power efficiency of the test chip is 9.76 mW/Gb/s.

Channel Estimation and IQ Imbalance Compensation for Uplink Massive MIMO Systems With Low-Resolution ADCs

In this paper, two techniques to compensate inphase/quadrature-phase imbalance (IQI) are investigated in the uplink-quantized massive multiple-input and multiple-output (MIMO) systems for different models of randomized IQI parameters. One is referred to as combined-signal-based channel estimation and compensation (CCEC) and the other is denoted by effective channel estimation and compensation (ECEC). First, an independent automatic gain control (AGC) scheme is proposed to calibrate the dynamic range of both the I branch and the Q branch. By doing that, different quantization steps are used for analog-to-digital converters following the AGCs in these two branches at each receive antenna. Second, considering the impacts of both quantization and IQI, we give the details of channel estimation and IQI compensation for both the CCEC and the ECEC using bilinear generalized approximate message passing (Bi-GAMP). Moreover, to exploit the Bi-GAMP for ECEC reasonably, we theoretically derive the probability density function PDF of the elements in the effective channel for the case where only RX IQI is considered. Furthermore, we extend the ECEC to the case where both RX IQI and TX IQI are incorporated into the systems and derive the similar pdf as well. Finally, we use the numerical results to testify the validity of our theoretical analysis and the fact that the analytic PDF can be approximated by a Gaussian distribution when the IQI parameters are relatively small. Compared with other classical methods, the proposed methods can obtain better performance based on the Monte Carlo simulation results.

Design of RF AGC scheme for improving dynamic range of multichannel heterodyne ECE radiometer in SST-1 Tokamak

This paper describes the design of Automatic gain control (AGC) circuit in RF receiver of a Radiometry system used for Electron Cyclotron Emission (ECE) measurements to determine plasma electron temperature. Based on a feed forward AGC model, the designed RF AGC circuit will enhance the dynamic range of RF receiver up to 50dB. The configured AGC circuit is an integral element of the receiver systems that provides a stable output when the input power is beyond the threshold.

All-optical feedforward automatic gain control scheme for pump power shared erbium-doped fiber amplifiers

All-optical feedforward automatic gain control scheme for pump power shared erbium-doped fiber amplifiers

Psychophysical Evaluation of An Ultra-Low Power, Analog Biomimetic Cochlear Implant Processor Filterbank Architecture With Across Channels AGC

This paper evaluated psychophysically an ultra-low-power, analog biomimetic cochlear-implant (CI) processor filterbank architecture, which was recently proposed and demonstrated in hardware. The architecture/strategy emulates the lateral inhibition (LI) mechanism by employing an automatic gain control (AGC) scheme that is coupled across One-Zero-Gammatone-Filter (OZGF) channels. The OZGF filtering and the coupled channel AGC were tested respectively in two experiments, where normal-hearing listeners were required to listen to sentences and recognise key words therein. The sentences were mixed with a steady background noise at signal-to-noise ratios (SNRs) of $-$ 6, $-$ 3 and 0 dB, and processed through a noise-excited envelope vocoder serving as the acoustic simulator of cochlear implants. In the first experiment, the OZGF filtering was compared with cascaded bandpass biquad filtering employed in recent attempts towards fully-implantable CI processing, in terms of the resulting intelligibility. The results showed that the sharply tuned OZGF response did not degrade intelligibility despite the very limited number (16) of channels used. In the second experiment, the sentences were processed in two multi-channel compression systems, one with the channel AGC coupled, whilst another uncoupled. The results showed that the AGC-coupled system was significantly advantageous, and the improvement averaged across the SNRs is 31 percentage points. Furthermore, this compressive system results in no significant decrease in intelligibility when compared to the linear filtering systems investigated in the first experiment. Thus, the coupled channel AGC may be considered as a potential solution to the limited spectral contrast of current CI systems, which may partially account for their noise-susceptibility.

A Shadowing-aware Automatic Gain Control Scheme for OFDM Wireless Communication System

A Shadowing-aware Automatic Gain Control Scheme for OFDM Wireless Communication System

A 6 μW per channel analog biomimetic cochlear implant processor filterbank architecture with across channels AGC.

A new analog cochlear implant processor filterbank architecture of increased biofidelity, enhanced across-channel contrast and very low power consumption has been designed and prototyped. Each channel implements a biomimetic, asymmetric bandpass-like One-Zero-Gammatone-Filter (OZGF) transfer function, using class-AB log-domain techniques. Each channel's quality factor and suppression are controlled by means of a new low power Automatic Gain Control (AGC) scheme which is coupled across the neighboring channels and emulates lateral inhibition (LI) phenomena in the auditory system. Detailed measurements from a five-channel silicon IC prototype fabricated in a 0.35 μm AMS technology confirm the operation of the coupled AGC scheme and its ability to enhance contrast among channel outputs. The prototype is characterized by an input dynamic range of 92 dB while consuming only 28 μW of power in total ( ∼ 6 μW per channel) under a 1.8 V power supply. The architecture is well-suited for fully-implantable cochlear implants.

Automatic Gain Control of EDFAs Using DSP

The recent development in automatic gain control (AGC) of Er-doped fiber amplifier (EDFA) based on the electrical feedback is reviewed briefly. We introduce a AGC method which uses the adaptive PID arithmetic with feedforward to realize gain clamping by automatically optimizing. The experimental results show that the AGC scheme based on DSP has the advantages of relatively low cost ,high reliability and good flexibility due to the potential of using different arithmetic.

A Multiband Mobile Analog TV Tuner SoC With 78-dB Harmonic Rejection and GSM Blocker Detection in 65-nm CMOS

A 48–885–MHz ultralow-cost high-performance mobile analog TV (MATV) tuner with an improved harmonic rejection design algorithm achieves 5.5 dB/4.5 dB noise figure at VHF and UHF bands, respectively, and adjacent channel interference (ACI) <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N}+1/{\rm N}+2$</tex></formula> performance of 24/29 dB. A harmonic rejection mixer (HRM) with a tracking filter (TF) scheme employing three external inductors, one for each TV band, achieves better than 78/83-dB harmonic-rejection for the VHFI/VHFIII bands. A single LC-tank VCO with a programmable divider that has a 50% duty cycle correction scheme covers the entire TV band with accurate LO phases. A digital automatic gain control (AGC) scheme detects the presence of ACI and/or GSM burst-mode blockers through an RF wideband peak detector (WBPD) and adjusts the receiver gain for optimum dynamic range. The RF tuner is fabricated in 65-nm CMOS technology with silicon area of only 1.25 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{mm}^{2}$</tex> </formula> and draws 37/19 mA for analog TV and FM radio receiver modes, respectively.

An RF front-end with an automatic gain control technique for a U/V band CMMB receiver

This paper presents a fully integrated RF front-end with an automatic gain control (AGC) scheme and a digitally controlled radio frequency varied gain amplifier (RFVGA) for a U/V band China Mobile Multimedia Broadcasting (CMMB) direct conversion receiver. The RFVGA provides a gain range of 50 dB with a 1.6 dB step. The adopted AGC strategy could improve immunity to adjacent channel signal, which is of importance for CMMB application. The front-end, composed of a low noise amplifier (LNA), an RFVGA, a mixer and AGC, achieves an input referred 3rd order intercept point (IIP3) of 4.9 dBm with the LNA in low gain mode and the RFVGA in medium gain mode, and a less than 4 dB double side band noise figure with both the LNA and the RFVGA in high gain mode. The proposed RF front-end is fabricated in a 0.35 μm SiGe BiCMOS technology and consumes 25.6 mA from a 3.0 V power supply.

An Enhanced Automatic Gain Control Algorithm for Initial Cell Search in 3GPP LTE TDD System

In this paper, we propose an AGC (Automatic Gain Control) algorithm for initial cell search in 3GPP (3rd Generation Partnership Project) LTE (Long Term Evolution) TDD (Time Division Duplex) system. Since the received signal has a large signal power difference between uplink and downlink subframe in wireless communication systems using a TDD scheme, conventional AGC scheme cannot sufficiently adjust the AGC gain because the AGC gain cannot converge fast enough to properly respond. Therefore, conventional AGC scheme leads to increased AGC gain variation, and the received signal will be attenuated by large AGC gain variation. To overcome this limitation, we propose an AGC scheme based on the average amplitude ratio calculation which can not only effectively increase convergence speed of the AGC gain but also maintain the stability of AGC operation in LTE TDD system. Also, it is important for AGC to converge efficiently for the accurate radio frame timing detection during the subsequent initial cell search procedure. Therefore, we also consider the proposed AGC scheme in combination with PSS (Primary Synchronization Signal) detection interface for the first step of initial cell search process in LTE TDD system to obtain both a stable AGC operation and accurate PSS detection performance. By extensive computer simulation in the presence of frequency offset and various channel environments, we verified that the proposed method can obtain a good behavior in terms of demodulation and PSS detection performance in LTE TDD system.

A novel control loop design and its application to the force balance of vibratory rate sensor

This paper investigates a new loop design approach of force balance control for the vibratory rate sensor application. The proposed force balance control design takes advantages of the modified automatic gain control configuration in controlling the system’s oscillating dynamics at the sense mode. The adapted automatic gain control scheme and force balance strategy, which maintains a constant oscillation magnitude in the sense mode, have several advantages. First it is possible to analyze a complicated nonlinear feedback system using a linear control theory, which resulted in straightforward prediction of closed loop performance. Moreover the control system to achieve the design goals can be implemented using a relatively simple feedback configuration. An application to the vibratory rate sensor using the proposed automatic gain control configuration witnessed that the force balance control can be validated in a practical design process. Experiments using an actual micromachined rate sensor verified the feasibility of the proposed control scheme with demonstration of enhanced performance.

Multiplexed Four-Channel Rectilinear Ion Trap Mass Spectrometer

A four-channel multiplexed mass spectrometer with rectilinear ion trap (RIT) mass analyzers was designed, constructed, and characterized. The system consists of four parallel atmospheric pressure ion (API) sources, four RIT mass analyzers, four sets of ion optical elements, and four conversion dynode detectors. The complete instrument is housed in a single vacuum manifold with a common vacuum system. It has a relatively small footprint, and costs and complexity were minimized and controls simplified by sharing the electronics and control modules among different channels. Each channel of the instrument can be operated in either positive or negative ion mode with a choice of ionization methods to improve the information content from an experiment. Also, the instrument is equipped with simultaneous data acquisition capabilities from all four channels, but the use of a common RF electronics system limits the degree to which the analyzer channels can be scanned independently. The instrument was characterized over the mass/charge range of 150 to 1300 Th. Mass misassignments in different ion traps because of machining and assembly tolerances were avoided by the application of supplementary direct current signals to each mass analyzer to correct mass offsets. A multiplexed automatic gain control (AGC) scheme was developed to control the ion population in each of the traps independently. These two features allow tandem mass spectrometry to be performed with an isolation window of 1 Th so trapping identical ions in all four channels. There are two principal modes of operation. In one, the same sample is analyzed in all four channels using different ionization methods to increase the information content of the analysis. In the other mode of operation, different samples are analyzed in all four channels with the same ionization method, so providing higher throughput. These capabilities were demonstrated by examining lipids produced by Escherichia coli and complex mixtures containing drugs of abuse.

AUTOMATIC GAIN CONTROL FOR UNITY FEEDBACK CONTROL SYSTEMS

In this paper, an automatic gain control scheme is proposed for analyses and designs of unity feedback control systems. It is consisted of a fast command tracking loop and a slow gain adaptive loop. The overall system is equivalent to a conventional automatic gain control loop with command tracking error input. It gives good command tracking behaviour while keeping robust characteristic of the original automatic gain control loop. It gives good robustness for coping with fast large parameter and load disturbance variations also. The stability of the controlled systems and effective of the proposed method are verified by root-loci, time responses, frequency responses, large parameter variations and fast large load disturbances testing with two numerical examples.

Joint Gain and Timing Recovery With Applications to Magnetic Tape Storage

We discuss a joint gain and timing recovery scheme that provides performance advantages in tape recording environments plagued by deep amplitude fades and timing error fluctuations. The idea is to find a particular combination of the gain and phase errors that best matches with a window of playback samples and use the resulting estimates to drive the automatic gain control (AGC) loop and the timing recovery loop. The gain and phase estimate pair is obtained and maintained separately for each survivor path in the Viterbi processor, and is used to compensate for the corresponding distortions in the Viterbi branch metric computation. The gain and phase error estimates are then taken out of the best survivor path possibly with some delay and are used to drive the respective loops. The BER performance and cycle slip probabilities are compared with those of a conventional AGC and timing recovery scheme

Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs

Traditional approaches of automatic gain control (AGC) involve estimating the average power or the peak amplitude over an extended time period, which results in high hardware complexity and a long processing time. Moreover, the accuracy of traditional approaches is seriously degraded by noise and intersymbol interference. In this paper, we propose a joint AGC and equalization (Joint AGC-EQ) scheme, in which the AGC circuitry comprises only one-tenth of the area of a traditional AGC. In addition, the total convergence time of the proposed Joint AGC-EQ is only half that of traditional blind equalization. The scheme is already silicon proven for the application of a Fast Ethernet transceiver using Faraday/UMC 0.18-mum cell libraries

Analog AGC Circuitry for a CMOS WLAN Receiver

The IEEE 802.11a standard uses orthogonal frequency division multiplexing (OFDM) to allow high data rates in multipath WLAN environments. The high peak-to-average power ratio (PAPR) of OFDM signals, along with stringent settling-time constraints, make conventional closed-loop automatic gain control (AGC) schemes impractical for WLAN receivers. In a direct conversion receiver, AGC and channel-select filtering are performed by analog baseband circuitry. A baseband signal processor using a new open-loop analog gain-control algorithm for OFDM is described. The new AGC algorithm uses switched coarse gain-setting steps followed by an analog open-loop fine gain-setting step to set the final gain of variable gain amplifiers (VGAs). The AGC was implemented in a 0.18-mum CMOS process using newly designed circuits including linear VGAs, RMS detectors, and current-mode computation circuitry. Simulation and measurement results verify that the new AGC circuit converges with gain error less than 1dB to the desired level within 5.6 mus

The New Design of AGC Circuit for the Sinusoidal Oscillator With Wide Oscillation Frequency Range

The typical automatic gain control (AGC) schemes are not suitable for the sinusoidal oscillator with wide oscillation frequency range. To solve this problem, the up-down counter, multiplying digital-to-analog converter, and high-speed comparators are employed to achieve the proposed AGC circuit, which corrects the complex roots of the overall system automatically to the imaginary axis of the complex frequency plane. The negative feedback technique with digital hardware is applied on the loop gain control. No low-pass filter is needed to detect the oscillation amplitude. Thus, this technique is suitable for the sinusoidal oscillator with wide oscillation frequency range. The oscillation frequencies ranging from 7 Hz to 1 MHz are tested with the proposed AGC circuit. The experimental results demonstrate the static characteristics and dynamic responses of the overall system.

Lossless dispersion compensating fibre module for wavelength-management networks

A lossless dispersion compensating fibre module employing a high-speed automatic gain control scheme is demonstrated. The gain is controlled by monitoring total input and output signal powers and only adjusting pump power at the shortest wavelength. The static and dynamic gain excursion is suppressed effectively.