Audio ADC Research Articles

A VCO-ADC Linearized by a Capacitive Frequency-to-Current Converter

In this brief we propose a technique to compensate the distortion of an open-loop VCO-based ADC. The VCO is linearized by placing an analog feedback loop based on a frequency-to-current converter which uses an asynchronous switched capacitor circuit. The feedback loop relies on the VCO gain to linearize the ADC without requiring additional amplifiers. This permits the use of a ring oscillator with small input range to efficiently encode a large signal. The proposed technique has been experimentally demonstrated in an audio ADC. The proof-of-concept chip was fabricated in 130nm CMOS and achieves 76.64 dBA of peak SNDR with a Dynamic Range of 90dB and a power consumption of 482μW in 20kHz.

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation.

Testing high resolution ΣΔ ADC's by using the quantizer input as test access

A new solution to improve the testability of high resolution ΣΔ Analogue to Digital Converters (ΣΔ ADC's) using the quantizer input as test node is described. The theoretical basis for the technique is discussed and results from high level simulations for a 16 bit, fourth order, audio ADC are presented. The analysis demonstrates the potential to reduce the computational effort associated with test response analysis versus conventional techniques. If only SNR, THD and gain of the ΣΔ ADC are evaluated with the new proposed method the test time is already reduced by 20%.

A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR

This paper presents a second-order /spl Delta//spl Sigma/ modulator for audio-band analog-to-digital conversion implemented in a 3.3-V, 0.5-/spl mu/m, single-poly CMOS process using metal-metal capacitors that achieves 98-dB peak signal-to-noise-and-distortion ratio and 105-dB peak spurious-free dynamic range. The design uses a low-complexity, first-order mismatch shaping 33-level digital-to-analog converter and a 33-level flash analog-to-digital converter with digital common-mode rejection and dynamic element matching of comparator offsets. These signal-processing innovations, combined with established circuit techniques, enable state-of-the art performance in CMOS technology optimized for digital circuits.