Au Stud Bumps Research Articles

A novel insight into Au-Au thermosonic flip chip joint under extreme thermal cycles: Defect characterization and failure analysis

Au-Au thermosonic flip chip joints are regarded as a promising chip-substrate interconnect structures and their reliability has been a concern. Compressing the top of Au stud bumps during the coining process would result in plastic deformation of Au; During the bonding process, plastic deformation took place at the interface of Au stud bump and substrate under the impact of ultrasonic vibration, elevated temperature, and bonding pressure; additionally, due to different Coefficient of Thermal Expansion (CTE) between various components of the joint, the mismatch of CTE caused by the thermal cycling process would also result in plastic deformation. For Au element with extraordinary ductility, plastic deformation would inevitably lead to various material defects. This research first performed thermal cycling tests on Au-Au thermosonic flip chip joints, and found that a crack developed after 500 cycles and it propagated along the interface to the entire width of the joint, which seriously injured the joint. Here, for the first time, this research characterized all types of material defects (dislocations, stacking fault, twin, and amorphization) at the bonding interface of the Au-Au flip chip joint which underwent 500 thermal cycles. Their causes and effects on cracking were investigated individually, finally a novel failure mechanism was proposed from the perspective of material defects and a technique to prevent cracking was proposed. This research is anticipated to provide an in-depth study of the microstructure at the bonding interface of Au-Au flip chip joints and the impact of various defects on their reliability.

Experimental study on the fracture behavior variation of the Au stud bump bonding with different high temperature storage times

PurposeAu stud bump bonding technology is an effective means to realize heterogeneous integration of commercial chips in the 2.5D electronic packaging. The purpose of this paper is to study the long-term reliability of the Au stud bump treated by four different high temperature storage times (200°C for 0, 100, 200 and 300 h).Design/methodology/approachThe bonding strength and the fracture behavior are investigated by chip shear test. The experiment is further studied by microstructural characterization approaches such as scanning electron microscope, energy dispersive spectrometer and so on.FindingsIt is recognized that there were mainly three typical fracture models during the chip shear test among all the Au stud bump samples treated by high temperature storage. For solder bump before aging, the fracture occurred at the interface between the Cu pad and the Au stud bump. As the aging time increased, the fracture mainly occurred inside the Au stud bump at 200°C for 100 and 200 h. When aging time increased to 300 h, it is found that the fracture transferred to the interface between the Au stud bump and the Al Pad.Originality/valueIn addition, the bonding strength also changed with the high temperature storage time increasing. The bonding strength does not change linearly with the high temperature storage time increasing but decreases first and then increases. The investigation shows that the formation of the intermetallic compounds because of the reaction between the Au and Al atoms plays a key role on the bonding strength and fracture behavior variation.

Die-Level Thinning for Flip-Chip Integration on Flexible Substrates

Die-level thinning, handling, and integration of singulated dies from multi-project wafers (MPW) are often used in research, early-stage development, and prototyping of flexible devices. There is a high demand for thin silicon devices for several applications, such as flexible electronics. To address this demand, we study a novel post-processing method on two silicon devices, an electrochemical impedance sensor, and Complementary Metal Oxide Semiconductor (CMOS) die. Both are drawn from an MPW batch, thinned at die-level after dicing and singulation down to 60 µm. The thinned dies were flip-chip bonded to flexible substrates and hermetically sealed by two techniques: thermosonic bonding of Au stud bumps and anisotropic conductive paste (ACP) bonding. The performance of the thinned dies was assessed via functional tests and compared to the original dies. Furthermore, the long-term reliability of the flip-chip bonded thinned sensors was demonstrated to be higher than the conventional wire-bonded sensors.

Intermetallic Compounds at the Interfaces of Ag–Pd Alloy Stud Bumps With Al Pads

Stud bumping using a traditional wire bonding process followed by the severing of the wire material from the ball bond has been widely applied in flip chip packages. Traditionally, Au stud bumps were employed because of the physical properties of gold, but the mediocre reliability of Au with Al pads and the cost of gold make this material unfavorable for industrial needs. Copper stud bumps were also considered, but the intrinsic features of Cu, such as its high hardness and ease of oxidation, present no advantages over gold stud bumps. However, Ag-alloy stud bumps exhibit satisfactory bondability and have been proposed as the optimal substitute for Au stud bumps to ensure better reliability in soldering and better intermetallic growth kinetics with Al bond pads. In this article, the intermetallic growth of Ag stud bumps alloyed with 2%, 10%, and 12% Pd after high-temperature storage tests (HTSTs) is investigated. The results indicated that the Pd atoms remained immobile in the bump-side matrix without diffusing into the aluminum pad side. Alloying with higher Pd content enhanced the formation of the favorable Ag <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Al intermetallic compound (IMC), whereas lower Pd content resulted in severe cracking due to the formation of Ag <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Al IMC. Compositional analysis showed that continuous layers of Ag-Al IMCs doped with large amounts of Pd formed at the interfaces close to the Ag stud bumps, but no Pd was detected on the Al pad side. The bonding strength increased after aging at 150 °C and 200 °C for 200 h, but it decayed drastically after aging at 250 °C for 200 h. The relationship between intermetallic growth and failure mode was established.

A 2.5-D Integrated Data Logger for Measuring Extreme Accelerations

A very compact and rugged 2.5-D integrated data logger has been built and tested. The data logger is capable of measuring accelerations exceeding 70 000 g. Microcontroller and flash memory as bare dies have been mounted onto a silicon interposer with through silicon vias using anisotropic conductive film and Au stud bump bonding. A microelectromechanical system accelerometer is mounted onto the interposer, using a robust customized flip-chip mounting approach. The interposer is mounted into a 16-pin leadless chip carrier package using isotropic conductive adhesive, where the conductive part is made of metallized polymer spheres. The ceramic package was mounted onto an application printed circuit board (PCB) with filters, power management, and an interface contact, using soldered plastic core solder balls (PCSBs). The diameter of the data logger is less than 9 mm, and the height is approximately 5 mm. The data logger fits within 12.7-mm (0.50 cal.) projectile, and acceleration measurements have been performed during firing, flight, and recovery. The measured accelerations have been verified by comparing the calculated projectile muzzle velocities with Doppler radar measurements.

Packaging and Demonstration of Optical-Fiber-Coupled Photodiode Array for Operation at 4 K

An optoelectronic module for operation at 4 K is developed, intended for use in pulse-driven Josephson arbitrary waveform synthesizer. Multiple InP/InGaAs photodiodes with customized optical fiber assembly were assembled on a single silicon carrier. Photodiodes were flip-chip bonded on the carrier using Au stud bumps, and laser-cut silicon fixtures were aligned and adhesively bonded to the carrier in order to attach pigtailed borosilicate ferrules. Optical simulations were performed to estimate the tolerance for fiber-chip misalignment. The photodiodes were bonded with an average misalignment of $8~\mu \text{m}$ , while the misalignment between the silicon fixture and the photodiodes after bonding was $13~\mu \text{m}$ . The electrical response to continuous-wave laser inputs was measured at room temperature and at 4 K by direct immersion in liquid helium. The results show that the assembly technique could facilitate a stable and efficient optical coupling. The individual photodiodes were able to deliver currents up to 12 mA at room temperature and 7 mA at 4 K.

Microstructure and reliability of hybrid interconnects by Au stud bump with Sn-0.7Cu solder for flip chip power device packaging

With miniaturization of the interconnect solder bumps, high current density causes serious reliability issues (stress, electromigration etc.) in electronic packages. Through Au stud bumping on the chips and following reflow of solder to produce hybrid interconnects, the eletromigration resistance may be improved by the intermetallics formed inside them due to their barrier effects on the atoms migration. Here, microstructures and reliabilities of Au stud with serial amounts of Sn-0.7Cu solder paste were studied through controlling size of stencil printing aperture. After reflow, AuSn, AuSn2 and AuSn4 formed from the surface of Au stud bump to the solder. A layer of (Cu,Au)6Sn5 with thickness of 3μm existed at the interface near the Cu substrate with a scallop shape similar to Cu6Sn5. The fraction of intermetallics to the mixed joints varied with the solder amount. Shear strength decreased slightly when comparing with the sole solder joint due to large amounts of brittle intermetallics. Thermal aging resulted in many Kirkendall voids generated at the interfaces of Au stud and the solder, which further decreased the shear strength. The effect of solder amount on microstructural evolution and fracture modes was discussed. The hybrid interconnects showed a good electromigration resistance.

Room-Temperature Gold-Gold Bonding Method Based on Argon and Hydrogen Gas Mixture Atmospheric-Pressure Plasma Treatment for Optoelectronic Device Integration

SUMMARY Low-temperature bonding methods of optoelectronic chips, such as laser diodes (LD) and photodiode (PD) chips, have been the focus of much interest to develop highly functional and compact optoelectronic devices, such as microsensors and communication modules. In this paper, room-temperature bonding of the optoelectronic chips with Au thin film to coined Au stud bumps with smooth surfaces (Ra: 1.3nm) using argon and hydrogen gas mixture atmospheric-pressure plasma was demonstrated in ambient air. The die-shear strength was high enough to exceed the strength requirement of MIL-STD-883F, method 2019 (×2). The measured results of the light-current-voltage characteristics of the LD chips and the dark current-voltage characteristics of the PD chips indicated no degra

A 60-GHz-band 2 x 4 planar dipole array antenna module fabricated by 3-D SiP technology

A 2 × 4 phased array antenna module has been developed for 60-GHz-band short- range high-speed wireless communication terminals. To realize the required vertical distance between the antenna elements, the module is made of five sheets of multi-layered organic substrates vertically stacked with Cu balls, and the 1 x 4 dipole array antenna is placed on both the top and bottom organic substrates. To reduce the mutual coupling between the element antennas, a monolithic microwave integrated circuit (MMIC) is flip-chip mounted on the feed line of each element antenna. The Au-stud bump flip-chip mounting technique helps achieve a lower return loss in the transition section at the MMIC than the Au-wire bonded. The placement accuracy of each antenna element in the vertical direction, 60-GHz signal vertical interconnection between the substrates with Cu balls, and flip-chip mounting of the MMIC are confirmed by 3-D computed tomography (CT) scans.

(Invited) Flipchip with Au Die Bumps Interconnected to Au Plated Substrate Used for Mobile Processors

Recently, TCNCP (Thermal Compression with Non-Conductive Paste) flipchip technology has received much attention because of the demands of flipchip with high bump density for mobile devices and 2.5D/3D applications. TCNCP technology is a relatively new technology that is applied for flipchip with very fine bump pitch. One of the advantages of TCNCP process is that it could ensure IC flatness during local reflow process as IC is under pressure during TCNCP process. Here TCNCP technology is used with Au stud bump for mobile processor. Au stud bumping process is done with sawn IC with standard wire bonder. The Au stud bumps are usually connected to trace on the substrate (Bump on Trace) as there is no space for bump landing pads. Pressure and heat are applied simutaneoursly during thermal compression bonding (TCB) process at temperature of less than 230︒C. The formed Au to Au joint is mechanical contact without interrmetallic formation. Reliability results show that although without intermetallics, the package structure can pass TCT 1000 cycles, HTS 1000 hours and uHAST 192hrs without failures.

Soldering of non-wettable Al electrode using Au-based solder

In manufacturing three-dimensional SiC power modules, the Al electrode of SiC power devices should be soldered to the substrate. However, the Al electrode is difficult to be bonded by a solder due to the naturally formed aluminum oxide on it. In this paper, we describe an effective approach for soldering the non-wettable Al electrode by fabricating a Au-stud bump in the Al electrode together with a Au-20 wt% Sn or Au-12 wt% Ge solder. The soldering initiated at the Au bump and spreaded on the Al electrode. The soldering featured as reactive wetting, realized by the reaction of liquid Au in the Au-base solder and the Al electrode. The activation energy of the Au-20 wt% Sn soldering the Al electrode was Q = 159 kJ/mol. A continuous Au4Al layer formed at the Au-20 wt% Sn bond interface. The shear strength exceeded 60 MPa, ∼1 order magnitude higher than the required shear strength. For the bond with Au-12 wt% Ge solder on the Al electrode with a Au bump, the liquid Au-12 wt% Ge solder reacted with the solid Al electrode and formed a Au-Ge-Al solid solution after solidification. The shear strength of the Au-12 wt% Ge solder on the Al electrode with a Au bump was beyond 50 MPa. Little electrical characteristics of the SiC-SBD changed after the Al electrode was bonded to a circuit substrate using this technology.

Optimization of the Au Stud Bump Number for the Flip-Chip Packaged InGaN LEDs

Au stud bump can provide a good heat spreading path for the flip-chip LED due to its high thermal conductivity (300 W/mK) . In this paper, we compared four flip-chip LED devices with four different numbers of Au stud bumps. The thermal imaging analysis indicates that the heat dissipation is proportional to the number of Au stud bump. However, when the number of Au stud bumps was larger than 24, the heat dissipation performance will become deteriorated due to the poor bonding between grain and substrate. Therefore, the number of Au stud bumps was optimized to be 20 to 24, which can be employed to develop flip-chip LEDs with optimum electrical and optical performance.

The effect of intermetallic compound evolution on the fracture behavior of Au stud bumps joined with Sn-3.5Ag solder

The microstructure and joint properties of Au stud bumps joined with Sn-3.5Ag solder were investigated as functions of flip chip bonding temperature and aging time. Au stud bumps were bonded on solder-onpad (SOP) at bonding temperature of 260°C and 300°C for 10 s, respectively. Aging treatment was carried out at 150°C for 100 h, 300 h, and 500 h, respectively. After flip chip bonding, intermetallic compounds (IMCs) of AuSn, AuSn2, and AuSn4 were formed at the interface between the Au stud bump and Sn-3.5Ag solder. At a bonding temperature of 300°C, AuSn2 IMC clusters, which were surrounded by AuSn4 IMCs, were observed in the Sn-3.5Ag solder bump. After flip chip bonding, bonding strength was approximately 220.5mN/bump. As aging time increased, the bonding strength decreased. After 100 h of aging treatment, the bonding strength of the joint bonded at 300°C was lower than that bonded at 260°C due to the fast growth rate of the AuSn2 IMCs. The main failure modes were interface fractures between the AuSn2 IMCs and AuSn4 IMCs, fractures through the AuSn2 IMCs and pad lift. Initial joint microstructures after flip chip bonding strongly affected the bonding strengths of aged samples.

Thermal and Mechanical Properties of Flip Chip Package with Au Stud Bump

Thermal and Mechanical Properties of Flip Chip Package with Au Stud Bump

Recent Progress in Thin Film Multichip Packaging for High Temperature Digital Electronics

A thin film material and process technology is being developed and evaluated for high temperature (300°C) digital multichip modules for use in geothermal well instrumentation. The substrate technology selected is AlN to minimize the difference in the coefficient of thermal expansion between the substrate and the SiC digital die. A thin film/plated Ti/Ti:W/Au metallization is used with a plasma enhanced chemical vapor deposited Si3N4 to create multilayer interconnections. Active components are assembled to the interconnect substrate using Au stud bump thermocompression bonding. The Au stud bump maintains a monometallic interface between the substrate Au pad surface and the Au pads on the SiC die. A digital circuit has been built and successfully tested as an initial demonstration.

Investigation of Photo-Imageable Thick Film Metallization on Low Temperature Cofired Ceramics (LTCC) for Improved Packaging Density

With the increasing electronics demand on complexity and functionality, low temperature cofired ceramic (LTCC) shows its advantages for cost efficiency under high volume, multilayer high packaging density, and compatibility of passive components integration. However, compared with thin film technology, the minimum thick film line width and spacing on LTCC is 4mil, which limits the packaging of fine pitch devices. In this study, one of DuPont™ photoimageable thick film gold (Au) conductors has been selected to fabricate on DuPont 951PX substrate, with the patterns as small as 1mil. Surface insulation resistance (SIR) and serpentine resistance patterns with a series of line width and spacing was printed and post fired on LTCC to investigate the capabilities and limits of the feature size. Feature dimensions were measured to compare with the design value. Metal adhesion and stud bump patterns are also included in the test substrate. After initial testing, the substrates are undergoing 300°C aging. Post aging resistance measurement, metallization adhesion pull test and Au stud bump shear test are carried out to evaluate its high temperature behaviors.

Au 스터드 범프와 Sn-3.5Ag 솔더범프로 플립칩 본딩된 접합부의 미세조직 및 기계적 특성

The effect of flip chip bonding parameters on formation of intermetallic compounds (IMCs) between Au stud bumps and Sn-3.5Ag solder was investigated. In this study, flip chip bonding temperature was performed at <TEX>$260^{\circ}C$</TEX> and <TEX>$300^{\circ}C$</TEX> with various bonding times of 5, 10, and 20 sec. AuSn, <TEX>$AuSn_2$</TEX> and <TEX>$AuSn_4$</TEX> IMCs were formed at the interface of joints and (Au, Cu)<TEX>$_6Sn_5$</TEX> IMC was observed near Cu pad side in the joint. At bonding temperature of <TEX>$260^{\circ}C$</TEX>, <TEX>$AuSn_4$</TEX> IMC was dominant in the joint compared to other Au-Sn IMCs as bonding time increased. At bonding temperature of <TEX>$300^{\circ}C$</TEX>, <TEX>$AuSn_2$</TEX> IMC clusters, which were surrounded by <TEX>$AuSn_4$</TEX> IMC, were observed in the solder joint due to fast diffusivity of Au to molten solder with increased bonding temperature. Bond strength of Au stud bump joined with Sn-3.5Ag solder was about 23 gf/bump and fracture mode of the joint was intergranular fracture between <TEX>$AuSn_2$</TEX> and <TEX>$AuSn_4$</TEX> IMCs regardless bonding conditions.

Surface activated bonding of copper through silicon vias and gold stud bumps at room temperature

A comprehensive investigation of the surfaces of copper through silicon vias (Cu-TSVs) and gold stud bumps is presented. These vias and stud bumps were bonded at room temperature using a nanobonding and interconnection equipment. The influence of heating on the bonded interface was also studied. In order to achieve an intimate contact between the Au-stud bumps and Cu-TSVs, the stud bumps were flattened under an external force of 20 N before bonding. The surface roughness of the flattened area was improved due to deformation of the bumps. Specimens with high deformation provided better alignment accuracy than those with low deformation. The Cu-TSV surface showed inhomogeneous behavior due to the influence of electroplating and chemical mechanical polishing. Tensile pulling test of the bonded interfaces showed three fractures modes in the bulk of the Au bump and the Au pad. The electrical resistance of the bonded interface was dependent on the surface morphology of the bumps and TSVs, the distance between the bumps and TSVs, the locations of the bumps and TSV with respect to the argon fast atom beams, and the distribution of external force during bonding. Heating at 200 °C for 60 h in air increased the electrical resistance of the bonded interface. This investigation shows that the vertical integration of Au/Cu at room temperature and low bonding force can be applied to three-dimensional interconnections for low cost miniaturized systems.

A Novel Three-Dimensional Packaging Method for Al-Metalized SiC Power Devices

A novel three-dimensional packaging method for Al-metalized SiC power devices has been developed by means of Au stud bumping technology and a subsequent vacuum reflow soldering process with Au-20Sn solder paste. Al-metalized electrodes of a SiC power chip can be robustly assembled to a direct bonded copper (DBC) substrate with this method. The bump shear strength of a Au stud bump on an Al electrode of a SiC chip increased with bonding temperature. The die shear strength of a SiC chip on the DBC substrate increased with the number of Au stud bumps which were preformed on the Al electrode. The bonded SiC-SBD chips on a DBC substrate were aged at 250degC in a vacuum furnace and the morphologies, die shear strength and electrical properties were investigated after a certain aging time. After 1000 h aging at 250degC, the electrical resistance of the bonded SiC-SBD chips only increased about 0.4%, the residual die shear strength was much higher than that of the IEC749 (or JEITA) standard value, and little morphological change was observed by a micro-focus X-ray TV system. Very little diffusion between Au stud bumps and Au-20Sn solder was observed by scanning electron microscope (SEM) equipped with an energy dispersed X-ray analyzer (EDX). Intermetallic compounds (IMC) evolved at the interface of chip/solder and chip/Au stud bumps after 1000 h aging at 250degC. With this method, power devices with Al bond pads can be three-dimensionally packaged.

Effect of isothermal aging on intermetallic compounds and Kirkendall void growth kinetics of Au stud bumps

Intermetallic compounds (IMCs) and Kirkendall void growth kinetics at various interfaces in Au stud bumps were studied in terms of isothermal aging at 120 °C, 150 °C, and 180 °C for 300 h. Phases of AuSn, AuSn2, and AuSn4 form at the interface of Au studs and Sn after a reflow. The thickness of an Au-Sn IMC was quantified with an image analyzer as a function of aging temperature and time. The growth of the Au-Sn IMC increases linearly with the square root of the aging time at 120 °C, 150 °C, and 180 °C. The growth of the Au-Sn IMC at 180 °C differs from the growth of the Au-Sn IMC at 120 °C and 150 °C because of excessive Au consumption by the Au studs. Kirkendall voids form at the interface of the Au stud and the Au-Sn IMC and increase linearly with the square root of the aging time. The apparent activation energies for the growth of the Au-Sn IMC and the Kirkendall voids were determined to be 0.57 eV and 0.2 eV, respectively, from measurement of the thickness of the Au-Sn IMCs and the width of the Kirkendall voids in relation to the aging temperature and time.