Au-free Contacts Research Articles

Ta/Al/CuW low temperature ohmic contacts for GaN-on-Si HEMT

We proposed a low temperature Au-free ohmic contacts of GaN-on-Si HEMT with the Ta/Al/CuW metal stack. The CuW was deposited by using the dual-target magnetron sputter deposition method. The annealing conditions and recess depth of ohmic area were systematically investigated. By utilizing the Ta/Al/CuW structure, an improved contact characteristic (0.49 Ω·mm) is obtained following annealing at 550 °C for 10 min in vacuum, with the recess depth of 30 nm(±2 nm). This performance surpasses that of Ta/Al/W Au-free contacts (1.07 Ω·mm). Furthermore, both the Ta/Al/CuW ohmic contacts (RMS = 6.3 nm) and the Ta/Al/W ohmic contacts (RMS = 6.0 nm) exhibit smooth surface morphology. Compared to Ti contact layer, Ta demonstrates superior performance in low temperature contact and breakdown test. Amorphous Ta layer can effectively suppress Cu diffusion. The GaN-on-Si HEMT was also fabricated based on Ta/Al/CuW Au-free ohmic contacts, exhibiting excellent DC characteristics.

Recent Progress in Source/Drain Ohmic Contact with β-Ga2O3

β-Ga2O3, with excellent bandgap, breakdown field, and thermal stability properties, is considered to be one of the most promising candidates for power devices including field-effect transistors (FETs) and for other applications such as Schottky barrier diodes (SBDs) and solar-blind ultraviolet photodetectors. Ohmic contact is one of the key steps in the β-Ga2O3 device fabrication process for power applications. Ohmic contact techniques have been developed in recent years, and they are summarized in this review. First, the basic theory of metal–semiconductor contact is introduced. After that, the representative literature related to Ohmic contact with β-Ga2O3 is summarized and analyzed, including the electrical properties, interface microstructure, Ohmic contact formation mechanism, and contact reliability. In addition, the promising alternative schemes, including novel annealing techniques and Au-free contact materials, which are compatible with the CMOS process, are discussed. This review will help our theoretical understanding of Ohmic contact in β-Ga2O3 devices as well as the development trends of Ohmic contact schemes.

(Invited, Digital Presentation) High-κ Gate Oxide Integration and Ohmic Contact Development for AlGaN/GaN MISHEMTs

In this work we review our latest results concerning the integration of different high-κ dielectrics e.g. Al2O3, GdScO3 and TiO2 for gate passivation and the related development of ohmic contacts in metal insulator semiconductor high electron mobility transistor. Depending on deposition and crystallization temperature of the dielectric, a high-κ first and high-κ last process was used. For both concepts, the development of suitable ohmic contacts with low formation temperature were carried out. Vanadium based contacts for high-κ first and Au-free contacts for the high-κ last approach was shown. The influence of the ohmic contact formation temperature on the performance of the MISHEMT devices were studied for all high-κ gate passivation layer.

Mask registration and lithography platform portability for nitride fin-based field effect transistors prototyping

The authors report on the integration of a hybrid lithography process for AlGaN/GaN high-electron-mobility nanoscaled, fin-based field effect transistors with an Au-free contact. The integration consists of electron beam lithography (EBL) and optical photolithography to minimize prototyping cost and time while maximizing resolution and device array density. I-line direct photolithography is performed using standard photoresist, while EBL is accomplished using 2% polymethyl methacrylate for high resolution of fin structure patterning. Au-free contact is characterized using linear transmission line method (TLM) and is deposited along with registration marks via electron beam evaporation. The registration marks and TLM structures are used for alignment in the EBL process. Details of the device fabrication process and electrical results are discussed and show possible parallel processing of GaN and Si devices.

(Invited) Technology Options to Reduce Contact Resistance in Nanoscale III-V MOSFETs

III-V semiconductors have emerged as a leading candidate to replace Si as channel material in future low power logic applications. To realize the full performance benefits of III-V channels, it is crucial that external parasitic resistance (REXT) be minimized. Among the different components of REXT, contact resistance (RC) between metal and source/drain (S/D) junctions has become a critical area of focus to lower REXT. Historically, multi-layered Au-based metal contacts (e.g. Au/Ge/III-V) were used in III-V processing. However, the renewed interest in III-V semiconductors for CMOS has attracted an increasing interest by many to develop Au-free contacts to III-V with low RC. In addition, a “silicide-like” metal contact process for III-V was recently developed by reacting Ni with InGaAs to form Ni-InGaAs. This is significant as it is a self-aligned process and it offers the option of using a common S/D contact metal in a hetero-integrated device flow (e.g. Si/Ge/III-V). In this paper, we will review these technology options for RC reduction and present some of our recent results on contact/junction engineering to lower RC in III-V transistors.

(Invited) Technology Options to Reduce Contact Resistance in Nanoscale III-V MOSFETs

III-V semiconductors have emerged as the leading candidate to replace Si as the n-FET channel material for future low power logic applications. However, to realize the full performance benefits of III-V channels, it is crucial that external parasitic resistance (Rext) be minimized. Among the different components of Rext, contact resistance (RC ), between metal and source/drain (S/D) junctions, has become the critical focus. Historically, multi-layered Au-based contacts (e.g. Au/Ge/III-V) are used in III-V processing to lower RC . However, the renewed interest in III-V semiconductors has attracted an increasing interest in developing Au-free contacts to III-V with low RC . In addition, a “silicide-like” metal contact process for III-V was recently developed by reacting Ni with InGaAs to form Ni-InGaAs. This is significant as it enables self-alignment and offers the option of using a common S/D contact metal in a hetero-integrated device flow (e.g. Ge/III-V). In this paper, we will review these RC reduction options and present some of our recent results on contact/junction engineering to lower RC in III-V MOSFETs.

Challenges of contact module integration for GaN-based devices in a Si-CMOS environment

The authors report on the integration of an Au-free contact module intended for AlGaN/GaN high-electron-mobility transistors fabricated in a 200 mm Si complementary metal–oxide–semiconductor facility. Contacts are characterized via transfer line method structures, tunneling electron microscopy, and energy-dispersive x-ray spectroscopy. Factors leading to incorrect extraction of contact resistance are discussed. The authors find that reoptimization of chemical vapor deposited silicon nitride on AlGaN/GaN substrates is required to ensure reliable determination of contact resistance, gate-to-source spacing, and gate-to-drain spacing. Additional process development is required to enable parallel processing of Si and GaN devices.

InxAl1-xN/AlN/GaN High Electron Mobility Transistor Structures on 200 mm Diameter Si(111) Substrates with Au-Free Device Processing

InxAl1-xN/AlN/GaN-based high electron mobility transistor (HEMT) structures are epitaxially grown on 200 mm diameter Si(111) substrates by a metal organic chemical vapor deposition technique. The structural and electrical properties of the nitride layers are addressed by high-resolution X-ray diffraction and Hall effect measurements. The fabricated HEMTs with Au-free contact metallization schemes have resulted in an ON-OFF current ratio ∼105. Ti/Al/Ni/W-based Ohmic source/drain contacts, with 1.5 μm RuOx Schottky gate on In0.15Al0.85N/AlN/GaN HEMTs at VDS = 10 V, show a maximum transconductance (gm) and saturation drain current (IDSAT) of 0.19 ± 0.01 S/mm and 0.82 ± 0.02 A/mm, respectively, with a reasonable uniformity from the center to edge of a 200 mm diameter epiwafer.

Transparent Ohmic contacts of oxidized Ru and Ir on p-type GaN

Low-resistance, high-transparency, and thermally stable Ohmic contacts on p-type GaN were achieved using Ru and Ir. Oxidation annealing under O2 atmosphere led to the reduction of contact resistivity by greater than one order of magnitude, compared to annealing under N2. The bilayer contacts of Ru (50 Å)/Ni (50 Å) and Ir (50 Å)/Ni (50 Å) exhibited a low contact resistivity of ∼4×10−5 Ω cm2 and high light transmittance of ∼85% after annealing at 500 °C for 1 min under O2. The barrier height for hole injection could decrease via contact formation of RuO2 (or IrO2) on p-type GaN. The Au-free contact structure of NiO/RuO2 (IrO2)/GaN led to high light transmittance and good thermal stability.