ASIC Wafer Research Articles

(Invited) Wafer-Bonding for MEMS – Status and Trends

The current sensor portfolio at Bosch is covering a large variety of different MEMS-based sensor products for automotive and consumer applications. Most of them use wafer-bonding as capping-technology on wafer-level. The basic features that wafer bonding technologies for MEMS must fulfil for a successful wafer-level packaging process are hermeticity, high bond strength and high temperature stability. Glass-frit and anodic bonding are well and long-term established standard technologies used for hermetic packaging of MEMS on wafer-level. But both technologies require comparatively large chip sizes that are not compatible with the requirements for miniaturization and cost reduction of new consumer sensors. Therefore metallic bonding processes like eutectic bonding with aluminium-germanium were used for current sensor generations. One step further is the realization of hermetic encapsulation and electrical interconnection, if an ASIC wafer serves as a functionalized cap. Cu-Cu thermo-compression and Cu/Sn SLID bonding are promising techniques that are of high interest for MEMS products of the future.

Invited: Wafer-Bonding for MEMS – Status and Trends

The current sensor portfolio at Bosch is covering a large variety of different MEMS-based sensor products for automotive and consumer applications. Examples for automotive applications are pressure sensors for engine control, side impact detection and inertial sensors for airbag systems, navigation and vehicle-dynamics control (ESP). Examples for consumer applications are inertial sensors for gaming, freefall detection in laptops, switching in mobile-phones and pressure sensors used as altimeter, barometer and indoor navigation. Among the different wafer bonding techniques for wafer-level packaging that are shown in figure 1, anodic bonding, glass-frit and eutectic bonding are state-of the-art for MEMS sensors and the metallic bonding processes thermo-compression and solid-liquid interdiffusion (SLID) bonding have a high potential for future applications.The basic features that wafer bonding technologies for MEMS must fulfil for a successful wafer-level packaging process are hermeticity, high bond strength and high temperature stability. Glass-frit and anodic bonding are well and long-term established standard technologies used for hermetic packaging of MEMS on wafer-level. But both technologies require comparatively large chip sizes that are not compatible with the requirements for miniaturization and cost reduction of new consumer sensors. Therefore metallic bonding processes like eutectic bonding with aluminium-germanium were used for new consumer sensors. Typically, the bond frame size with the eutectic bond can be reduced by a factor of 2 in combination with a frame that stops the liquid eutectic material in lateral extent. With eutectic bonding very small chip sizes are possible resulting in shrinking the size of Bosch accelerometers as shown in figure 2. One step further is the realization of hermetic encapsulation and electrical interconnection, if an ASIC wafer serves as a functionalized cap. Cu-Cu thermo-compression and Cu / Sn SLID bonding are promising techniques that are of high interest for MEMS products of the future.The wafer bonding processes used and under development at Bosch, examples, advantages, disadvantages and challenges will be described.Figure 1: Overview of waferbonding technologies.Figure 2: Shrinking the chip-size for smaller accelerometers was promoted by the change from glass-frit to eutectic wafer bonding.

Design and Process of 3D MEMS System-in-Package (SiP)

The design and assembly process of 10 different 3D MEMS packages will be presented and discussed in this study. These 3D MEMS packages integrate the MEMS devices from the MEMS wafer (with either wirebonding pads, or solder-bumped TSV, through silicon via, substrate, or solder-bumped flip chip without TSV), the ASIC chips from the ASIC wafer (either with or without TSV), and the cavity package cap from the cap wafer (either with or without TSV). The assembly process consists of release (etching), singulation, wire bonding, flip chip, TSV, cavity etching, chip-to-wafer (C2W) bonding, and wafer-to-wafer (W2W) bonding. It can be shown that these packages lead to a small packaging footprint, high electrical performance, and potentially low cost.