As-deposited Devices Research Articles

Engineering of forming-free resistive switching characteristics in ZrO2 films

The variation of forming-free resistive switching (RS) characteristics modulated by thermal annealing was investigated in ZrO2 films fabricated by electron beam evaporation. A typical forming-free behavior with pristine resistance comparable to that of the high resistance state (HRS) was observed in the as-deposited devices. Whereas, the resistance was further reduced to a state with initial resistance even lower than the low resistance state (LRS) after annealing in N2 ambient and a larger resistance ratio was verified in the annealed devices. Both devices exhibited stable bipolar RS without any forming step, which has great potential for memory applications. A possible RS mechanism associated with adjusting of oxygen vacancy formation and migration was proposed to explain these distinct forming-free behaviors. It is expected that controllable forming-free characteristics and improved device performance may be obtained by further optimizing the distribution and density of oxygen vacancies via post-annealing.

Temperature-dependent current–voltage measurements of Au/C9H7N/p-Si: Characterization of a metal–organic-semiconductor device

The attachment of organic molecules onto the silicon surfaces is of crucial interest for the development of nanoscale organic–inorganic hybrid materials. In this study, the electrografting of diazonium salts has been used for covalent attachment of the molecules to H-passivated silicon (100) surface. The modification of silicon electrodes with quinoline molecules was carried out through electrochemical reduction of in situ generated diazonium salts from 6-aminoquinoline, and thus an Au/quinoline/p-Si device was fabricated. The results measured from the as-deposited device displayed a higher barrier height at room temperature due to the formation of an interfacial dipole at a metal/organic interface during electrochemical deposition. It has been shown that the barrier height value was increased with the increasing temperature. In addition, there were seen two different behaviours of the temperature-dependent ideality factor and this was attributed to the response of quinoline to temperature below and above 160K such it is likely to take place phase change at the interface. Such a temperature dependence of the barrier height was explained by the Gaussian distribution of the barrier heights due to the barrier height inhomogeneities at the quinoline film/p-type silicon interface. The mean barrier height and the standard deviation σ values were determined as 0.87eV and 0.0989V, respectively. Furthermore, the Norde model was also used for determining the temperature-dependent of barrier height and it was seen that there was a good agreement between that of the common ln(I)–V and Norde model.

Electrical and Optical Characterization of R.F.-Sputtered CdTe Thin Films

Four sets of R.F.-sputtered CdS/CdTe thin-film solar cells are activated through comparable treatment procedures. Two samples were rinsed into deionized water for an hour before $\hbox{CdCl}_{2}$ treatment and then activated in Ar or air ambient. The two others are normally treated and activated in Ar and air, respectively. The influence of water rinsing and annealing ambient on the electrical and optical properties of the films is investigated by current–voltage, field-emission scanning electron microscope, X-ray diffraction, and optical transmission spectroscopy. We examined water rinsing as a cheap and simple pretreatment step to modify the semiconductor surface and to obtain quality device. In this way, the fill factor of the cells that were rinsed into water before $\hbox{CdCl}_{2}$ activation was comparable with the one prepared without rinsing. There is a challenge between the effect of water and Ar on the electrical parameters of the cells. Water-rinsed cells annealed in Ar showed better properties than those that received no water rinsing. It seems that water reduces the negative effect of Ar annealing or parasitic diffusion of Cu into the semiconductor. The higher shunt resistance of the rinsed samples represents that water rinsing could passivate the surface defects and pinholes. The grain size, phase, and band gap of the thin films are extracted, analyzed, and compared with the as-deposited devices.

Effect of Rapid Thermal Annealing on Resistive Switching Uniformity of HfAlO<sub>x</sub> Based RRAM Devices

HfAlOx based RRAM devices were fabricated using atomic layer deposition by modulating deposition cycles for HfO2 and Al2O3. The effect of rapid thermal annealing (RTA) on the resistive switching uniformity of HfAlOx based RRAM devices was investigated. Compared to the as-deposited devices, the resistive switching uniformity of HfAlOx based RRAM devices after RTA treatment are remarkably improved. The uniformity improvement of HfAlOx based RRAM after RTA treatment is related to microstructure change in the resistive switching film.

Resistive switching memory characteristics of Ge/GeO x nanowires and evidence of oxygen ion migration

The resistive switching memory of Ge nanowires (NWs) in an IrOx/Al2O3/Ge NWs/SiO2/p-Si structure is investigated. Ge NWs with an average diameter of approximately 100 nm are grown by the vapor–liquid-solid technique. The core-shell structure of the Ge/GeOx NWs is confirmed by both scanning electron microscopy and high-resolution transmission electron microscopy. Defects in the Ge/GeOx NWs are observed by X-ray photoelectron spectroscopy. Broad photoluminescence spectra from 10 to 300 K are observed because of defects in the Ge/GeOx NWs, which are also useful for nanoscale resistive switching memory. The resistive switching mechanism in an IrOx/GeOx/W structure involves migration of oxygen ions under external bias, which is also confirmed by real-time observation of the surface of the device. The porous IrOx top electrode readily allows the evolved O2 gas to escape from the device. The annealed device has a low operating voltage (<4 V), low RESET current (approximately 22 μA), large resistance ratio (>103), long pulse read endurance of >105 cycles, and good data retention of >104 s. Its performance is better than that of the as-deposited device because the GeOx film in the annealed device contains more oxygen vacancies. Under SET operation, Ge/GeOx nanofilaments (or NWs) form in the GeOx film. The diameter of the conducting nanofilament is approximately 40 nm, which is calculated using a new method.

Influence of post-deposition heat treatment on electrical transport properties of In2S3-buffered Cu(In,Ga)Se2 cells

The electrical characteristics of Cu(In,Ga)Se2-based solar cells with In2S3 buffer were investigated. The effects of post-deposition annealing in helium or in air on current–voltage characteristics, net acceptor density profiles and admittance spectra were studied. Analysis of the current–voltage characteristics showed that interface recombination dominated transport in the as-deposited devices was reduced after annealing and partially replaced by bulk recombination. This was accompanied by a decrease in the saturation current and diode ideality factor. The influence of the heat treatment on the buffer/hetero-interface region as determined by capacitance measurements was minor. We conclude that a reduction in the interface states density and in the p+ layer doping caused by the chemical modification of the hetero-interface region is the major source of the improvement.

Investigation of temperature dependent threshold voltage variation of Gd2O3/AlGaN/GaN metal-oxide-semiconductor heterostructure

Temperature dependent threshold voltage (Vth) variation of GaN/AlGaN/Gd2O3/Ni-Au structure is investigated by capacitance-voltage measurement with temperature varying from 25°C to 150°C. The Vth of the Schottky device without oxide layer is slightly changed with respect to temperature. However, variation of Vth is observed for both as-deposited and annealed device owing to electron capture by the interface traps or bulk traps. The Vth shifts of 0.4V and 3.2V are obtained for as-deposited and annealed device respectively. For annealed device, electron capture process is not only restricted in the interface region but also extended into the crystalline Gd2O3 layer through Frenkel-Poole emission and hooping conduction, resulting in a larger Vth shift. The calculated trap density for as-deposited and annealed device is 3.28×1011∼1.12×1011 eV−1cm−2 and 1.74×1012∼7.33×1011 eV−1cm−2 respectively in measured temperature range. These results indicate that elevated temperature measurement is necessary to characterize GaN/AlGaN heterostructure based devices with oxide as gate dielectric.

Enhancement of photovoltaic characteristics of nanocrystalline 2,3-naphthalocyanine thin film-based organic devices

In this work, nanocrystalline thin films of 2,3-naphthalocyanine (NPC) were successfully deposited by a thermal evaporation technique at room temperature under high vacuum (∼10−4Pa). The crystal structure and surface morphology were measured using X-ray diffraction (XRD) and scanning electron microscopy (SEM), respectively. A preferred orientation along the (001) direction was observed in all the studied films and the average crystallite size was calculated. Scanning electron miscroscopy (SEM) images of NPC films at different thermal treatment indicated significant changes on surface level patterns and gave clear evidence of agglomeration of nanocrystalline structures. The molecular structural properties of the thin films were characterized using Fourier transform infrared spectroscopy (FTIR), which revealed the stability of the chemical bonds of the compound under thermal treatment. The dark electrical conductivity of the films at various heat treatment stages showed that NPC films have a better conductivity than that of its earlier reported naphthalocyanine films and the activation energy was found to decrease with annealing temperature. The absorption edge shifted to the lower energy as a consequence of the thermal annealing of the film and the fundamental absorption edges correspond to a direct energy gap. The temperature coefficient of the onset and optical band gaps for the film was calculated to be −4.4×10−4 and −1.76×10−3eV/K, respectively. The effect of thermal annealing on the photovoltaic properties of Al/NPC/ITO devices was also considered. The as-deposited device showed maximum power conversion efficiency about 0.70% under illumination of 100mW/cm2, whereas 2.65% power conversion efficiency was achieved after annealing the samples at 500K for 1h.

Performance and stability of amorphous InGaZnO thin film transistors with a designed device structure

We propose a specifically designed structure to fabricate thin-film transistors using amorphous indium-gallium-zinc-oxide (a-IGZO) films as the active channel layers. The I-shaped gate electrode is employed to define the channel width, reducing overlaps between the gate and source/drain electrodes. The devices with such a structure exhibit acceptable electrical performance and stability after annealing treatment. The XPS data show that the as-deposited a-IGZO film has not a very dense structure that may induce shallow traps. A shallow trap model is proposed to explain the large threshold voltage shifts of the as-deposited device. Annealing treatment can eliminate these shallow traps and improve the device stability.

Heteromorphic chloroindium phthalocyanine films for improved photovoltaic performance

A new structure incorporating multiple phases of chloroindium phthalocyanine (ClInPc) is fabricated and tested in photovoltaic devices. This so-called heteromorphic structure includes as-deposited and THF vapor treated ClInPc films to improve absorption and photovoltaic (PV) performance in devices. Absorption of the polymorphic phases of ClInPc are complementary and lead to improved current generation. Short circuit current is improved by over 70% using the heteromorphic structure, while power conversion efficiency (PCE) improves by more than 40% versus solely as-deposited devices. Advantages of the heteromorphic structure include broader spectral response, improved interfacial contact area and an intermediary open circuit voltage ( V oc).

Investigation of the metastability behavior of CIGS based solar cells with ZnMgO–Zn(S,O,OH) window-buffer layers

In this paper, different electrical characterization techniques are used to investigate the metastability behavior of the ZnO:Al/ZnMgO/Zn(S,O,OH)/Cu(In,Ga)Se2 solar cell. Whereas this device presents a poor conversion efficiency and metastable behavior just after the deposition stage, Thermal Annealing and Light Soaking considerably improved its conversion efficiency. In order to understand the metastable behavior and Thermal Annealing effect of this device, different electrical and electro-optical characterization measurements were carried out including Sub Gap Modulated Photo-Current Spectroscopy. The application of Sub Gap Modulated Photo-Current Spectroscopy measurements performed on an as-deposited device, revealed two deep defects. These defects became shallower and less efficient for the capture of free carriers after Thermal Annealing. Moreover, the photoluminescence spectra exhibit an increase of the measured signal after Thermal Annealing, which is due to a band-to-band recombination. In addition, capacitance–voltage measurements show a hysteresis behavior that is significantly reduced after Light Soaking or Thermal Annealing. We also performed numerical simulations with SCAPS, a software tool of the University of Gent available to the PV research community, to calculate the current–voltage characteristics under AM1.5G illumination and the capacitance–voltage ones under dark conditions. The evolution of the corresponding experimental characteristics from the as-deposited state to different steps during the Thermal Annealing or Light Soaking posttreatment could be well reproduced by varying a high acceptor-like defect density at the buffer/absorber hetero-interface.

Strong orange/red electroluminescence from hydrogenated polymorphous silicon carbon light-emitting devices

We report on electroluminescent P-I-N diodes containing silicon nanocrystals embedded in an amorphous silicon carbon matrix as emitting material. The as-deposited devices mostly contain amorphous Si nanoparticles and emit weakly in the IR. After a forming process consisting of the application of a high current density to the structure, the intensity of the electroluminescence increases by a factor of 30 and shifts to the red. The forming process is characterized by electroluminescence measurements and the induced crystallization of the nanoparticles is evidenced by Raman scattering spectroscopy measurements. These results are interpreted as a metal induced crystallization.

Al Ga N ∕ Ga N metal-oxide-semiconductor heterostructure field-effect transistors using barium strontium titanate

Use of high-k gate dielectrics in AlGaN∕GaN heterostructure field-effect transistors (HFETs) may reduce gate leakage and improve device reliability without adversely impacting transconductance and pinchoff voltage. To achieve this, AlGaN∕GaN metal-oxide-semiconductor heterostructure field-effect transistors have been formed by incorporating barium strontium titanate (BST) deposited by rf magnetron sputtering as the gate dielectric. The maximum current achieved was slightly lower than realized in standard devices without BST, while the gate leakage of the devices was reduced by ∼5 orders of magnitude compared to a conventional HFET for the as-deposited devices and 4 orders of magnitude for films annealed in N2. The transconductance and pinchoff voltage were found to vary with different dielectric constants of the BST films, being reduced by ∼25% for a 40nm film with a dielectric constant of 20, and by 14% upon annealing in N2 (dielectric constant ∼66) when compared to a baseline device with no oxide. It was found that the BST deposition temperature greatly affected mobility in the AlGaN∕GaN structure, with higher temperatures significantly reducing the HFET mobility.

Low‐frequency noise characterizations on Ni/GaN Schottky diodes deposited on intermediate‐temperature buffer layers

Silicon dioxide passivated back-to-back Schottky diodes were fabricated by depositing Ni on rf plasma-assisted molecular beam epitaxy-grown GaN utilizing a unique double buffer layer structure. In this study, both low-frequency noise and deep-level transient Fourier spectroscopy (DLTFS) measurements were conducted to characterize the effects of intermediate-temperature buffer layers (ITBLs) on the hot-electron hardness of GaN Schottky diodes. Device A was fabricated with a double buffer layer consisting of a thin AlN high-temperature buffer layer (HTBL) and a GaN ITBL. Device B consists of a single AlN HTBL. Low-frequency noise results measured from the as-deposited devices show a significant reduction in the noise level, over an order of magnitude, for device A indicative of the substantial reduction in the trap density in the GaN thin films deposited on ITBLs. Hot-electron hardness of the devices was examined through the application of high voltage stress. The increase in the low-frequency noise for device A after voltage stressing is much smaller and no detectable deep-level is observed by both low-frequency noise and DLTFS techniques. However, both characterization techniques indicate a generation of a deep-level at 780 meV below the conduction band edge for device B. Based on detailed optical and electrical characterizations of the samples, the improved device properties for device A are attributed to the relaxation of residue strain in the epilayer during growth due to the utilization of ITBL [W. K. Fong et al., J. Cryst. Growth 233, 431 (2001)]. (© 2003 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Annealing Effects of Schottky Contacts on the Characteristics of 4H-SiC Schottky Barrier Diodes

ABSTRACTThis paper reports on the relationship between the microstructure and the device performance of Pt/4H-SiC schottky barrier diodes ( SBDs ). The evolution of microstructure in the metal/SiC interfaces annealed at different temperatures was characterized using X-ray scattering techniques. The reverse characteristics of the devices were degraded with annealing temperatures. The maximum breakdown voltages of as-deposited devices and 850 °C annealed devices are 1300 V and 626 V, respectively. However, the forward characteristics of the devices were found out to improve with annealing temperatures. X-ray scattering analysis showed that Pt-silicides were formed by annealing performed at or higher than 650 °C. The formation of silicides was shown to increase the roughness of the Pt/SiC interface. It is believed that the forward characteristics of the SBDs be strongly dependent on the crystallity of silicides formed in the Pt/SiC interface during the annealing process.

Amorphous silicon solar cells

The perfectioning of the deposition techniques of amorphous silicon over large areas, in particular film homogeneity and the reproducibility of the electro-optical characteristics, has allowed a more accurate study of the most intriguing bane of this material: the degradation under sun-light illumination. Optical band-gap and film thickness engineering have enabled device efficiency to stabilize with only a 10–15% loss in the as-deposited device efficiency. More sophisticated computer simulations of the device have also strongly contributed to achieve the highest stable efficiencies in the case of multijunction devices. Novel use of nanocrystalline thin films offers new possibilities of high efficiency and stability. Short term goals of great economical impact can be achieved by the amorphous silicon/crystalline silicon heterojunction. A review is made of the most innovative achievements in amorphous silicon solar cell design and material engineering.

Interface effects on double injection current and photocurrent in a-Si:H n-i-p and p-i-n diodes

I- V curves of n-i-p and p-i-n diodes have been measured under forward bias with and without light-bias. It was found that the photogain, G ph, can be as high as 1000 in an n-i-p structure. However, G ph is below the limitation of our measurements in most p-i-n structures. Both the dark- and the photo-current responses of the devices depend strongly on the deposition sequence (n-layer before or after i-layer) which affects both n-i and p-i interfaces. One explanation of these findings is that the photogain in both n-i-p or p-i-n structures is controlled by the strength of hole trapping near the n-i interface; the current transients are fitted well if we use this hypothesis. This suggests that the n-i interface is degraded by light-soaking, as is the bulk. It was also found that the recombination mechanism near the n-i interface is bimolecular for as-deposited devices, and becomes monomolecular after degradation.

Electrical characterization of low-pressure chemical-vapor-deposited silicon dioxide metal-oxide-silicon structures

The electrical characteristics of as-deposited and oxygen-annealed low-pressure chemical-vapor-deposited (LPCVD) silicon dioxide (SiO2) metal-oxide-silicon (MOS) structures were investigated. As-deposited LPCVD SiO2 MOS structures exhibit a high oxide fixed charge density in the mid-1011 cm−2 and an interface state density in the low-1011 cm−2 eV−1 due to the large number of oxygen and silicon dangling bonds. A low electron barrier height in these structures (1.2 eV) is presumed to be due to lowering of the barrier by excess silicon microclusters. Oxygen-annealed LPCVD SiO2 MOS structures exhibit oxide fixed charge and interface state densities in the mid-1010 cm−2 and mid-1010 cm−2 eV−1, respectively. Both the as-deposited and annealed devices exhibit turnaround in flatband voltage shift with avalanche electron injection. However, the direction of shift is opposite for the two devices with the annealed device being very similar to that of thermally grown SiO2 MOS structures. Apparently, oxygen annealing restructures and oxidizes the partial SiOx in the as-deposited LPCVD oxide into stochiometric SiO2. However, the residual nonstochiometric SiO2 microclusters in the bulk result in an electron barrier height of only 2.3 eV.