Reconfigurable Cell Array Research Articles

Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture

Row Parallel Coarse-Grained Reconfigurable Architecture (RPCGRA) has the advantages of maximum parallelism and programmable flexibility. Designing an efficient algorithm to map the diverse applications onto RPCGRA is difficult due to a number of RPCGRA hardware constraints. To solve this problem, the nodes of the data flow graph must be partitioned and scheduled onto the RPCGRA. In this paper, we present a Depth-First Greedy Mapping (DFGM) algorithm that simultaneously considers the communication costs and the use times of the Reconfigurable Cell Array (RCA). Compared with level breadth mapping, the performance of DFGM is better. The percentage of maximum improvement in the use times of RCA is 33% and the percentage of maximum improvement in non-original input and output times is 64.4% (Given Discrete Cosine Transfor 8 (DCT8), and the area of reconfigurable processing unit is 56). Compared with level-based depth mapping, DFGM also obtains the lowest averages of use times of RCA, non-original input and output times, and the reconfigurable time.

Design and implementation of a data-driven dynamical reconfigurable cell array

The nature of dataflow computation demands the heavy flow of tokens amongst computation nodes. Traditional reduced instruction-set computer (RISC) processors are not suitable for such style computation. Devices that use long wire buses are not suitable for dataflow either. Reconfigurable computing devices (RCDs) consist of data transfer wires and computing resources. With minor modifications, reconfigurable cells can be adopted to perform dataflow computation. A reconfigurable cell array (RCA) is presented in this paper and it is suitable for dataflow computation. This cell array has a dynamic reconfigurable storage model. The distinctive features of the architecture include dataflow reconfigurable cells and reconfigurable storage. Dataflow applications can be mapped easily and effectively onto the cells. Reconfigurable storage is mainly used to manage data access and transmission. Furthermore, computation and data management are separated. Meanwhile, dynamical reconfiguration is accomplished, when some clusters of cells work in configuration mode and other clusters work in computation mode. The dataflow graphs of some algorithms are mapped onto our architecture, and the performance results are compared with those of CPU and GPU.

A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing

This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 ${rm mm}^{2}$ core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 $times$ 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs. (Less)

A dynamically reconfigurable cell array for software-defined radio

The reconfigurable cell array (RCA) architecture and its implementation are presented in this article. A distinctive feature of this architecture is its dual mode of operations. A reconfigurable cell in this array can operate in either blocking mode or non-blocking mode. This makes it suitable for efficient dataflow computation. This architecture is designed for high-throughput applications of software-defined radio (SDR) using fully pipelined and wavefront computation with fast dynamic reconfiguration. The RCA is part of a SDR chip and is responsible for the high-throughput, intermediate-frequency processing such as digital up and down conversion. In addition to the processing cells, the RCA also includes finite-state machine controllers for data stream management and distributed memory elements for stream data storage. The RCA, when combined with the programmable digital signal processor array, forms a powerful system for the SDR.

High-Efficiency Customized Coarse-Grained Dynamically Reconfigurable Architecture for JPEG2000

This brief presents an efficient implementation of JPEG2000 encoding algorithm based on an architecture consisting of a coarse-grained dynamically reconfigurable instruction cell array and an embedded advanced RISC machine core. In this implementation, different tasks within the JPEG2000 encoding algorithm are allocated with proper computational resources to achieve high throughput. The proposed architecture is dynamically reconfigured for different tasks during the encoding process. Simulation results demonstrate that the proposed architecture provides a throughput of up to 52.1 f/s (or 19.18 ms/frame) to encode a 256 × 256 standard Lena test image. Compared with various digital signal processor & very long instruction word-based JPEG2000 solutions, the proposed architecture provides significant advantages in terms of throughput and energy consumption.

Cell array reconfigurable architecture for high-efficiency AES system

This paper present the issue of standard security algorithms with reconfigurable cell array architecture. The reconfigurable Advanced Encryption Standard (AES) architecture is proposed for high performance information security applications. The reconfiguration architecture based on cell array processing elements is connected to each other through the interconnect routing and the switchbox. AES operations are performed on a two-dimensional array using four rows and four columns for the encryption with 128-bit Key length. The Key expansion unit is set the flexible architecture with 128-, 196- and 256-bit cipher Key length. The reconfigurable Key generator further increases the AES hardware flexibility. The operation of SubBytes and XOR is implemented with internal cell of array, but ShiftRow and MixColumns must depend on co-ordination between cells of array. Sixteen free cells of array are connected using the switchbox to operate the encryption of AES algorithm. The on-line fault detection based on parity code is designed to check fault cell. The cell array AES architecture is simulated with Verilog HDL. The prototype system of reconfigurable cell array AES is verified using a field programmable gate array (FPGA). The experiment results show that the proposed method achieves a high-efficiency, low-hardware overhead and high reliability for the information security.

Fast AdaBoost-Based Face Detection System on a Dynamically Coarse Grain Reconfigurable Architecture

An AdaBoost-based face detection system is proposed, on a Coarse Grain Reconfigurable Architecture (CGRA) named “REMUS-II”. Our work is quite distinguished from previous ones in three aspects. First, a new hardware-software partition method is proposed and the whole face detection system is divided into several parallel tasks implemented on two Reconfigurable Processing Units (RPU) and one micro Processors Unit (µPU) according to their relationships. These tasks communicate with each other by a mailbox mechanism. Second, a strong classifier is treated as a smallest phase of the detection system, and every phase needs to be executed by these tasks in order. A phase of Haar classifier is dynamically mapped onto a Reconfigurable Cell Array (RCA) only when needed, and it's quite different from traditional Field Programmable Gate Array (FPGA) methods in which all the classifiers are fabricated statically. Third, optimized data and configuration word pre-fetch mechanisms are employed to improve the whole system performance. Implementation results show that our approach under 200MHz clock rate can process up-to 17 frames per second on VGA size images, and the detection rate is over 95%. Our system consumes 194mW, and the die size of fabricated chip is 23mm2 using TSMC 65nm standard cell based technology. To the best of our knowledge, this work is the first implementation of the cascade Haar classifier algorithm on a dynamically CGRA platform presented in the literature.

Radiation-Hardened Reconfigurable Array With Instruction Roll-Back

This letter presents the design and evaluation of a coarse grained reconfigurable array, hardened against radiation induced transient errors. The architecture consists of an 8 × 8 array of reconfigurable cells, each provided with a built-in soft error detection and instruction roll-back control. We also present the communication management scheme between the processors in the presence of varying degrees of single event upsets. The impact on throughput while evaluating an 8 × 8 discrete wavelet transform (DWT) and 8 × 8 discrete cosine transform (DCT) are also presented.

Reconfigurable architecture for entropy decoding and inverse transform in H.264

Reconfigurable hardware is an effective design option for dealing with the increasing demands of flexibility and computation power in system design. This paper explores techniques to combine the two entropy decoding methods defined in the H.264 standard, context-based adaptive binary arithmetic coding (CABAC) and context-based adaptive variable length coding (CAVLC), using a coarse-grain reconfigurable architecture. An analyzing of the similarities and differences between these two decoding processes shows that CAVLC can be effectively merged into a CABAC decoder. Experimental results show that about 1.5K gates can be saved using the proposed reconfigurable cell (RC) architecture, which corresponds to a 25.4% area savings in the implementation of the CAVLC decoder. Using the idle time in RC arrays, the base cell can be extended to carry out the inverse transform with very limited overhead. The proposed entropy decoder design, which operates at 66 MHz, can decode video sequences at Baseline and Main profiles at Level 3.0 under the real-time constraint.

Self-routing, reconfigurable and fault-tolerant cell array

Many examples of reconfigurable fault-tolerant hardware consist of cells that have the same hardware structure. The arithmetic or logical functions of the cells can be configured. The interconnection of the configured cells can perform a complex task. The interconnection of these cells can be configured too. When some cells are faulty, the function and routing of some cells have to be reconfigured to restore the system's normal function. Most published fault-tolerant schemes cannot automatically achieve fault tolerance without the aid of external software and hardware, or they will require a long routing time to restore normal system function. Some published fault-tolerant schemes require a massive amount of spare cells. A self-routing, reconfigurable and fault-tolerant cell array is presented. When some cells are faulty, spare cells can automatically replace the faulty cells and rerouting can be automatically achieved. The cell array automatically achieves fault tolerance without the aid of external software or hardware, using a small amount of spare cells. In addition, the proposed cell array achieves short routing time to quickly restore normal system function.

Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor

In this paper, we describe the implementation of MorphoSys, a reconfigurable processing system targeted at data-parallel and computation-intensive applications. The MorphoSys architecture consists of a reconfigurable component (an array of reconfigurable cells) combined with a RISC control processor and a high bandwidth memory interface. We briefly discuss the system-level model, array architecture, and control processor. Next, we present the detailed design implementation and the various aspects of physical layout of different sub-blocks of MorphoSys. The physical layout was constrained for 100 MHz operation, with low power consumption, and was implemented using 0.35 μm, four metal layer CMOS (3.3 Volts) technology. We provide simulation results for the MorphoSys architecture (based on VHDL model) for some typical data-parallel applications (video compression and automatic target recognition). The results indicate that the MorphoSys system can achieve significantly better performance for most of these applications in comparison with other systems and processors.