Arithmetic Modules Research Articles

PENGARUH PENERAPAN MODUL AJAR ARITMATIKA SOSIAL PADA KEMAMPUAN PEMECAHAN MASALAH DAN PEMAHAMAN LITERASI FINANSIAL

The tendency in math learning in classrooms is for teachers to explain the material according to what is in the available textbooks without making efforts to develop learning in accordance with the contextual realities of students' daily lives. As a result, students face difficulties in solving mathematical problems when encountering issues different from the example problems provided by the instructor. This research aims to implement a problem-based social arithmetic teaching module based on the contextual approach of Papua. The subsequent application's results will be observed to determine if it has an impact on students' problem-solving abilities and financial literacy comprehension in elementary schools. The research stages include preparation, implementation, and evaluation. Data collection for this research is done through observation, interviews, and tests of students' problem-solving abilities and financial literacy comprehension. The research findings indicate that there is a partial difference in problem-solving abilities and financial literacy comprehension between students taught with the arithmetic teaching module and those taught with the conventional teaching module used in schools. It can be concluded that there is a partial influence on students' problem-solving abilities and financial literacy comprehension taught using the arithmetic teaching module and those taught using the conventional teaching module used in schools.

Area-Delay-Power Efficient VLSI Architecture 2D FIR Filter using Modified Multipliers and Adders

In this paper, a low power, area, and delay 2D Finite Impulse Response (FIR) filter architecture is derived from an analysis of a memory-efficient design. The completely direct-form 2D FIR filter is where the idea of parallel processing is first presented. As a result, the FIR filter may make better use of its memory by reusing its contents. With a block size of L and a filter length of N, a non-separable 2D FIR filter structure is developed and implemented. The FIR filter's arithmetic module makes use of high-speed, low-power multipliers and Carry Look Ahead (CLA) adders, with the output calculated by a pipelined adder unit. Verilog HDL code is used to represent the proposed architecture, and the CADENCE environment's NC Simulator and RTL Compiler synthesis tool are used to verify the design. Existing memory-efficient 2D FIR filter hardware architectures are compared to the produced area, power, and delay reports. Using Modified CLA (MCLA) adders and pipelining, we were able to cut down on power consumption by 44% and delay by 20%. Index Terms: Memory reuse, 2D-FIR filter, Low Power Multiplier, Parallel Prefix Adder, Carry Look Ahead adder, and pipelining.

Integer multiple quantum image scaling based on NEQR and bicubic interpolation

As a branch of quantum image processing, quantum image scaling has been widely studied. However, most of the existing quantum image scaling algorithms are based on nearest-neighbor interpolation and bilinear interpolation, the quantum version of bicubic interpolation has not yet been studied. In this work, we present the first quantum image scaling scheme for bicubic interpolation based on the novel enhanced quantum representation (NEQR). Our scheme can realize synchronous enlargement and reduction of the image with the size of 2 n × 2 n by integral multiple. Firstly, the image is represented by NEQR and the original image coordinates are obtained through multiple CNOT modules. Then, 16 neighborhood pixels are obtained by quantum operation circuits, and the corresponding weights of these pixels are calculated by quantum arithmetic modules. Finally, a quantum matrix operation, instead of a classical convolution operation, is used to realize the sum of convolution of these pixels. Through simulation experiments and complexity analysis, we demonstrate that our scheme achieves exponential speedup over the classical bicubic interpolation algorithm, and has better effect than the quantum version of bilinear interpolation.

DEVELOPMENT OF E-LKPD WITH THE APPLICATION OF PROBLEM BASED LEARNING MODELS IN CLASS VII SOCIAL ARITHMETIC MATERIAL FOR JUNIOR HIGH SCHOOL / MTs

This research resulted in E-LKPD based on the Problem Based Learning (PBL) model on valid and practical Class VII SMP/MTs Social Arithmetic material. E-LKPD is prepared with the help of the Live Worksheet application to improve the quality of learning in schools. One of the learning models that can increase student motivation is the PBL model which directly involves student activity. A 4D development model consisting of define, design, develop, and disseminate stages was used in this study. The experts validated the E-LKPD that had been compiled and conducted small group trials on 6 students of grade VII SMP IT AUFIA GIBS Riau with heterogeneous abilities. The results of the student response questionnaire were obtained 94% with a very practical category. Therefore, it can be concluded that E-LKPD based on the PBL model on social arithmetic material for grade VII SMP/MTs meets the aspects of validity and practicality. This research can also be an alternative guideline choice for teachers in developing E-LKPD in the 2013 Curriculum and can improve students' mathematical reflective thinking skills. Other research has also shown that PBL-based social arithmetic modules are valid, practical, and effective for use in students with different ability levels.

Multiplexer Based Error Efficient Fixed-Width Adder Tree Design for Signal Processing Applications

In copious mixed media applications, humans cannot necessarily discern error free or erroneous outputs, owing to the small range of perception abilities. Crucial information can still be obtained from marginally inexact outputs. Leveraging this, many algorithms such as Digital Signal Processing (DSP), Discrete Cosine Transform (DCT), Motion Compensation (MC) use approximate calculations while still maintaining appreciable computation accuracy. When data processing algorithms are taken into consideration, adders play an important role in the arithmetic module by managing the power and area utilization of the system. A fixed-width adder tree design for approximate calculations is proposed, that uses the trade-off between area and accuracy as the base for analysis. Our design uses 12.42%, 18.17% and 5.05% lesser area compared to the full width adder tree, FX-AT-PT and FX-AT-DT respectively. Additionally, when compared to FX-AT-DT, TFX-AT and ITFX-AT, the proposed design has an improved Maximum Error Distance (MED) of (33.33%, 29.03%), (63.64%, 65.63%) and (38.46%, 35.29%) for N = 8, 16 respectively. To cope with the inaccuracy caused by truncation, the proposed design employs mux-based radix-4 addition coupled with bias estimation. Further, to examine the error performance we have incorporated the proposed design and a few other existing designs into the Walsh-Hadamard Transform (WHT), to process images with different metrics and compare the Peak Signal to Noise Ratio (PSNR) of the images. It was observed that the proposed design showed significant improvement in the PSNR score when compared to ITFX-AT and maintains a score similar to that of FX-AT-PT.

Multiplexer Based Error Efficient Fixed-Width Adder Tree Design for Signal Processing Applications

BACKGROUND: In copious mixed media applications, humans cannot necessarily discern error free or erroneous outputs, owing to the small range of perception abilities. Crucial information can still be obtained from marginally inexact outputs. Leveraging this, many algorithms such as Digital Signal Processing (DSP), Discrete Cosine Transform (DCT), Motion Compensation (MC) use approximate calculations while still maintaining appreciable computation accuracy. METHOD: When data processing algorithms are taken into consideration, adders play an important role in the arithmetic module by managing the power and area utilization of the system. A fixed-width adder tree design for approximate calculations is proposed, that uses the trade-off between area and accuracy as the base for analysis. Our design uses 12.42%, 18.17% and 5.05% lesser area compared to the full width adder tree, FX- AT-PT and FX-AT-DT respectively. Additionally, when compared to FX-AT-DT, TFX-AT and ITFX-AT, the proposed design has an RESULT: To cope with the inaccuracy caused by truncation, the proposed design employs mux-based radix-4 addition coupled with bias estimation. Further, to examine the error performance we have incorporated the proposed design and a few other existing designs into the Walsh-Hadamard Transform (WHT), to process images with different metrics and compare the Peak Signal to Noise Ratio (PSNR) of the images. CONCLUSION: It was observed that the proposed design showed significant improvement in the PSNR score when compared to ITFX-AT and maintains a score similar to that of FX-AT-PT.

Efficient Error Estimation for High-Level Design Space Exploration of Approximate Computing Systems

This article presents an error estimation technique for a data-flow graph (DFG) representation of an approximate computing (AC) circuit. The technique, which may be used during the high-level design of digital circuits, estimates error metrics for the outputs of the approximate circuit. The proposed technique receives as an input, output error characterizations of arithmetic modules in a high-level library. The error modeling of a library module is accomplished by dividing the input (operand) ranges into intervals and then characterizing the output error for different combinations of these input intervals. Subsequently, the error for each combination is stored in a lookup table (LUT). The module error models are integrated into a design space exploration (DSE) framework to evaluate different combinations of exact and approximate realizations of various operations in the DFG. The DSE, which performs error calculation and propagation from inputs to outputs of the target DFG, may be used to explore trade-offs between the output error and other design metrics of the approximate circuit, e.g., energy efficiency. The efficacy of the proposed method is assessed for three image processing benchmarks. Results for these benchmarks demonstrate that the framework can efficiently generate the Pareto frontier (PF) in the trade-off space of accuracy versus energy efficiency for the targeted benchmarks. Compared to a purely simulation-based exploration, the proposed technique provides an average of 92 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> speed improvement.

Social Arithmetics Module Based on Islamic Values and Realistic Mathematics Education to Improve Students’ Problem-Solving Skills

Mathematics learning must be made more exciting and meaningful to overcome the perception that mathematics is a tricky subject. Students must be facilitated to build their knowledge through mathematics learning linked to realistic problems and integrated with Islamic values so that they can solve relevant daily problems. This research aims to develop a Social Arithmetic module based on Islamic values ​​and Realistic Mathematics Education (RME) to help junior high school students improve their problem-solving skills. This research uses R&amp;D with the ADDIE development model. The development of the mathematics module consists of three stages, namely the preliminary, development, and evaluation stages. The resulting module prototype has been assessed as valid by material and media experts. Meanwhile, based on student and teacher responses to the questionnaire, the module was proven suitable for use in mathematics learning. In addition, the results of the paired t-test stated that the module was effective in improving students' problem-solving skills. Therefore, this research concluded that the Social Arithmetics module based on Islamic values ​​and RME that were developed has met the valid and practical criteria and has proven effective in improving the problem-solving abilities of seventh-grade junior high school students.

Design and Analysis of Multiplexer based Approximate Adder for Low Power Applications

Low power consumption is crucial for error-acceptable multimedia devices, with picture compression approaches leveraging various digital processing architectures and algorithms. Humans can assemble useful information from partially inaccurate outputs in many multimedia applications. As a result, producing exact outputs is not required. The demand for an exact outcome is fading because new innovative systems are forgiving of faults. In the domain where error-tolerance is accepted, approximate computing is a new paradigm that relaxes the requirement for an accurate modeling while offering power, time, and delay benefits. Adders are an essential arithmetic module for regulating power and memory usage in digital systems. The recent implementation and use of approximate adders have been supported by trade-off characteristics such as delay, lower power consumption. This study examines the delay and power consumption of conventional and approximate adders. Also, a simple, fast, and power-efficient multiplexer-based approximate adder is proposed, and its performance outperforms the adders compared with existing adders. The proposed adder can be utilized in error-tolerant and various digital signal processing applications where exact results are not required. The proposed and existing adders are designed using EDA software for the performance calculations. With a delay of 81 pS, the proposed adder circuit reduces power consumption compared to the exact one. The experiment shows that the designed approximate adder can be used to implement circuits for image processing systems because it has a smaller delay and uses less energy.

Fitting ideals and various notions of equivalence for modules

Recently there has been a lot of work on determining the Fitting ideals of arithmetic modules over groups rings, first and foremost of class groups and their Pontryagin duals. In particular, it has turned out that these Fitting ideals are usually non-principal and may be described, up to principal ideals, in terms of group-theoretical information only. The involved principal ideal factors are essentially given by values of equivariant L-functions. The present paper is not concerned with these L-functions but rather focuses on a systematic understanding of the Fitting ideals up to principal factors. To this end, we develop a certain notion of “equivalence of modules” over suitable commutative rings R. We establish that understanding the equivalence of R-modules is closely related to the classification of R-lattices. We also offer a construction of a category, inspired by derived categories, which embodies our new notion of “equivalence”.

Distributional consequences of climate change impacts on residential energy demand across Italian households

The paper evaluates the macroeconomic and distributional implications for Italian households and regions of both climate change impacts and a carbon tax. We use a recursive-dynamic general equilibrium model to evaluate aggregate changes in prices, income and expenditure, and a sequential arithmetic micro-simulation module to downscale them to the household level. Climate change impacts are regressive, adding to the already regressive effects of a carbon tax. Wealthy households reduce expenditure on gas and petroleum fuels the most, whereas households in the lowest deciles increase electricity expenditure relatively more. Climate and policy impacts differ significantly also within income groups, reflecting regional variations in the size of climate shocks, the prevalent climate conditions, and the energy mix. We highlight a new emerging risk related to those households that will be exposed to higher temperatures and will not be able to sustain the electricity expenditure needed for adaptation, and we emphasize the importance of accounting for the distributional consequences of climate change impacts when designing climate policies.

A Modular Framework for Generic Quantum Algorithms

We describe a general-purpose framework to design quantum algorithms. This framework relies on two pillars: a basic data structure called quantum matrix and a modular structure based on three quasi-independent modules. These latter include a loading module, a tool-kit of basic quantum arithmetic operations and a read-out module. We briefly discuss the loading and read-out modules, while the arithmetic module is analyzed in more depth. Eventually, we give explicit examples regarding the manipulation of generic oracles and hint at possible applications.

A Fully Analog Autonomous QRS Complex Detection and Low-Complexity Asystole, Extreme Bradycardia, and Tachycardia Classification System

This article presents a power-efficient fully analog classifier architecture for the detection of critical cardiac abnormalities, i.e., asystole, extreme bradycardia, and tachycardia. To reduce power consumption and hardware complexity, an analog QRS complex detection circuit and arithmetic counter-based classification modules are introduced. The QRS detection circuit is autonomous and consumes an average current of 34 nA only, vis-à-vis state-of-the-art QRS detection designs that are digital signal processor (DSP) assisted and consume tens of microwatts of power. Furthermore, a heart-rate estimator provides the number of QRS complexes per minute. Each of the proposed modules is successfully validated through real electrocardiogram (ECG) test signals taken from the PhysioNet database. The proposed beat detector circuit exhibits a sensitivity of 97.85% and a positive prediction of 98.3%. Experimental results based on bedside monitor data show that the proposed classification module provides an overall sensitivity of 96.25% and a positive prediction of 96.97%. The complete classification architecture, implemented fully on analog platform, is simulated in the UMC 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process and consumes 119-nW power with an active silicon area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$450\times 800~\mu \text{m}$ </tex-math></inline-formula> . Moreover, the low-power implementation makes it suitable for long-term battery-operated remote ECG monitoring systems.

Low-Power Approximate RPR Scheme for Unsigned Integer Arithmetic Computation

A scheme often used for error tolerance of arithmetic circuits is the so-called Reduced Precision Redundancy (RPR). Rather than replicating multiple times the entire module, RPR uses reduced precision (inexact) copies to significantly reduce the redundancy overhead, while still being able to correct the largest errors. This paper focuses on the low-power operation for RPR; a new scheme is proposed. At circuit level, power gating is initially utilized in the arithmetic modules to power off one of the modules (i.e., the exact module) when the inexact modules&#x2019; error is smaller than the threshold. The proposed design is applicable to (unsigned integer) addition, multiplication, and MAC (multiply and add) by proposing RPR implementations that reduce the power consumption with a limited impact on its error correction capability. The proposed schemes have been implemented and tested for various applications (image and DCT processing). The results show that they can significantly reduce power consumption; moreover, the simulation results show that the Mean Square Error (MSE) at the proposed schemes&#x2019; output is low.

A LOW POWER AND HIGH SPEED APPROXIMATE ADDER FOR IMAGE PROCESSING APPLICATIONS

Low power is an essential requirement for suitable multimedia devices, image compression techniques utilizing several signal processing architectures and algorithms. In numerous multimedia applications, human beings are able to congregate practical information from somewhat erroneous outputs. Therefore, exact outputs are not necessary to produce. In Digital signal processing system, adders play a vital role as an arithmetic module in fixing the power and area utilization of the system. The trade off parameters such as area, time and power utilization also the fault tolerance environment of few applications have employed as a base for the adverse development and use of approximate adders. In this paper, various types of existing adders, approximate adders are analyzed based on the area, delay and power consumption. Also an approximate, high speed and power efficient adder is proposed which yields the better performance than the existing adders. It can be used in various image processing applications, data mining and where the accurate outputs are not needed. The existing and proposed approximate adders are simulated by using Xilinx ISE for time and area utilization. Power simulation has been done by using Microwind Software.

High speed Power efficient Vedic arithmetic modules on Zedboard‐Zynq‐7000 FPGA

SummaryHardware implementation of dedicated arithmetic modules is inevitable for any signal processing system development and computational complexity of such modules could be significantly reduced with improved performance by utilizing Vedic algorithms. Five novel Vedic arithmetic modules for multiplication, square, cube, square root, and cube root are implemented on Zedboard Zynq‐7000 FPGA. A novel 4:2 compressor that uses only primitive gates in critical path is proposed to reduce partial products in the Urdhwa Tiryakhbhyam parallel multiplier achieving the best performance reported so far. Elimination of recursiveness in Antyayordashekepi‐Dwanda squarer results in reduced area while modified Dwanda squarer results in reduced delay. Anurupyena cubic module with 4:2 and 5:2 compressors is implemented from which the one with 4:2 compressor provides the least delay with more than 50% reduction with respect to that of reported cube modules. Modified Vargamula square root and modified cube root modules are also implemented incorporating pipelining, priority encoder, and padding of zero's to achieve better performance. In addition to the delay, in terms of area occupancy, power, and energy consumed (power‐delay‐product), better or comparable performance is also achieved by all the above‐mentioned modules implemented. The dedicated multiplier is used in a 64‐point FFT Implementation and results similar to existing structures are obtained.

Adversarial Hardware With Functional and Topological Camouflage

The lately attack on the Qualcomm’s Snapdragon chip reminds us security risks related to digital arithmetic circuits. Most system designers neglect the employed computer arithmetic algorithms or their implementation details. Arithmetic circuits are therefore usually used as “black box” units that are instantiated by third-party intellectual-property core or electronic design-automation tool vendors. In this brief, we propose the first most-significant digit-first arithmetic-based hardware Trojan attack by addressing the questions of where to insert and with what . First, we demonstrate how functional camouflage is achieved. Certain arithmetic modules can be quietly replaced with functionally equivalent ones, which we term functionally camouflaged Trojans. Next, we introduce a topologically camouflaged Trojan by employing graph-centrality analysis on rare behaviours in the circuit. The proposed approach is applicable to any digital computing scenarios. Experimental results on a financial computing system demonstrate that completely inaccurate numeric results are yielded, along with an up-to 91.6% numerical error tested.

A cross-layer approach towards developing efficient embedded Deep Learning systems

With the evolution of Smart Cyber–Physical Systems (CPS) and Internet-of-Things (IoT), the number of connected (intelligent) devices is increasing at an exponential rate, and so as the data being produced by them. To process this gigantic amount of data, algorithms are being proposed that can extract information from it without much human intervention. Deep Learning (DL) is one of the fields which has recently shown significant potential towards this direction, as it allows computational models (deep neural networks) composed of multiple processing layers to learn autonomously to interpret data with the help of the back-propagation algorithm. However, state-of-the-art deep neural networks (DNNs) are highly resource-hungry. To enable the use of DNNs in resource constraint mobile devices, several optimization techniques have been proposed at different abstraction layers of the computing stack. In this paper, we highlight the main categories of the optimization techniques and present a cross-layer methodology for developing performance/energy efficient DNN-based systems. At the software level, we employ a structured pruning technique along with the quantization of inputs and network parameters to reduce the computational complexity and memory requirements for the DNN inference process. At the hardware level, exploiting the error resilience characteristics of the DNNs, we make use of functional approximations in the arithmetic modules to further improve the efficiency of DNN-based systems.

Framework-based Arithmetic Datapath Generation to Explore Parallel Binary Multipliers

Arithmetic modules usually have a significant impact on performance, circuit area, energy, and power in digital circuits of DSP (Digital Signal Processing). Exploring implementation trade-offs in these circuits is of utmost importance in low-power and low-cost devices such as sensors in IoT devices which often have stringent requirements. Multipliers are of particular concern due to their ubiquitous use in DSP algorithms and their inherent implementation complexity. This work proposes a framework to efficiently generalize and explore different compositions of arithmetic operators with an emphasis on parallel binary multipliers, guiding the designer through the micro-architecture development. Several partial product encoders were combined with multiple compression trees to generate multipliers that were synthesized in a commercial 65 nm to obtain area, power, and timing results.

A Framework for Hardware Trojan Vulnerability Estimation and Localization in RTL Designs

As the design complexity increases, the attack space for malicious modifications in the design also increases. Attackers in untrusted phases during the Integrated Circuit (IC) design cycle may embed a Hardware Trojan (HT). A potential and stealthy HT is triggered with nets that rarely switch during regular circuit operation. Detection of HT in the host design requires exhaustive simulation to activate the HT during pre- and post-silicon. For analyzing HT vulnerability, we present a modeling approach to capture the rare nets using word-level statistics of the inputs. It provides the capability to locate macro-block(s) in a Register Transfer Level (RTL) design to estimate the rare triggering nets. Given RTL description of a design, we decompose the design into a subset of basic arithmetic modules, each of which is pre-characterized (empirically and analytically) by which we evaluate the design for quick estimation of HT vulnerable macro-block(s). The relative impact of mapping the design to a particular module from its analytical characteristics can be used to detect “low activity” and “local regions” without expensive low-level simulation. We implement the model over a wide range of input signal statistics for Digital Signal Processing (DSP) Intellectual Property (IP) cores, and the average estimation error for different bit-widths and correlations is less than 2%. We also propose cost functions during mapping and show that identification of rare activity blocks (nets) at a higher level is closely related to the simulation results. The final mapping that identifies the candidate arithmetic modules can minimize HT vulnerability in design at the cost of accuracy.