Arithmetic Logic Unit Research Articles

Attenuated processing of task-irrelevant speech and other auditory stimuli: fMRI evidence from arithmetic tasks.

When performing cognitive tasks in noisy conditions, the brain needs to maintain task performance while additionally controlling the processing of task-irrelevant and potentially distracting auditory stimuli. Previous research indicates that a fundamental mechanism by which this control is achieved is the attenuation of task-irrelevant processing, especially in conditions with high task demands. However, it remains unclear whether the processing of complex naturalistic sounds can be modulated as easily as that of simpler ones. To address this issue, the present fMRI study examined whether activity related to task-irrelevant meaningful speech is attenuated similarly as that related to meaningless control sounds (nonsense speech and noise-vocoded, unintelligible sounds). The sounds were presented concurrently with three numerical tasks varying in difficulty: an easy control task requiring no calculation, a 'routine' arithmetic calculation task and a more demanding 'creative' arithmetic task, where solutions are generated to reach a given answer. Consistent with their differing difficulty, the tasks activated fronto-parieto-temporal regions parametrically (creative > routine > control). In bilateral auditory regions, activity related to the speech stimuli decreased as task demands increased. Importantly, however, the attenuation was more pronounced for meaningful than nonsense speech, demonstrating that distractor type can strongly modulate the extent of the attenuation. This also suggests that semantic processing may be especially susceptible to attenuation under conditions with increased task demands. Finally, as this is the first study to utilize the 'creative' arithmetic task, we conducted exploratory analyses to examine its potential in assessing neural processes involved in mathematical problem-solving beyond routine arithmetic.

Design and Implementation of a 3-bit ALU with Integrated 7-Segment Display on FPGA

This paper describes the design and implementation of a 3-bit Arithmetic Logic Unit (ALU) with integrated 7-segment display output, deployed on an FPGA platform. The objective of this project is to efficiently perform and display basic arithmetic and logic operations, including addition, subtraction, AND, OR, XOR, and NOT, with an FPGA-based ALU. A control signal selects the operation, and the ALU's 3-bit result is decoded and displayed on a 7-segment interface for clear output visualization. The ALU design is coded in Verilog and includes logic to manage carry and overflow in arithmetic functions. A display decoder module maps the ALU’s binary output to the correct LED segments on the 7-segment display, allowing intuitive real-time readout of operation results. The system was synthesized, simulated, and tested on an Artix-7 FPGA using the Xilinx Vivado development environment, achieving accurate and expected functionality across all operations. This work showcases the effectiveness of FPGA technology in integrating computation and display within a compact digital system, with potential applications in both educational and embedded system design settings where real-time processing and display are essential. Keywords: FPGA, ALU, 7-segment display, Verilog, Digital system design, Embedded computing.

The brain under pressure: Exploring neurophysiological responses to cognitive stress

Stress is an increasingly dominating part of our daily lives and higher performance requirements at work or to ourselves influence the physiological reaction of our body. Elevated stress levels can be reliably identified through electroencephalogram (EEG) and heart rate (HR) measurements. In this study, we examined how an arithmetic stress-inducing task impacted EEG and HR, establishing meaningful correlations between behavioral data and physiological recordings. Thirty-one healthy participants (15 females, 16 males, aged 20 to 37) willingly participated. Under time pressure, participants completed arithmetic calculations and filled out stress questionnaires before and after the task. Linear mixed effects (LME) allowed us to generate topographical association maps showing significant relations between EEG features (delta, theta, alpha, beta, and gamma power) and factors such as task difficulty, error rate, response time, stress scores, and HR. With task difficulty, we observed left centroparietal and parieto-occipital theta power decreases, and alpha power increases. Furthermore, frontal alpha, delta and theta activity increased with error rate and relative response time, while parieto-temporo-occipital alpha power decreased. Practice effects on EEG power included increases in temporal, parietal, and parieto-occipital theta and alpha activity. HR was positively associated with frontal delta, theta and alpha power whereas frontal gamma power decreases. Significant alpha laterality scores were observed for all factors except task difficulty and relative response time, showing overall increases in left parietal regions. Significant frontal alpha asymmetries emerged with increases in error rate, sex, run number, and HR and occipital alpha asymmetries were also found with run number and HR. Additionally we explored practice effects and noted sex-related differences in EEG features, HR, and questionnaire scores. Overall, our study enhances the understanding of EEG/ECG-based mental stress detection, crucial for early interventions, personalized treatment and objective stress assessment towards the development of a neuroadaptive system.

ACTF: An efficient lossless compression algorithm for time series floating point data

The volume of time series data across various fields is steadily increasing. However, this unprocessed massive data challenges transmission efficiency, computational arithmetic, and storage capacity. Therefore, the compression of time series data is essential for improving transmission, computation, and storage. Currently, improving time series floating-point coding rules is the primary method for enhancing compression algorithms efficiency and ratio. This paper presents an efficient lossless compression algorithm for time series floating point data, designed based on existing compression algorithms. We employ three optimization strategies data preprocessing, coding category expansion, and feature refinement representation to enhance the compression ratio and efficiency of compressing time-series floating-point numbers. Through experimental comparisons and validations, we demonstrate that our algorithm outperforms Chimp, Chimp128, Gorilla, and other compression algorithms across multiple datasets. The experimental results on 30 datasets show that our algorithm improves the compression ratio of time series algorithms by an average of 12.25% and compression and decompression efficiencies by an average of 27.21%. Notably, it achieves a 24.06% compression ratio improvement on the IOT1 dataset and a 42.96% compression and decompression efficiency improvement on the IOT4 dataset.

Implementation of adders using XOR gates in quantum-dot cellular automata with physical verification

Abstract This paper presents a promising approach to nanoscale computing, offering significant advantages through the QCA technology. It suggests a highly efficient, scalable, and reliable multilayered QCA half and full adder circuits, leveraging a three-input QCA XOR gate. The proposed full adder layout demonstrates significant improvements in various parameters, including area, latency, and energy dissipation. In particular, it offers 17% greater area efficiency and utilizes 14 fewer cells compared to the best work existing work. We thoroughly evaluated energy dissipation using the QCADesigner-E tool. We also examined the cost functions, with a QCA-specific cost of 22 units, which is ~37% better than earlier designs. The architecture is strategically designed with externally accessible input and output nodes to ensure seamless scalability. Physical reliability is ensured through kink energy calculations for the suitability of higher-order circuit designs. Practical applications of the proposed blocks include their use in arithmetic logic units (ALUs), digital signal processors, and other modern processing and computing systems. This work sets a new benchmark for future developments in QCA technology, offering a robust, efficient, and versatile solution for advanced nano-processing and computing systems.

Analysis of Serial Foot Radiographs to Determine Foot Height Multipliers.

The multiplier method is an arithmetic calculation that estimates the amount of growth remaining until skeletal maturity. When predicting lower limb length discrepancy, differences in foot height are added to femur and tibia discrepancies. Foot height multipliers have not been calculated using radiographic measurements, so it is unclear whether foot height develops at the same pace as the femur and tibia. This study used serial images to calculate foot height multipliers and compared them to published lower limb and foot length multipliers. The Bolton Brush radiograph collection was used to measure foot height on the lateral foot view. Multipliers were calculated for ages with at least 10 serial study visits. 212 patients (2195 radiographs) were included in the study (102 female, 110 male patients). Foot height multipliers were calculated for ages 0 to 17 years (females) and 0 to 18 years (males). Multipliers decreased with age, but qualitatively plateau at age 13 (females) and age 15 (males). Lower extremity multipliers have a more dramatic growth curve, indicating comparatively greater lower extremity growth after birth. However, when comparing the limb length discrepancy calculation using the lower extremity multiplier versus the foot height multiplier for the foot portion, the difference was negligible. This paper provides a database of foot height multipliers. Foot height seems to grow on a different trajectory than other lower limb components, confirming that one should consider separate multiplier values. The difference created by the foot height multiplier versus the lower extremity multiplier appears to be modest. Separate use of the foot height multiplier may only be necessary for young children with large foot height discrepancies, but further study to confirm the lack of impact of the foot height multiplier on limb length discrepancy calculations is needed. Our data were derived from normal children, so it is unknown if the presence of a talo-calcaneal coalition would affect foot height on the involved side. Level III-retrospective comparative study.

Analog Implementation of a Spiking System for Performing Arithmetic Logic Operations on Mixed‐Signal Neuromorphic Processors

In recent years, physical limitations in the integration of transistors in computers have forced the search for low‐computational‐power alternatives in hardware design. Although doubts may arise regarding the limit of the relationship between performance and power consumption in computers, these disappear when considering the brain, which is one of the most efficient computing systems. In this way, bioinspired applications try to benefit from the low‐power consumption present in the biological nervous system. Previous work has shown the feasibility of implementing spiking neural networks that operate in a Boolean manner on digital platforms, such as SpiNNaker, using basic logic gates and a spiking memory, which suggests the potential for constructing a low‐power consumption spiking computer. This work takes a first step in the implementation of a spiking central processing unit by developing an arithmetic logic unit, which is an essential block for instruction execution, demonstrating its correct operation on Dynap‐SE1. The results confirm the feasibility of using this Boolean approach on this platform, despite certain limitations in the number of inputs and operating frequencies of the blocks, and pave the way for the construction of a spiking computer.

Investigation of PNN Inverter-Based Low PDP 12T GNRFET Full Adder for VLSI Signal Processing Applications

When an adder circuit, which uses less power and operates at a higher speed, is introduced as a fundamental building block, the multiplier, arithmetic and logic unit (ALU), and digital system’s power delay product (PDP) performance can be easily improved. The graphene nanoribbon field effect transistor (GNRFET) used in very large-scale integrated (VLSI) circuits was developed in the submicron regime and offers superior electrical properties to the MOS transistor. This research paper introduces a full-adder circuit containing twelve GNRFETs (12T GF-FA). Calculations have been made about the introduced 12T GF-FA’s power usage, speed, PDP and leakage power. A few of the existing full adders with 8–32 transistors are compared to the performance of the newly proposed 12T GF-FA in terms of power and delay. For this comparison, some conventional full adders with 8–32 transistors have been implemented using 16[Formula: see text]nm technology GNRFETs. The pull-down network of the suggested adder has two stacked GNRFETs. The proposed adder’s current conduction and power consumption are reduced by the use of stacked transistors. According to the simulation results, the PDP of the suggested 12T GF-FA is 73.2–99% lower when compared to other full adders considered state-of-the-art. Additionally, it has been researched and documented how variations in the PVT and GNRFET parameters affect the performance of full-adder circuits. The proposed adder, with its low PDP, is especially suitable for VLSI signal processing applications. The simulation was carried out using the HSPICE simulation tool and the 16[Formula: see text]nm MOS-GNRFET model.

Prepare Linear Distributions with Quantum Arithmetic Units.

Quantum arithmetic logic units (QALUs) perform essential arithmetic operations within a quantum framework, serving as the building blocks for more complex computations and algorithms in quantum computing. In this paper, we present an approach to prepare linear probability distributions with quantum full adders. There are three main steps. Firstly, Hadamard gates are applied to the two input terms, preparing them at quantum states corresponding to uniform distribution. Next, the two input terms are summed up by applying quantum full adder, and the output sum is treated as a signed integer under two's complement representation. By the end, additional phase -1 is introduced to the negative components. Additionally, we can discard either the positive or negative components with the assistance of the Repeat-Until-Success process. Our work demonstrates a viable approach to prepare linear probability distributions with quantum adders. The resulting state can serve as an intermediate step for subsequent quantum operations.

Multi-Layer QCA Reversible Full Adder-Subtractor Using Reversible Gates for Reliable Information Transfer and Minimal Power Dissipation on Universal Quantum Computer

The effects of quantum mechanics dominate nanoscale devices, where Moore’s law no longer holds true. Additionally, with the recent rapid development of quantum computers, the development of reversible gates to overcome the problems of energy and information loss and the nano-level quantum-dot cellular automata (QCA) technology to efficiently implement them are in the spotlight. In this study, a full adder-subtractor, a core operation of the arithmetic and logic unit (ALU), the most important hardware device in computer operations, is implemented as a circuit capable of reversible operation using QCA-based reversible gates. The proposed circuit consists of one reversible QCA gate and two Feynman gates and is designed as a multi-layer structure for efficient use of area and minimization of delay. The proposed circuit is tested on QCADesigner 2.0.3 and QCADesigner-E 2.2 and shows the best performance and lowest energy dissipation. In particular, it shows tremendous improvement rates of 180% and 562% in two representative standard design cost indicators compared to the best existing studies, and also shows the highest circuit average output polarization.

FPGA Implementation of Sliding Mode Control and Proportional-Integral-Derivative Controllers for a DC–DC Buck Converter

DC–DC buck converters have been designed by incorporating different control stages to drive the switches. Among the most commonly used controllers, the sliding mode control (SMC) and proportional-integral-derivative (PID) controller have shown advantages in accomplishing fast slew rate, reducing settling time and mitigating overshoot. The proposed work introduces the implementation of both SMC and PID controllers by using the field-programmable gate array (FPGA) device. The FPGA is chosen to exploit its main advantage for fast verification and prototyping of the controllers. In this manner, a DC–DC buck converter is emulated on an FPGA by applying an explicit multi-step numerical method. The SMC controller is synthesized into the FPGA by using a signum function, and the PID is synthesized by applying the difference quotient method to approximate the derivative action, and the second-order Adams–Bashforth method to approximate the integral action. The FPGA synthesis of the converter and controllers is performed by designing digital blocks using computer arithmetic of 32 and 64 bits, in fixed-point format. The experimental results are shown on an oscilloscope by using a digital-to-analog converter to observe the voltage regulation generated by the SMC and PID controllers on the DC–DC buck converter.

Design and implementation in power-efficient and thermal conductivity of vedic processor for embedded applications

An embedded system that handles critical applications requires power economy, performance and thermal management, and an efficient Vedic processor with highly efficienct thermal conductivity. The proposed contemporary processor architecture has been designed to use Vedic mathematics and elaborate power and thermal optimization approaches to formulate an Arithmetic Logic Unit (ALU). This ALU is based on Vedic Sutras to enable quick computation, high precision floating point operations, and low power consumption. Since thermal management leads to energy loss in the form of heat, the embedded processor’s thermal conductivity is enhanced using novel materials and unique ways of heat dissipation. This improves performance as well as power efficiency. The proposed approach uses extensive simulation thermal analysis by EDA tools to build an optimised embedded processor that consumes 35% less power, has 40% high thermal conductivity, is 25% faster, and utilizes 15% less area when compared to conventional embedded processors. This paper helps in furthering embedded systems research by showing how old mathematical ideas can be used in a new engineering approach to solve current technology issues. The suggested novel embedded system is more efficient and thermally resistant for IOT, mobile computing, and industrial control systems.

Ethno-Science, Technology, Engineering, and Mathematics (EthnoSTEM) Ideas in the Sama Mat-Weaving

Mat weaving has been culturally and economically significant among the Sama ethnolinguistic group since time immemorial. This study sought to find concepts and processes of ethnoscience, ethnotechnology, ethnoengineering, and ethnomathematics (ethnoSTEM) present in weaving tepo, a hand-woven mat of the Sama, made from indigenously processed leaves of pandan or screw pine (Pandanus tectorius). To determine ethnoSTEM ideas, concepts, and processes in tepo weaving, an ethnography was conducted involving five female mat weavers in a coastal village in Tawi-Tawi’s major producer of tepo, the Municipality of Tandubas. Data were gathered primarily through observations during a monthlong community immersion. Results revealed that Ethnotechnology tools were in the form of bolo, pandan-presser, pandan slitter, traditional stove, bamboo scalp scratcher, and other local cooking tools, with each tool exhibiting unique characteristics and functions needed for weaving. Ethnoengineering was evident in preparing pandan strips to create, bleach, and dye pandan strips for weaving and fastening the tepo. Ethnomathematics comprised primitive length measurement, arithmetic calculations, ratio and proportion, linear and quadratic equations, sinusoidal functions, basic geometric concepts, circles, symmetries, and isometries. Ethnoscience was observed in the processes determining the dyeability of pandan strips, as well as in the procedures employed in its softening and bleaching. It is concluded that the concepts and ideas of ethnoSTEM found in Sama weaving of tepo are loaded with scientific affluence that should be preserved to preclude them from fading to oblivion.

Comparative analysis of Vedic multiplier using Vedic sutras with existing multipliers in biomedical application

In today's computer world, a lot of real-time applications require rapid processing units. Arithmetic Logic Units (ALU) and Multiply-Accumulate (MAC) are the fundamental parts of these circuits and are necessary for their effective and rapid operation. The most significant prevalent part of digital signal processing devices is multipliers. The multiplier, adder, and registers need to be changed in order to maintain accuracy and increase execution speed, which will improve the performance of the ALU and MAC. The development of greater multipliers is being given priority for application in processors because of the increasing constraints on latency. To accelerate multiplication, it is essential to develop quicker multipliers. Vedic multipliers are preferred over different current expansions due to their low power consumption, fast operation, and efficient use of space. Vedic mathematics-based algorithms are often utilized to build quick, low-power multipliers. In addition to simulation results, this section covers the four sutras of Vedic mathematics: Urdhva Tiryakbhyam, Ekadhikena Purvena, Ekanyunena Purvena, and Nikhilam. Vedic multipliers are also compared to a variety of modern multipliers, including booth, Wallace, and array multipliers. All of the sutras are evaluated according to area, speed, power, propagation delay, and mean relative error (MRE) in the current research. The results of the study will be applied in the biomedical field.

High performance rapid single-flux-quantum bit-slice arithmetic logic unit

Two optimization technologies, namely, bypass and carry-control optimization, were demonstrated for enhancing the performance of a bit-slice Arithmetic Logic Unit (ALU) in 2n-bit Rapid Single-Flux-Quantum (RSFQ) microprocessors. These technologies can not only shorten the calculation time but also solve data hazards. Among them, the proposed bypass technology is applicable to any 2n-bit ALU, whether it is bit-serial, bit-slice or bit-parallel. The high performance bit-slice ALU was implemented using the 6 kA/cm2 Nb/AlOx/Nb junction fabrication process from Superconducting Electronics Facility of Shanghai Institute of Microsystem and Information Technology. It consists of 1693 Josephson junctions with an area of 2.46 × 0.81 mm2. All ALU operations of the MIPS32 instruction set are implemented, including two extended instructions, i.e., addition with carry (ADDC) and subtraction with borrow (SUBB). All the ALU operations were successfully obtained in SFQ testing based on OCTOPUX and the measured DC bias current margin can reach 86% - 104%. The ALU achieves a 100% utilization rate, regardless of carry/borrow read-after-write correlations between instructions.

Correction: Oldrieve, R.M. Teaching K–3 Multi-Digit Arithmetic Computation to Students with Slow Language Processing. Computation 2024, 12, 128

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Typical Mathematical Education Cannot Predict Non‐Verbal Number Sense

ABSTRACTFormal education would promote symbolic number processing ability, but the relationship between non‐symbolic number sense and mathematical education remains controversial. The current investigation hypothesized that non‐symbolic number sense is independent from the limited human experience of mathematical education, while symbolic number processing could be influenced by related closely to mathematical education. Experiment 1 compared both non‐symbolic number sense and arithmetic computation of undergraduates majoring in STEM fields and humanities. Experiment 2 compared homologous undergraduates from China and Kyrgyzstan in non‐symbolic number sense and mathematical cognitive processing. Both of two experiments found that mathematical education was significantly associated with symbolic mathematics, but not with non‐symbolic number sense. The results suggest that while mathematical education might improve symbolic mathematics, it does not alter non‐symbolic number sense.

Reversible arithmetic and logic unit using a novel reversible NRRG gate in quantum dot technology

Quantum-dot Cellular Automata (QCA) has become one of the promising studies for nano-scale computing. QCA is one of the candidate technologies to be replaced with CMOS technology. QCA technology not only reduces power consumption and delay but also increases operating frequency and speed. The arithmetic logic unit is the essential component in a processor that performs arithmetic and logical operations. This paper presents a novel 5 × 5 reversible logic gate called the NRRG (Norouzi_Rasouli Reversible Gate) which can be used as the basic building block of 4:1 and 8:1 reversible multiplexers. Then, we have designed a RALU (reversible arithmetic and logic unit) using this gate. Our design can perform 20 operations such as AND, NAND, OR, XOR, XNOR, COPY, addition, and increment. The proposed QCA RALU requires 0.44 μm2 area, 480 QCA cells, and 10 clock phases. The proposed design needs less cell count, delay, and cost of QCA compared to previous works. The structure is implemented without any rotated cells and only uses one layer which improves the manufacturability of the design. The architectures are designed and simulated using QCA Designer 2.0.3.

High-Linearity Ta2O5 Memristor and Its Application in Gaussian Convolution Image Denoising.

In the image Gaussian filtering process, convolving with a Gaussian matrix is essential due to the numerous arithmetic computations involved, predominantly multiplications and additions. This can heavily tax the system's memory, particularly with frequent use. To address this issue, a W/Ta2O5/Ag memristor was employed to substantially mitigate the computational overhead associated with convolution operations. Additionally, an interlayer of ZnO was subsequently introduced into the memristor. The resulting Ta2O5/ZnO heterostructure layer exhibited improved linearity in the pulse response, which enhanced linearity facilitates easy adjustment of the conductance magnitude through a linear mapping of the number of pulses and the conductance. Subsequently, the conductance of the W/Ta2O5/ZnO/Ag bilayer memristor was employed as the weights for the convolution kernel in convolution operations. Gaussian noise removal in image processing was achieved by assembling a 5 × 5 memristor array as the kernel. When denoising was performed using memristor arrays, compared to denoising achieved through Gaussian matrix convolution, an average loss of less than 5% was observed. The provided memristors demonstrate significant potential in convolutional computations, particularly for subsequent applications in convolutional neural networks (CNNs).

Eye tracking study in children to assess mental calculation and eye movements

Eye tracking technology is a high-potential tool for different mathematic cognition research areas. Moreover, there is a dire need for more studies that provide detailed information on the quality of registered eye data. This study aimed to illustrate the applicability of eye tracking in the examination of mathematical cognition, focusing specifically on primary school students completing a computerized mental arithmetic task. Results suggested that the eye tracking device effectively captured high-quality eye movement data when primary school children engaged in this specific task. Furthermore, significant negative correlations have been found between task performance and number of eye fixations. Finally, eye movements distinctions between “Areas of Interest” have been found, indicating different visual tracking associated with different components of arithmetic calculations. This study underscores the extensive possibilities for future research employing eye tracking devices during computerized calculation tasks as assessment tools to explore the complex visual and cognitive processes.