Arithmetic Logic Unit Research Articles (Page 1)

A parametric machine learning tool with many applications is the radial basis function (RBF) network, which has been incorporated into various classification and regression problems. A key component of these networks is their radial functions. These networks acquire adaptive capabilities through a technique that consists of two stages. The centers and variances are computed in the first stage, and in the second stage, which involves solving a linear system of equations, the external weights for the radial functions are adjusted. Nevertheless, in numerous instances, this training approach has led to decreased performance, either because of instability in arithmetic computations or due to the method’s difficulty in escaping local minima of the error function. In this manuscript, a three-stage method is suggested to address the above problems. In the first phase, an initial estimation of the value ranges for the machine learning model parameters is performed. During the second phase, the network parameters are fine-tuned within the intervals determined in the first phase. Finally, in the third phase of the proposed method, a local optimization technique is applied to achieve the final adjustment of the network parameters. The proposed method was evaluated on several machine learning models from the related literature, as well as compared with the original RBF training approach. This methodhas been successfully applied to a wide range of related problems reported in recent studies. Also, a comparison was made in terms of classification and regression error. It should be noted that although the proposed methodology had very good results in the above measurements, it requires significant computational execution time due to the use of three phases of processing and adaptation of the network parameters.

A Ternary Arithmetic Logical Unit (TALU) combines the adder, subtractor, and Ex-OR into a single module. Therefore, a novel design is proposed in this manuscript for TALU using multiple controlled reversible gates and the Gate Diffusion Input (GDI) technique-based multiplexer (TALU-GDI-MUX). The proposed ternary arithmetic logic unit (ALU) architecture includes a function selector, transmission gates (TG), and a rewritten functional module for abstraction. The functional module chooses the arithmetical or logical operations. The functional modules are designed using multiple controlled reversible gates with a GDI technique-based multiplexer, which provides the output of TALU operation, such as TALU1 and TALU0. This reduces transistor usage and power consumption while maximizing the speed. The TALU-GDI-MUX approach is implemented in HSPICE experimental tools. The TALU-GDI-MUX attains 23.53%, 15.64%, and 33.85% lower Delay, 32.43%, 14.84%, and 15.75% higher speed when compared to the existing techniques.

Visually impaired students can do mathematics despite the challenges they face due to their types of visual impairment and visual representations in math texts. Lack of trained teachers in teaching the math subject is a problem in the teaching-learning process of visually impaired students. They rely on tactile and auditory methods. They require specialized tools unique to their visual impairment, which include Braille text books, calculation devices, i.e., the abacus and Taylor Frame, and Braille rulers. Visually impaired students can gain confidence in their ability to learn math with acquisition of skills in traditional math tools, such as the abacus and Taylor Frame, and support from teachers. The main purpose of this research was to find out the level of acquisition of skills in operating mathematical tools, such as the abacus and Taylor Frame, by visually impaired students. A sample of 80 students was selected using a stratified random sampling technique. Performance tests, which include questions related to arithmetic calculations using the abacus and Taylor Frame, were administered. Results indicate that visually impaired students show poor performance in the usage of the abacus and Taylor Frame, and hence their performance in the math subject is lower when compared to arts subjects. The study identified that inadequate skilled manpower in operating these devices is a major problem, and hence, they were not able to instruct visually impaired students in the application of math tools. The study recommends that the teacher training programme incorporate components of math tools in their curriculum and conduct a capacity-building programme for in-service teachers.

The rising demand for high-performance and low-power consumption in modern computing devices is making the method of Arithmetic Logic Units (ALUs) a critical area of focus. This paper introduces a novel reversible multiplier architecture integrated with a Sklansky adder, specifically designed to address the challenges of modern ALUs, such as power reduction, low propagation delay, and efficient resource utilization. By leveraging the parallel prefix efficiency of the Sklansky adder and the inherent power-saving capabilities of reversible logic, the proposed architecture achieves superior performance metrics. Synthesized and evaluated on the ARTIX-7 FPGA (XC7a35tcpg236-1) using VHDL in Xilinx Vivado, the design demonstrates a propagation delay of 6.458 ns, a power consumption of 26.442 µW, and a power-delay product (PDP) of 170.762 fJ. These results significantly outperform existing designs, highlighting the architecture’s scalability and suitability for compact, low-power System-on-Chip (SoC) applications. This work sets a new benchmark in reversible logic-based ALU design, paving the way for advanced, energy-efficient computing platforms.

Currently, quantum-dot cellular automata (QCA) are considered a promising alternative to CMOS technology. The purpose of this paper is to demonstrate the functionality and capabilities of an exclusive 2:1 multiplexer architecture, which is used to generate the sum bit in a full adder. This structure also offers an ineffective state in addition to the traditional binary values “1” and “0”. Since the gate inputs cancel each other in this state, the output cell cannot influence its fan-out. Using this multiplexer, coplanar arithmetic circuits, including full adder (FA) and arithmetic and logic unit (ALU), are designed. By introducing a controllable path structure, based on High-Z concept, we achieve significant improvements in terms of area, delay, power consumption and overall performance, as measured by the Figure of Merit (FOM). The FA based on the High-Z cocept outperforms state-of-the-art designs, achieving a remarkable 42.86% improvement. For ALUs, experimental results show 26–39% higher FOM than state-of-the-art ALUs, with peak FOM of 0.881 for the four-operation design. These advancements, particularly in handling complex operations, make our proposed structures promising candidates for future high-performance, low-power digital circuits.

Design and implementation of FinFET and GnrFET based nano arithmetic logic unit

The CMOS increases the power dissipation in the VLSI architectures due to the technology value going to deep submicron. Hence, power dissipation optimization in CMOS circuits is a trending research area. Novel techniques are introduced in the existing CMOS circuits to reduce power utilization. Adiabatic, subthreshold adiabatic, and mixed logics are some of the novel examples of reducing power. In this paper, the Sub-threshold Adiabatic Logic (SAL), along with other logic, is used to implement the high-speed and low-power Arithmetic-Logic Unit (ALU) for high-speed processor applications. All the arithmetic, control, and logic blocks are implemented by SAL and integrated for the architecture of a 4-bit ALU using Cadence Virtuoso tools with the 45 nm CMOS technology. The design metrics, such as area, delay, and power values, are compared with the conventional CMOS-based ALU architecture and existing ALU designs proposed by other researchers. The power of the proposed SAL-ALU and mixed design-based ALU is decreased by 25% and 34% to the conventional CMOS-ALU. The power of the mixed design-based ALU is decreased by 11% compared to the SAL-ALU architecture. The transistor count of the proposed ALU is reduced by 64% by SAL-ALU and 77% by mixed design-based ALU, respectively. The mixed design-based ALU needed 38% transistors than the SAL-ALU architecture. The delay of the proposed SAL-ALU and mixed design-ALU is reduced by almost 65% compared to the conventional CMOS-ALU.

Although they differentiate between integer and floating-point datum, modern Instruction Set Architectures and their implementations do not differentiate integer datum used to address memory from integer datum used in purely arithmetic and logical computations. This is a perfectly reasonable choice as addresses are, in fact, integral quantities. However, in many cases, there is already a fundamental difference between addresses and integer data: Their width. As computer systems moved from 16 to 32, then to 64-bit pointers, with a potential future where 128-bit might be used for specific systems, the data width required to compute a given output with a given algorithm has remained the same, e.g., an ASCII character is still represented on a byte. This work aims to leverage this dichotomy to revisit hardware clustering, a well known microarchitectural technique used to mitigate the cost of scaling processor backend structures by dividing the backend into several mostly independent execution clusters. We show that by treating instructions as manipulating addresses or data and steering them to a ”data” or an ”address” cluster accordingly, reasonable cluster load balancing can be achieved without the need for complex steering policies that can lead to performance on par with the baseline with limited hardware overhead. Moreover, we highlight two possible optimizations stemming from this distribution. First, the registers of the ”address” cluster can easily be compressed thanks to address spatial and temporal locality. Second, if a processor requires a large address space but only processes narrow data (e.g., 32-bit data with 64-bit pointers or 64-bit data with 128-bit pointers), the ”data” cluster datapath can be kept narrower than the ”address” cluster datapath.

We consider fundamental to encourage and valorize themes belonging to the conjunction of Elementary Theory of Numbers and Algebra in the basic education, areas that present interesting and simple understanding contexts which allow developing problem solving strategies. This paper aimed to present the results of the application and analysis of a problem thematized in the linear Diophantine equations to beginner students from a Brazilian Licentiate degree in Science course. The methodology employed was based on the four phases of Didactic Engineering - preliminary analyzes, conception and priori analysis, experimentation and posteriori analysis - described in Artigue (1996; 2014; 2020). From the results, it was observed that all the students mobilized the trial-and-error as an initial tool to seek the entire solutions, by using arithmetic calculations. There were no manifestations of using algebraic writing as a basic support for solving the proposed problem, which represented an indication of the lack to understand the role of algebraic writing as a tool and potentiating strategy of mathematical problem solving.

Abstract To solve complex problems of the theory of elasticity of plates and shallow shells subject to local dynamic loading, two versions of the semi‐analytical finite element method are proposed. In the first variant, a model for calculating plates and shallow shells when taking into account shear and compression is used to construct dynamic equilibrium equations. Its distinctive feature is the assignment of the sought functions on the outer surfaces of the layers, which allows dividing the layers into sublayers with a corresponding increase in the accuracy of the calculation results. All known models for the calculation of plates and shallow shells taking into account shear and compression have one reduction surface. For such models, it is difficult to divide layers into sublayers. The original distinctive feature of the second variant is finding the distribution of the sought functions by the thickness of the structure by means of an exact solution of the corresponding system of differential equations. The authors did not find similar variants of the semi‐analytical finite element method in publications. Both x‐axis options use finite element approximation. Trigonometric functions are used to approximate the y‐axis. The necessity of developing two approaches is attributed to the fact that they have inaccuracies of approximation and arithmetic calculations, which are especially seen in the calculation of forced vibrations at the frequencies close to resonance. The coincidence of the calculation results obtained by the two proposed variants of the semi‐analytical finite element method can serve as a confirmation of their reliability. An analysis of the behavior of plates and flat shells under forced vibrations at frequencies close to resonance was carried out. The conducted studies have shown that for the class of problems under consideration, using the option with a polynomial approximation of the required functions over the thickness of the structure when considering a layer within one sublayer can lead to a large error.

The use of augmented reality (AR) tools and innovative learning environments in education have increased over the last few years due to the rapid advancement of technology. In this study, an AR mathematics learning intervention has been proposed which consisted of the creation of 3D multibase blocks to perform AR arithmetic calculations conducted through active methodologies in the future classroom lab (FCL). The aim of this study was to analyze pre-service teachers’ (PSTs) affective domain (emotion, self-efficacy, and attitude), engagement, motivation, and confidence. The sample consisted of 97 PSTs enrolled on the second year of the Primary Education degree, who were attending the “Mathematics and its Didactics” subject. The findings revealed a significant increase in PSTs’ satisfaction, fun, confidence, and pride, and a decrease in uncertainty, nervousness, and concern. Regarding PSTs’ self-efficacy, a significant improvement was observed in knowing the necessary steps to teach mathematical concepts and work in the FCL. No significant differences were found in attitude, engagement, and motivation; however, the PSTs showed a high disposition in all of them before starting the intervention. Additionally, the PSTs reported to be more confident, and it enhanced their knowledge in the use of 3D design and AR applications to create multibase blocks to support the teaching–learning content of arithmetic operations.

Abstract The intrinsic high non‐linearity of Schottky diodes with the latest improvements in performance, material, and design novelties have made them invaluable in the emerging devices ecosystem. However, the reported studies on diodes based on 2D and metal‐oxide semiconductors for digital circuits are limited to basic logic gates. The Schottky diodes‐based integrated circuit feasibility and scalability discussions are lacking. In this work, the large throughput and cost‐effective adhesion lithography in tandem with the solution‐based method is used to fabricate integrated functional circuits for Arithmetic Logic Unit (ALU). The self‐aligned nanogap separation between interdigitated coplanar aluminum (Al) and gold (Au) electrodes is uniform throughout the fabricated diode width, resulting in a high rectification ratio of 5 × 106. The fundamental logic AND, OR, and XOR gates based on nanogap Schottky diodes are fabricated, from which arbitrary logic and arithmetic functional circuits can be constructed. To demonstrate the large‐area integration, a 3‐bit Binary Shifter circuit is implemented. The measurement‐based Keysight ADS diode model is used to design a complete 4‐bit ALU circuit. The excellent circuit‐level performance, large‐area scalability, design flexibility, and cost‐efficiency of logic circuits based on nanogap Schottky diodes make them promising candidates for future Internet of Things applications.

The article presents a study of hybrid adder architectures, focused on increasing their efficiency by minimizing signal propagation delay in digital systems. The main attention is paid to the comparative analysis of integrating different principles of adder construction, particularly serial and parallel circuits, with the aim of achieving an optimal balance between speed and hardware costs. For a detailed study of the time characteristics of hybrid solutions, modeling in the specialized software environment OrCAD/PSpice was applied. Critical parameters that significantly affect calculation speed and signal delay under different input pulse configurations were experimentally determined. Approaches to optimizing these parameters to ensure stable and fast operation are proposed. The research results demonstrate how the use of hybrid architectures can significantly improve the overall performance of arithmetic logic units. This creates prerequisites for the development of more high-speed and energy-efficient microchips, which is critically important for modern computing systems. A comparative characteristic of the studied adders is provided, confirming the effectiveness of the chosen approach. The obtained data emphasize the significant potential of hybrid adders as a key element in the design of new generation high-performance digital systems. Figs.: 9. Tabl.: 1. Refs.: 8 titles.

Modern telecommunication technologies, such as the 5G and upcoming 6G networks, rely on devices operating in the radio frequency (RF) spectrum of 0.3–90 GHz and 7–300 GHz, respectively. To meet these demanding frequency requirements, new manufacturing methods and device architectures are gaining increasing attention. However, achieving scalable manufacturing alongside ultra-fast device operation presents formidable techno-economic challenges. Here, we explored a modified version of adhesion lithography (a-Lith) to create coplanar nanogap zinc oxide (ZnO) Schottky diodes for application in diode-logic arithmetic circuits. The planar ZnO diodes offer highly scalable manufacturing and combine high current rectification (> 106) with low reverse currents (≈80 pA) and a remarkable cut-off frequency of over 25 GHz. Engineering the topologies of the planar ZnO diodes enables their facile monolithic integration into multi-bit AND and OR gates over 4-inch glass wafers. By integrating several such logic gates, we demonstrated fully functional monolithic 2-bit Half-Adder circuits, the primary component of an arithmetic logic unit. The work offers an alternative method for developing fast large-area electronics that could lead to a new family of logic circuitry.

<p>The growing demand for energy-efficient and real-time biomedical signal processing in wearable devices has necessitated the development of application-specific and reconfigurable embedded hardware architectures. This paper presents the register transfer level (RTL) design and simulation of a custom reduced instruction set computer-V (RISC-V) based hardware architecture tailored for real-time electrocardiogram (ECG) feature extraction, focusing on R-peak detection and heart rate (HR) calculation. The proposed system combines ECG-specific functional blocks including a specialized ECG arithmetic logic unit and a finite state machine-based ECG control unit with a compact 16-bit RISC-V control core. Hardware optimized algorithms are used to carry out pre-processing activities such high-pass and low-pass filtering as well as feature extraction processes including moving average filtering, derivative calculation, and threshold based peak identification. Designed to reduce memory footprint and control complexity, a custom instruction set architecture supports modular reconfigurability. Functional validation is carried out by Xilinx Vivado simulating RTL components described in very high speed integrated circuit (VHSIC) hardware description language (VHDL). The present work shows successful simulation of important architectural components, complete system-level integration and custom ECG data validation. This work provides the basis for an application-specific, reconfigurable, power efficient hardware solution for embedded health-monitoring devices.</p>

The way in which EEG signals reflect mental tasks that vary in duration and intensity is a key topic in the investigation of neural processes concerning neuroscience in general and BCI technologies in particular. More recent research has reinforced historical studies that highlighted theta band activity in relation to cognitive performance. In our study, we propose a comparative analysis of experiments with cognitive load imposed by arithmetic calculations performed mentally. The analysis of EEG signals captured with 64 electrodes is performed on low theta components extracted by narrowband filtering. As main signal discriminators, we introduced an original measure inspired by the integral of the curve of a function—specifically the signal function over the period corresponding to the filter band. Another measure of the signal considered as a discriminator is energy. In this research, it was used just for model comparison. A cognitive load detection algorithm based on these signal metrics was developed and tested on original experimental data. The results present EEG activity during mental tasks and show the behavioral pattern across 64 channels. The most precise and specific EEG channels for discriminating cognitive tasks induced by arithmetic tests are also identified.

Abstract The responses of Mimosa pudica and Venus Flytraps to abiotic stimulation have been studied and applied in this research to biosensor devices and related logic systems. Via unique behavior and electrophysiological signals from Mimosa pudica and Venus Flytraps, a complete ripple‐carry ternary arithmetic logic system is achieved in this research. Mimosa pudicas serve as the touch keyboard for the signal input and the monitor for the output of the plant‐based biocomputer, and Venus flytraps based AND and OR logic gates implement the core ALU (Arithmetic Logic Unit) of the plant‐based biocomputer. The energy consumed by a single Venus flytrap requires only 38.8 µW of power in the process of logic gate operation, and 74‐series logic gate chips (74F08N chip (4 AND gate integrated circuit)) used in consumer electronics require 7.86 mW to drive. To compare the energy consumed by the operation of the Venus Flytrap, the Venus flytraps based AND and OR logic gates implement the core ALU consumes 6.24 µJ for operation. Even though the energy consumption per calculation differs by a factor of ≈226 from 74‐series logic gate chips, it is emphasized that the Venus Flytrap biocomputer has the potential for ultra‐low frequency sensing and green computing.

Abstract— In this digital world, technology depends on the operations of A.L.U to decide the system performance. The need for an Arithmetic Logic Unit (ALU) is as important as the computer, simply because ALU forms the fundamental part of any Central Processing Unit (CPU). And so the encryption of an ALU is highly mandatory for the safety of the device as there are hardly any device without an ALU. This paper deals with the design of an single-bit ALU using a hardware description language, HDL that is structurally modelled. The results are verified and synthesized through Xilinx. Keywords- ALU, FPGA SPARTAN6, REVERSIBLE LOGIC, QUANTUM COST, FEYNMAN GATE.

Tooth preparation, as an irreversible surgical procedure, critically determines the long-term efficacy of dental restorations. Traditional preparation techniques, heavily reliant on operators' unaided visual estimation and empirical skills, suffer from inherent subjectivity and the inability to quantitatively verify preparation dimensions. These limitations render them inadequate to meet the sub-100-micron linear precision required for contemporary minimally invasive and esthetic restorations, which often feature maximum preparation depths below 1 mm. Emerging digital solutions, such as depth-specific preparation guides based on target restorative space analysis, have achieved reported preparation accuracies of approximately 50 μm by integrating arithmetic calculations and real-time verification of preparation depth as the pivotal geometric parameter. Further advancements, including real-time intraoral scanning-based preparation monitoring systems, are now being applied to ultra-thin and extreme-thin veneer restorations, offering a more precise and efficient paradigm for depth control. To comprehensively evaluate the efficacy of current digital tooth preparation protocols, this article systematically compares digital guidance technologies with conventional methods across three dimensions: time efficiency, economic cost, and clinical efficacy. It critically examines the synergistic use of visual magnification tools, emphasizing the necessity of concurrently addressing" visual clarity" and "enhancement of manual skill stability and precision". Notably, the target restorative space (TRS)-guided digital preparation technique under dental microscopy employs preparation depth as the master geometric parameter throughout multi-stage workflows. By combining microscopic visualization with rigid depth-specific guides, this method enables real-time verification of preparation depth, achieving unprecedented intraoperative precision. The integration of next-generation non-contact high-precision intraoral scanning systems further elevates accuracy from the sub-100-micron level to a tens-of-microns precision scale, paving the way for ultra-precise tooth preparation. These innovations in digital guidance systems not only redefine clinical standards but also herald the evolution of "digitally guided prosthodontics"as a transformative frontier in restorative dentistry.

This article presents “An Integrated Approach: Design and Implementation of a 4-Bit Signed Binary Calculator for Arithmetic Operations using Schematic and Verilog”. Capable of performing essential arithmetic operations like addition, subtraction, multiplication, and division, this calculator has been meticulously crafted to cater specifically to the efficient computation needs of a 4-bit binary system. By integrating numerous arithmetic modules including an adder-subtractor unit, a multiplier, and a divider, this calculator achieves exceptional functionality and reliability. To maximize performance and minimize hardware complexity, the implementation of the calculator harnesses a combination of combinational and sequential logic design techniques. This strategic approach allows for rapid computation and facilitates seamless execution of arithmetic operations within the limitations of a 4-bit binary environment. I have used Xilinx Design suite 14.7 to design and simulate the Schematic and Verilog Design.