Finite Field Arithmetic Research Articles

Signature analysis for analog and mixed-signal circuit test response compaction

While the design of signature analyzers for digital circuits has been well researched in the past, signature analyzers for analog signals are relatively unknown. The primary difficulty in analyzing signatures for analog signals is that the latter are imprecise in nature. Therefore, deterministic signature analysis schemes, such as those based on finite-field arithmetic using linear feedback shift registers, are unsuitable for analog circuits. In this paper, a novel signature analysis scheme for analog and mixed signal circuits is proposed. The signatures possess the interesting property that if the input analog signal is imprecise within certain bounds (an inherent property of analog signals), then the generated signature is also imprecise within certain bounds. A failure is indicated by the generated signature being different from the expected signature by a margin greater than a predetermined threshold; the larger the effects of the failure, the larger the difference between the generated signature and the expected signature. The probabilities of aliasing and false rejection are also derived. Results for an example filter circuit are presented.

Efficient semisystolic architectures for finite-field arithmetic

Finite fields have been used for numerous applications including error-control coding and cryptography. The design of efficient multipliers, dividers, and exponentiators for finite field arithmetic is of great practical concern. In this paper, we explore and classify algorithms for finite field multiplication, squaring, and exponentiation into least significant bit first (LSB-first) scheme and most significant bit first (MSB-first) scheme, and implement these algorithms using semisystolic arrays. For finite field multiplication (for programmable as well as fixed field order) and exponentiation, we conclude that LSB-first algorithms are more efficient as their basic cells have less critical path computation time. Another advantage of LSB-first scheme is its capability of achieving substructure sharing among multiple operations, which could lead to savings in hardware when these arithmetic units are used as building blocks for a large system. For finite field squaring operation, it turns out that the MSB-first algorithm is more efficient as it leads to simpler architectures. Bit-level pipelined semisystolic architectures utilize broadcast signals. As a result, these require much less number of latches and lead to much smaller latency than the corresponding systolic array, with the same cycle time (the computation time in one basic cell). Efficient VLSI implementation of semisystolic multipliers, squarers and exponentiators are designed and compared with existing architectures. A novel architecture for computing AB/sup n/+C using power representation is also presented.

RNS-modulo reduction upon a restricted base value set and its applicability to RSA cryptography

For a modulo reduction scheme in RNS a set of restricted base values is proposed. In RNS, additions and multiplications can be computed in parallel, avoiding carry propagation delays. This advantage enables the implementation of scalable, parallel arithmetic units for computations in very large finite fields. For such a long integer arithmetic unit certain selection criteria for the base value set have been worked out, targeted to optimise the modulo reduction operation on the RNS digit level. As public key cryptography heavily depends on arithmetic in large finite fields, a parallelisable RSA variant is shown as a sample application.

VLSI architectures for computing exponentiations, multiplicative inverses, and divisions in GF(2/sup m/)

A modified parallel-in-parallel-out linear-systolic power-sum circuit designed to perform AB/sup 2/+C computations in the finite field GF(2/sup m/) is presented, where A, B, and C are arbitrary elements of GF(2/sup m/). On the basis of the linear-systolic power-sum circuits, a VLSI architecture for exponentiation in GF(2/sup m/) is developed. Furthermore, two modified architectures that can be used to compute inverses and divisions over GF(2/sup m/) are proposed. All the architectures are constructed from m-1 linear-systolic power-sum circuits. It should be noted that the presented exponentiator, inverter, and divider are the only such circuits having a throughput of 100%. The latency of the presented pipeline exponentiator, inverter, and divider is m(m-1) clock cycles. The cycle time (i.e., clock period) of the presented architectures is only two logic gate delays plus a short routing delay. For moderate values of m, say m/spl les/10, the circuit complexity of the presented circuits is realizable using presently available VLSI technology. The computation time of near two gate delays and 100% throughput enables the greatest computation speed in finite field arithmetic.

Regulus-free spreads ofPG (3,q)

An old conjecture of Bruck and Bose is that every spread of \Sigma = PG(3,q) could be obtained by starting with a regular spread and reversing reguli. Although it was quickly realized that this conjecture is false, at least for q even, there still remains a gap in the spaces for which it is known that there are spreads which are regulus-free. In several papers Denniston, Bruen, and Bruen and Hirschfeld constructed spreads which were regulus–free, but none of these dealt with the case when q is a prime congruent to one modulo three. This paper closes that gap by showing that for any odd prime power q, spreads of PG(3,q) yielding nondesarguesian flag-transitive planes are regulus–free. The arguments are interesting in that they are based on elementary linear algebra and the arithmetic of finite fields.

Unconventional cryptographic keying variable management

We present three unconventional approaches to keying variable management. The first approach is based on using a public key cryptosystem (PKC) that is breakable in short, but on average less, time than it takes to set up an ultrawide bandwidth modem that is then used to transport a keying variable for a classical cryptosystem. The second concept proposes using the characteristics of an urban UHF radio channel, determined by mutual sounding, as the cryptovariable. The third concept encourages research into ill-conditioned problems as potentially fruitful ground for PKCs not based on finite field arithmetic.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The computational efficacy of finite-field arithmetic

We investigate the computational power of finite-field arithmetic operations as compared to Boolean operations. We pursue this goal in a representation-independent fashion. We define a good representation of the finite fields to be essentially one in which the field arithmetic operations have polynomial-size Boolean circuits. We exhibit a function ƒ p on the prime fields with two properties: first, ƒ p has a polynomial-size Boolean circuit in any good representation, i.e. ƒ p is easy to compute with general operations; second, any function that has polynomial-size Boolean circuits in some good representation also has polynomial-size arithmetic circuits if and only if ƒ p has polynomial-size arithmetic circuits. Informally, ƒ p is the hardest function to compute with arithmetic that has small Boolean circuits. We reduce the function ƒ p to the pair of functions g p = ∑ k=1 p−1 x k k on the field F p , and m p on Z p 2 . Here m p is the “modulo p” function defined in the natural way. We show that ƒ p has polynomial-size arithmetic circuits if and only if g p and m p have polynomial-size arithmetic circuits, the latter being arithmetic circuits over the ring Z p2 . Finally, we establish a connection of ƒ p and m p with the Bernoulli polynomials and determine the coefficients of the unique degree p − 1 polynomial over F p that computes ƒ p .

Algorithm engineering for public key algorithms

Methods of implementing public key algorithms based on modular integer arithmetic (RSA) and finite-field arithmetic (Diffie-Hellman, El Gamal) are examined. Architectures for VLSI implementations are emphasized. >

Finite field manipulations in Macsyma

We present the implementation of an extensive system of routines, in Macsyma, which allows finite field arithmetic and manipulation of symbolic objects in finite fields,

A hardware architecture using finite-field arithmetic for computing maximum-likelihood estimates in emission tomography

A special-purpose hardware architecture is proposed to implement the expectation-maximization algorithm to compute, in clinically useful times, the maximum-likelihood estimate of a radionuclide distribution for a positron-emission tomogram from time-of-flight measurements. Two-dimensional convolutions required for forming the estimate are converted into a series of one-dimensional convolutions that can be evaluated in parallel. Each one-dimensional convolution is evaluated using a number-theoretic transform. All numerical calculations are performed using finite-field arithmetic. To avoid the use of large finite fields and to increase parallelism, each convolution is performed by a series of convolutions with small digits in a Galois field. The hardware architecture allows a two-dimensional convolution of dimension NxN to be formed with O(N) operations, permitting one iteration of the expectation-maximization algorithm to be formed in approximately 100 ms when N=128 and the number of view angles is 32.

The Depth Efficacy of Unbounded: Characteristic Finite Field Arithmetic

We introduce an arithmetic model of parallel computation. The basic operations are ½ and Š gates over finite fields. Functions computed are unary and increasing input size is modelled by shifting the arithmetic base to a larger field. When only finite fields of bounded characteristic are used, then the above model is fully general for parallel computations in that size and depth of optimal arithmetic solutions are polynomially related to size and depth of general (boolean) solutions. In the case of finite fields of unbounded characteristic, we prove that the existence of a fast parallel (boolean) solution to the problem of powering an integer modulo a prime (and powering a polynomial modulo an irreducible polynomial) in combination with the existence of a fast parallel (arithmetic) solution for the problem of computing a single canonical function, f&lt;em&gt;(x)&lt;/em&gt;, in the prime fields, guarantees the full generality of the finite field model of computation. We prove that the function f&lt;em&gt;(x)&lt;/em&gt;, has a fast parallel arithmetic solution for any ''shallow'' class of primes, i.e. primes &lt;em&gt;p&lt;/em&gt; such that any prime power divisor &lt;em&gt;q&lt;/em&gt; of &lt;em&gt;p&lt;/em&gt; -1 is bounded in value by a polynomial in log &lt;em&gt;p&lt;/em&gt;.

A knapsack-type public key cryptosystem based on arithmetic in finite fields

A knapsack-type public key cryptosystem is introduced that is the system is based on a novel application of arithmetic in finite fields. By appropriately choosing the parameters, one can control the density of the resulting knapsack, which is the ratio between the number of elements in the knapsack and their size in bits. In particular, the density can be made high enough to foil so-called low-density attacks against the system. At the moment, no attacks capable of breaking the system in a reasonable amount of time are known.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A VLSI architecture for performing finite field arithmetic with reduced table lookup

A new table lookup method for finding the log and antilog of finite field elements has been developed by Glover. The method makes use of several smaller tables, and is based on the Chinese remainder theorem. It often results in a significant reduction in the memory requirements of the problem. A VLSI architecture is developed here for a special case of this new algorithm to perform finite field arithmetic including multiplication, division, and the finding of an inverse element in the finite field.

Finite Field Fault-Tolerant Digital Filtering Architectures

Digital filtering architectures that simultaneously offer advantages for VLSI fabrication and contain distributed error control are presented. Such structures require parallelism as well as inherent error- control capabilities because VLSI implementations are susceptible to temporary and intermittent hardware errors. The filtering convolution operation is similar to the formation of cyclicerror-correcting codes so that fault-tolerant systems employing finite field arithmetic may be designed containing such codes imbedded directly in the architecture. The interconnection of such systems produces a fault-tolerant system. In addition, the subsystems possess a common design structure which is easily customized to the particular field required, an attractive feature for yield enhancement. Straightforward realizations depending on parallel algebraic decompositions are studied, introducing the locations for fault tolerance and the role of cyclic codes.

The Computational Efficacy of Finite Field Arithmetic

&lt;p&gt;We show that there exists an interesting non-uniform model of computational complexity within characteristic-two finite fields. This model regards all problems as families of functions whose domain and co-domain are characteristic-two fields. The model is both a &lt;em&gt;structured&lt;/em&gt; and a &lt;em&gt;fully&lt;/em&gt; &lt;em&gt;general&lt;/em&gt; model of computation.&lt;/p&gt;&lt;p&gt;We ask if the same is true when the characteristics of the fields are unbounded. We show that this is equivalent to asking whether arithmetic complexity over the prime fields is a fully general measure of complexity.&lt;/p&gt;&lt;p&gt;We show that this reduces to whether or not a single canonical function is ''easy'' to compute using only modulo &lt;em&gt;p&lt;/em&gt; arithmetic.&lt;/p&gt;&lt;p&gt;We show that the arithmetic complexity of the above function is divided between two other canonical functions, the first to be computed modulo &lt;em&gt;p&lt;/em&gt; and the second with modulo p^2 arithmetic.&lt;/p&gt;&lt;p&gt;We thus have tied the efficacy of finite field arithmetic to specific questions about the arithmetic complexities of some fundamental functions.&lt;/p&gt;

A Fast VLSI Multiplier for GF(2&amp;lt;sup&amp;gt;m&amp;lt;/sup&amp;gt;)

Multiplication in the finite field GF(2^{m} ) has particular computational advantages in data encryption systems. This paper presents a new algorithm for performing fast multiplication in GF(2^{m} ), which is O(m) in computation time and implementation area. The bit-slice architecture of a serial-in-serial-out modulo multiplier is described and the circuit details given. The design is highly regular, modular, and well-suited for VLSI implementation. The resulting multiplier will have application in algorithms based on arithmetic in large finite fields of characteristic 2, and which require high throughput.

Fault-tolerant digital filtering architectures using fast finite field transforms

Digital filtering architectures for highly parallel realizations containing distributed error control are presented. They involve the interconnection of fault-tolerant sections using finite field arithmetic into which powerful cyclic error-correcting codes can be imbedded naturally. Realizations employing finite field transform domains and new techniques for protecting the transform coefficients are developed. These coefficients' special property, called the Chord Property, permits error detection and correction in the transform domain, and the proper selection of certain code parameters can expand this capability. Fast Transform algorithms with distributed error-control are possible because the interstage variables also obey limited chord properties. The interplay between these properties and certain code parameters are used to eliminate undesirable error propogation and provide reliable digital filter realizations.

Processor Architectures for Two-Dimensional Convolvers Using a Single Multiplexed Computational Element with Finite Field Arithmetic

This paper describes the theory, simulation, and construction of a two-dimensional number theoretic transform (NTT) convolver. The convolver performs indirect convolution by using the cyclic convolution property of a class of generalized discrete Fourier transforms (DFT's) defined over rings isomorphic to direct sums of Galois fields. The paper first presents the theoretical development of the computational element required for computing the generalized discrete Fourier transform (GDFIT) and its inverse. The theory extends the use of base fields to second degree extension fields and provides efficient choices for transform parameters to minimize hardware. The paper next presents results of recent work in multidimensional transform memory structures, and extends this work to the complete convolution process. The two theories are then "married" to produce efficient, very high speed convolution architectures. Simulation results are presented for a second degree extension field image convolver and constructional details are presented for a fast image convolver using 2 base fields and designed to operate as a peripheral to a fast 32 bit minicomputer.

Arithmetic of finite fields

Arithmetic of finite fields

Arithmetic in a finite field

An algorithm for realizing finite field arithmetic is presented. The relationship between linear recursions and polynomial arithmetic (modulo a fixed polynomial) over Zp is exploited to reduce the storage and computation requirements of the algorithm. A primitive normal polynomial is used to simplify the calculation of multiplicative inverses.