Arithmetic Circuits Research Articles (Page 1)

Efficient quantum realizations of arithmetic operations, such as multiplication/division, addition/subtraction, square root, and arcsine - are of utmost importance for several quantum algorithms of practical importance. In literature, such implementations are reported with the objective of minimizing qubit count, Toffoli/T/CNOT gate count, logical depth, quantum volume, and other commonly used metrics. By extending the realm of quantum states to higher dimensions, it has been demonstrated recently that intermediate qutrits can be leveraged to reduce ancilla qubits, thereby reducing qubit count. In this article, we have incorporated this approach to prepare efficient implementation for several quantum arithmetic operations, obtaining significantly lowered qubit count. As an exemplary application, we study derivative pricing, in which, quantum arithmetic circuits are necessary for path loading using the re-parameterization method, as well as the payoff calculation. The intermediate qutrit approach requires to access higher energy levels, making the design prone to errors. Nevertheless, we show that the overall decrease in the error probability of error is significant owing to the fact that we achieve circuit robustness compared to the qubit-only approach in this NISQ era. We also study how we may achieve possible effectiveness with fewer gate counts of the proposed approach in the fault-tolerant setting.

Abstract Approximate computing (AC)-based arithmetic circuits have not been considered in sensitive applications, and the exact domain has been preferred. In this paper, as an approximate computing concept, new domains called moderate and less are proposed and assigned to very low-sensitive domain (VLSD) and LSD applications, respectively. So, an approximate low-power and full-swing full adder (FA) is presented with four transistors, which uses gate diffusion input (GDI) and dynamic threshold (DT) techniques. The FA which has three errors is used in a 12-transistor approximate 4:2 compressor based on the stacking circuit concept.The presented low-power and small-area approximate compressor is embedded in an approximate sum of absolute difference (SAD) and some of its errors are compensated by an error correction module (ECM). In comparison with the exact type, the represented approximate 4:2 compressor reduces the power, power-delay-product (PDP), and power-delay-area-product (PDAP) by 95%, 95%, and 99%, respectively, while the utilization of the proposed compressor in SAD decreases 31% average power and reduces 32% of average PDP. The acceptable accuracy and performance of the SAD confirm the application of this study for the new generation of AC-based circuits in bioimage processing.

The present computing landscape operates on the foundations of the von Neumann architecture, which, while influential, is accompanied by limitations in areas, such as the memory capacity, power consumption, and instruction parallelism. This configuration has direct implications for the effectiveness of modern computer systems. One of the new computation architectures to break these three boundaries is the Computation In Memory (CIM) architecture. This paper presents a CIM technique and arithmetic circuit co-design using an 8T SRAM cell, demonstrating arithmetic and Boolean logic operations in 45 nm CMOS technology. The use of Transmission Gate (TG)-based SRAM eliminates the need for peripheral circuitry during the read operations, reducing the delay and power consumption. The SRAM memory array must be created utilizing the 8T SRAM cell along with the proposed sensing scheme, a mapped 4-bit array multiplier net-list into a SRAM memory array, and was tested for functionality before the arithmetic circuit can be implemented. The read and write operations using the proposed TG-based architecture in the 2-bit array multiplier, reduces the processing delay by 80.63% and the power consumption by 93.53% when compared to the existing pass transistor logic-based design. The study presents a full-stack demonstration—from 8T SRAM cell design, sensing scheme, and memory array construction, to arithmetic circuit mapping and functional testing of the multiplier—showing a holistic view of the practical CIM implementation.

Currently, quantum-dot cellular automata (QCA) are considered a promising alternative to CMOS technology. The purpose of this paper is to demonstrate the functionality and capabilities of an exclusive 2:1 multiplexer architecture, which is used to generate the sum bit in a full adder. This structure also offers an ineffective state in addition to the traditional binary values “1” and “0”. Since the gate inputs cancel each other in this state, the output cell cannot influence its fan-out. Using this multiplexer, coplanar arithmetic circuits, including full adder (FA) and arithmetic and logic unit (ALU), are designed. By introducing a controllable path structure, based on High-Z concept, we achieve significant improvements in terms of area, delay, power consumption and overall performance, as measured by the Figure of Merit (FOM). The FA based on the High-Z cocept outperforms state-of-the-art designs, achieving a remarkable 42.86% improvement. For ALUs, experimental results show 26–39% higher FOM than state-of-the-art ALUs, with peak FOM of 0.881 for the four-operation design. These advancements, particularly in handling complex operations, make our proposed structures promising candidates for future high-performance, low-power digital circuits.

The vast interconnection between digital logic blocks is the main challenge faced in chip designing, which leads to increased area overheads and average power consumption. One possible solution to overcome this challenge is to make use of multi-valued logic. However, for implementing multi-valued logic, new design techniques that deliver low-power and high-speed performance need to be explored. In this paper, carbon nanotube field effect transistor (CNTFET) based standard quaternary logic gates have been designed using pass transistor logic and voltage divider circuit techniques. The simulation results for the standard quaternary logic gates have been obtained using HSPICE with standard 32 nm CNTFET Stanford model. The results for the standard quaternary inverter circuit at a supply voltage of 0.9 V show average power consumption, delay, power delay product (PDP), energy delay product (EDP), and area of 31.446 nW, 7.948 ps, 0.249 aJ, 1.986 × 10-30 Js, and 13,287 λ2, respectively. Similarly, the performance metrics, i.e., PDP and EDP are 0.597 aJ and 6.535 × 10-30 Js for standard quaternary NAND circuit and 0.099 aJ and 1.046 × 10-30 Js for standard quaternary NOR circuit, respectively. The proposed designs are superior in power consumption, PDP, and EDP in contrast to existing designs. The area occupancy and robustness of proposed standard quaternary inverter is also investigated by implementing layouts and performing Monte Carlo simulations. Further, the functionality of proposed quaternary logic gates is verified by using quaternary multiplier (QMUL) and quaternary half adder (QHA) as application examples. The proposed QMUL and QHA show PDP of 97.60 aJ and 95.937 aJ, respectively, which are quite encouraging when compared with literature. The new methodology for designing quaternary circuits reported in this work is expected to improve the performance of computing devices.

Introduction: Parallel prefix adders are widely used in high-speed arithmetic circuits due to their ability to perform additions in logarithmic time. However, the high area and delay of exact parallel prefix adders prompted the development of approximate parallel prefix adders. These adders are a promising solution for high-speed arithmetic circuits because they sacrifice accuracy for reduced area and delay. Methods: This paper presents a performance analysis of five approximate parallel prefix adders realized with field programmable gate array technology. The five approximate parallel prefix adders are the Kogge-Stone adder, the Sklansky adder, the Brent-Kung adder, the Han-Carlson adder, and the Ladner-Fisher. Each adder is implemented in a Xilinx Artix-7 FPGA. The area and delay of five approximate parallel prefix adders are evaluated. The Kogge-Stone approximate parallel prefix adder, out of five approximate parallel prefix adders, consumes the least delay, irrespective of the number of bits. Results: The Sklansky approximate parallel prefix adder out of five approximate parallel prefix adders consumes the least area irrespective of the number of bits in addition. Overall, our research sheds light on the trade-offs between area, power delay, and power delay products of five approximate parallel prefix adders implemented with FPGA technology. Conclusion: This analysis can help choose the best approximate parallel prefix adder for specific high-speed arithmetic applications. In the case of 16- and 32-bit five approximate parallel prefix adders, Ladner-fisher shows the best power delay product, whereas 64- and 128-bit five approximate parallel prefix adders, Sklansky adder shows the best power delay product.

We present a simple algorithm based on the inclusion-exclusion principle for computing the sum of the coefficients of all multilinear monomials in a polynomial computed by an arithmetic circuit over any field \(\mathbb {F} \) . This problem is formally denoted as ( k , n )-MLC and is defined as follows: • Given an arithmetic circuit computing a homogeneous polynomial \(f \in \mathbb {F}[x_1,\ldots,x_n] \) of degree k , where \(\mathbb {F} \) is any field, compute the sum of the coefficients of all multilinear monomials in f . We provide a deterministic algorithm for the ( k , n )-MLC problem with a running time of O ( n k /2 · 2 O ( k ) · s O (1) ), where s is the size of the circuit. Our algorithm is also polynomial space-bounded. The ( k , n )-MLC problem was first studied by Koutis and Williams [15, 17, 22] and later studied by Arvind et al., [3], where they obtain a deterministic algorithm with a running time of \(O^*\left({n\atopwithdelims (){\downarrow k/2}}\cdot s^{O(\log k)}\right) \) using Hadamard product of polynomials. Pratt [18] proposed a deterministic algorithm that runs in O * ( n k /2 ) time, but this approach relies on a non-trivial Waring decomposition of symmetric polynomials over the rationals, which does not extend to small finite fields. Our method is notable for its simplicity and general applicability to all fields. In contrast to existing works, we introduce the complement of the ( k , n )-MLC problem, which we call the ( k , n )-NMLC problem. This approach looks at finding the sum of the coefficients of all non-multilinear monomials, which gives us a new way to think about the ( k , n )-MLC problem. This new method results in a simple algorithm and helps explain where the leading exponent k /2 comes from. We develop a deterministic algorithm for the ( k , n )-NMLC problem that runs in O ( n k /2 · 2 O ( k ) · s ) time and uses polynomial space. The algorithm for the ( k , n )-MLC problem is straightforward: it subtracts the sum of the coefficients of all non-multilinear monomials (the result from the ( k , n )-NMLC problem) from the total sum of all monomial coefficients in the polynomial, which includes both multilinear and non-multilinear monomials. We apply these results to obtain a deterministic algorithm for the exact counting version of the r -simple k -path problem, as introduced in [1, 13], and also to a generalization of the ( k , n )-MLC problem, which we call the ( r , k , n )-MLC problem. This involves computing the sum of the coefficients of all monomials in the polynomial produced by the given arithmetic circuit, where the degree of each variable is at most r .

This paper proposes a new enhanced Single Digit BCD Adder (SDBA) to perform decimal addition optimally. Quantum‐dot Cellular Automata (QCA) will construct nanostructured arithmetic circuits for future computing. One of the vital structures in arithmetic structures is the Binary Coded Decimal (BCD)/Decimal Adder. The existing Decimal Adders require many cells and consume more delay, which makes the circuit inefficient in doing decimal addition faster. The binary adder structures are more significant in deciding the performance of conventional BCD adders. Multiplexers are used in the proposed BCD adder to enhance the speed with less complexity. The main contribution of the proposed SDBA design is to replace the final part of the conventional structure Carry Flow Adder (CFA) based BCD adder with a multiplexer, which improves the speed and increases the regularity of the structure. The multiplexers perform the binary to decimal sum conversion in parallel rather than the carry rippling in the lower part of the standard circuit. The SDBA uses the optimized CFA Type‐II binary adder and new logic with a 2:1 multiplexer. Furthermore, the proposed BCD adder is an optimized design in terms of delay, which requires 2.75 clock cycles only compared to the recent designs. © 2025 The Author(s). IEEJ Transactions on Electrical and Electronic Engineering published by Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.

Abstract The intrinsic high non‐linearity of Schottky diodes with the latest improvements in performance, material, and design novelties have made them invaluable in the emerging devices ecosystem. However, the reported studies on diodes based on 2D and metal‐oxide semiconductors for digital circuits are limited to basic logic gates. The Schottky diodes‐based integrated circuit feasibility and scalability discussions are lacking. In this work, the large throughput and cost‐effective adhesion lithography in tandem with the solution‐based method is used to fabricate integrated functional circuits for Arithmetic Logic Unit (ALU). The self‐aligned nanogap separation between interdigitated coplanar aluminum (Al) and gold (Au) electrodes is uniform throughout the fabricated diode width, resulting in a high rectification ratio of 5 × 106. The fundamental logic AND, OR, and XOR gates based on nanogap Schottky diodes are fabricated, from which arbitrary logic and arithmetic functional circuits can be constructed. To demonstrate the large‐area integration, a 3‐bit Binary Shifter circuit is implemented. The measurement‐based Keysight ADS diode model is used to design a complete 4‐bit ALU circuit. The excellent circuit‐level performance, large‐area scalability, design flexibility, and cost‐efficiency of logic circuits based on nanogap Schottky diodes make them promising candidates for future Internet of Things applications.

In modern VLSI design, the full adder remains a fundamental component, directly influencing the overall efficiency of arithmetic circuits. This paper presents novel high-speed gate-level synchronous full adder designs that significantly optimize critical performance parameters including area, delay, and power consumption. Existing full adder implementations using AND-OR logic, half adders, and 2:1 multiplexers exhibit higher transistor counts (up to 74), increased delay (up to 20.03 ns), and elevated power dissipation (up to 137.5 µW). In contrast, the proposed designs—XAC, XNM, and XNAIMC—demonstrate remarkable improvements. The XNM design achieves the lowest delay of 0.032 ns and minimal power consumption of 0.335 µW with a reduced transistor count of 37. The XAC variant further reduces area to just 34 transistors, while maintaining efficient performance. These results confirm the effectiveness of the proposed architectures in advancing low-power, high-speed digital circuit design, making them highly suitable for next-generation VLSI systems

Approximate circuits have become ubiquitous in error-resilient applications. These circuits provide large reductions in area, power, and delay at the cost of erroneous computations. The error-resilient applications produce acceptable output quality, even after the introduction of erroneous computations. However, we observed that the error resilience of an application varies widely with respect to the applied inputs. Since prior works have mostly focused on using samples from a uniform distribution while designing the approximate circuits, they are unable to exploit input aware properties to design optimal circuits. Hence, in this work, we bridge this gap and propose Formally Verified Library of Input Data Aware Approximate Circuits (FV-LIDAC). FV-LIDAC is the first formally verified library of input distribution aware approximate arithmetic circuits. We use three of the most widely occurring distributions, namely uniform, normal, and exponential distributions, to show that optimal design sets are heavily dependent on the input data. FV-LIDAC chooses the best designs among millions of functional approximated adder and multiplier circuits, depending upon the inputs. Since there are no existing input-aware approximate circuit libraries, we compared FV-LIDAC against state-of-the-art input-unaware EvoApproxLib, to further highlight the need for FV-LIDAC. Additionally, we perform case studies on real-world applications to further highlight the improvement over state-of-the-art. We aim to make the Pareto-optimal designs available as open source to stimulate further research.

Modern telecommunication technologies, such as the 5G and upcoming 6G networks, rely on devices operating in the radio frequency (RF) spectrum of 0.3–90 GHz and 7–300 GHz, respectively. To meet these demanding frequency requirements, new manufacturing methods and device architectures are gaining increasing attention. However, achieving scalable manufacturing alongside ultra-fast device operation presents formidable techno-economic challenges. Here, we explored a modified version of adhesion lithography (a-Lith) to create coplanar nanogap zinc oxide (ZnO) Schottky diodes for application in diode-logic arithmetic circuits. The planar ZnO diodes offer highly scalable manufacturing and combine high current rectification (> 106) with low reverse currents (≈80 pA) and a remarkable cut-off frequency of over 25 GHz. Engineering the topologies of the planar ZnO diodes enables their facile monolithic integration into multi-bit AND and OR gates over 4-inch glass wafers. By integrating several such logic gates, we demonstrated fully functional monolithic 2-bit Half-Adder circuits, the primary component of an arithmetic logic unit. The work offers an alternative method for developing fast large-area electronics that could lead to a new family of logic circuitry.

Accurate decimal calculations are a fundamental requirement in accurate-operated domains such as finance and scientific research. Traditional binary arithmetic circuits, although widely used, often introduce rounding inaccuracy that can cascade in adequate errors in sensitive applications. To address this challenge, this research examines solution by designing the decimal arithmetic circuit using the CMOS-based binary-coded decimal (BCD) Adders. Unlike software-level reforms, the proposed approach embedded accuracy in circuit design itself. Decimal Adders are modeling and valid through the rhythm using 90nm CMOS technology, which ensures high loyalty in logic implementation. In addition, both Cadence virtuoso and tanner are organized to evaluate demonstration matrix using wide simulation, power efficiency and operating delays using EDA equipment. The benchmark comparison with existing architecture reveals significant reforms, especially in power consumption. This study confirms the argument that integrating the decimal arithmetic directly into silicon can greatly increase both reliability and computational accuracy in important systems.

Design of Low-Cost and High-Accurate 8-bit Logarithmic Floating-Point Arithmetic Circuits

Efficient quantum arithmetic circuits are commonly found in numerous quantum algorithms of practical significance. To date, the logarithmic-depth quantum adders includes a constant coefficient k ≥ 2 while achieving the Toffoli-Depth of \(k\log {}n + \mathcal {O}(1) \) . In this work, 160 alternative compositions of the carry-propagation structure are comprehensively explored to determine the optimal depth structure for a quantum adder. By extensively studying these structures, it is shown that an exact Toffoli-Depth of \(\log {}n + \mathcal {O}(1) \) is achievable. This presents a reduction of Toffoli-Depth by almost \(50\% \) compared to the best known quantum adder circuits presented to date. We demonstrate a further possible design by incorporating a different expansion of propagate and generate forms, as well as an extension of the modular framework. Our paper elaborates on these designs, supported by detailed theoretical analyses and simulation-based studies, firmly substantiating our claims of optimality within all possible configurations outlined in this work. The results also mirror similar improvements, recently reported in classical adder circuit complexity.

Advanced arithmetic circuits realization using next generation logic gates

ABSTRACT The evolution of Digital Signal Processing (DSP) systems within Very Large Scale Integration (VLSI) era has significantly impacted computational speed, chip size, and power consumption, consequently influencing the overall cost of systems. Typically, sophisticated DSP systems, including peak cancellation with infinite impulse response (PC-IIR) filters, require multiple arithmetic units. Therefore, the performance of PC-IIR filters can be significantly improved by efficient design of arithmetic logic circuits. In this paper, a new multiple-stage fast ripple hybrid adder (MS-FRHA) and Compressor-based divide-and-conquer vector multiplier (CDCVM) is introduced for PC-IIR filter. Multiple single-stage carry select structures are combined in the proposed MS-FRHA to increase area, delay, and power performance. Also, CDCVM effectively handles huge numbers by dividing the multiplication problem into smaller sub-problems and uses compressor-based Vedic multiplication (CVM) for each sub-problem. According to simulation data, the proposed arithmetic logic circuits use the least amount of space, time, and power of all the earlier designs. Furthermore, a comparison to the most advanced PC-IIR filter shows that the proposed model can reduce delays and resource consumption.

ABSTRACT Multiplication plays a major role in fundamental arithmetic operations in all real-time deployments. The fundamental arithmetic circuits in many digital image processing (DIP) applications are multipliers and adders. A developing technology called approximate computing involves designing power-efficient circuits with less complexity, although at the expense of some accuracy loss. These circuits are appropriate for applications when precise measurements are not necessary. To overcome these challenges a novel approximate TFIE adder, approximate 5:2 compressor, approximate 4:2 compressor, Approximate TFIE Booth Multiplier1 (ATBM1), Approximate TFIE Booth Multiplier2 (ATBM2), Approximate TFIE Booth Multiplier3 (ATBM3) uses logic such as AND, OR, NOT, modified FA, half adder. The proposed Approximate booth multiplication utilises TFIE FA, TFIE 4:2, and TFIE 5:2 and forms three versions of TFIE multipliers (ATBM1, ATBM2, ATBM3) for high-performance and low-power computing. Additionally, the proposed TFIE multiplier for image processing applications provides higher-resolution output images with lower power consumption. A limited amount of accuracy loss can be tolerated in image sharpening and related applications where approximation computing improves performance and energy economy. The total power required for the proposed ATBM1, ATBM2, ATBM3, approximated 4:2 compressor, and 5:2 compressor method is 0.150 mW, 0.105 mW, 0.103 mW, 0.103 mW, and 0.104 mW respectively. Finally, the proposed technique provides superior performance based on area, power, and delay compared with the prior method.

All-optical encoders and comparators are essential components for high-speed optical computing, enabling ultra-fast data processing with minimal latency and low power consumption. This paper presents a numerical analysis of an all-optical encoder and comparator architecture operating at 120 Gb/s, based on carrier reservoir semiconductor optical amplifier-assisted Mach-Zehnder interferometers (CR-SOA-MZIs). Building upon our previous work on all-optical arithmetic circuits, this study extends the application of CR-SOA-MZI structures to implement five key logic operations between two input signals (A and B): A¯B, AB¯, AB (AND), A¯ B¯ (NOR), and AB + A¯ B¯ (XNOR). The performance of these logic gates is evaluated using the quality factor (QF), yielding values of 17.56, 17.04, 19.05, 10.95, and 8.33, respectively. We investigate the impact of critical design parameters on the accuracy and stability of the logic outputs, confirming the feasibility of high-speed operation with robust signal integrity. These results support the viability of CR-SOA-MZI-based configurations for future all-optical logic circuits, offering promising potential for advanced optical computing and next-generation photonic information processing systems.

Approximate Full Adder is considered important for approximate computing to bring out improvements in the efficiency of circuit design. Adders are constituted as the fundamental blocks of arithmetic circuits and are considered important for computation devices. Arithmetic circuits are based on Carbon Nanotube Field Effect Transistor (CNFET)technology and broadly used in image processing, digital signal processing applications. The Carbon nanotube Field Effect transistor is one of the significant areas of research going and adaptable for scaling. It overcome the challenges such as high leakage current, hot effect on electrons, Drain-Induced Barrier Lowering (DIBL), impacts on a short channel effect, etc. They are having of P-type and N-type CNFET’s of equal sizes and provide same drive currents, that is essential for reducing the transistor sizes in the complex circuit designs. To evaluate the efficiency between transistor level and application-level simulations HSPICE and MATLAB software are carried out. The results that obtain from HSPICE software with the full adders/multipliers/approximate adders are carried out in applications of image processing.