Area Array Packages Research Articles

Failure analysis of automotive electronics and microsystems

This paper presents the results of experiments and combined numerical calculations for various kinds of automotive sensors and different microcomponents and microsystems for 'high tech' applications. With growing miniaturization, the 'local' properties of interconnected materials exert a greater influence on the reliability of microcomponents and microsystems than in any macroscopic component. The research team of the author has applied such techniques as acoustic microscopy, laser scanning microscopy, thermography, various kinds of laser field measuring techniques, X-ray stress analysis and the micro-DAC method, combined with FEA field simulation and reliability concepts. Special attention has been given to analysing the thermal fatigue and creep behaviour of solder regions (e.g. solder bumps and micro-solder interconnects) in the near chip regions of microsystem packages and housings. Advanced packaging strategies in automotive applications (e.g. the micromechatronic packaging approach, area array packaging, CSP, etc.) are in the focus of this research. The micro-moire´and micro-DAC techniques are described, using a laser and electron beams for the detection of local micro-deformation fields as well. Different automotive sensors, HF devices and other microcomponents and microsystems have been investigated and evaluated with respect to reliability and lifetime estimation. Crack avoidance strategies have been developed and employed successfully in various applications. Besides the classic concepts of FEA and also stochastic FEM, tools are applied in detail and combined with probabilistic fracture concepts to study the influence of scattering material parameters and of the geometric configuration on reliability estimations as well. The aim is to show that an adequate combination of advanced experimental and simulation approaches leads to reliable results for failure assessment and lifetime predictions of 'high tech' microsystems, e.g. MEMS, in automotive applications.

Mechanical cycling fatigue of PBGA package interconnects

Increased packaging density in micro-electronic products has advantaged attach of BGA, micro-BGA, CSP, and DCA packages. These area array packages are assembled to circuit boards that are reduced in size and thickness, by necessity. These assemblies would include flexible thin laminate circuit boards with area array components attached by solder balls. In normal use, these assemblies would be subjected to numerous ultra-low frequency mechanical deflections; consider a keypad when the user enters telephone numbers. Most of the reliability studies of area array packages have dealt with temperature cycling induced fatigue. However, less attention has been paid to mechanical bending fatigue of these packages. A test method has been developed to elucidate the mechanical bending fatigue issues of BGA, micro-BGA, CSP, and DCA packages attached to printed circuit boards. Appropriate bending fatigue reliability models and their theoretical basis are being developed. The test method and preliminary mechanical cyclic fatigue data on a PBGA package will be presented as a function of printed circuit board thickness. Consideration will be given to fatigue fracture morphology and its relation to solder joint location and rate of crack growth.

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.

Escape routing design to reduce the number of layers in area array packaging

High density multilayer substrate technologies are indispensable to accommodate high input/outputs (I/Os) fine pitch area array integrated circuits (ICs), chip scale packages/ball grid arrays (CSP/BGAs) in the coming packaging generation. They must provide not only a high wiring density, but also an acceptable low cost, short turn around time (TAT) and reliability. Reduction of the number of layers is expected to be a reasonable solution for the conflicting demands. General approaches to reduce the layer count have been to decrease the size of the routing line width and spacing. However, they need changes in the manufacturing processes and materials, causing an increased cost. From escape routing design viewpoint, effects of routing manner on the layer count have been studied. A preferential routing creates specific pad geometry resulting in a high wiring efficiency. This effect can be estimated with an increase in the number of lines per layer routable as a contribution of "the hybrid channel," depending on capture pad pitch-pad diameter-line width-interline space relationship. It is one of the remarkable cases recognized that, within one line per channel rule, the preferential routing can be almost equivalent to that by two lines per channel with regard to the wireability. Its better effect on cost and TAT can also be expected compared with the two thinner sized lines per channel rule, since nothing changes in both manufacturing processes and materials is needed. This method is applicable immediately to packages and boards for assembly of the high I/O flip chips, CSPs, and BGAs.

A System for First Order Reliability Estimation of Solder Joints in Area Array Packages

In this paper, a methodology, and a program based on the methodology, are presented, which, using the reliability of solder joints for various values of design/process parameters, can be estimated in seconds on a personal computer. The proposed methodology accurately captures the behavior of a solder joint in an artificial neural network (ANN) model trained to relate design as well as analysis parameters to fatigue life. The proposed methodology is novel since such simultaneous analysis and design (SAND) procedures do not appear to have been employed until now for reliability estimation of solder joints. The use of Moire´ interferometry as an experimental technique to estimate the analysis-related inputs to the neutral network model is also presented in the paper. [S1043-7398(00)01101-4]

Thermal fatigue analysis of the flip chip assembly on the polymer stud grid array (PSGA) package

Presents the thermo‐mechanical modelling of a new type of area array package: the flip chip on polymer stud grid array (PSGA). The objective is to optimise the material and geometrical design of this PSGA package and the flip chip assembly in order to achieve the highest thermal fatigue reliability for the solder joints in this structure. A parameterised non‐linear finite element model is used to calculate the inelastic strains induced in the solder joints due to thermal cycling. The techniques of design of experiments (DOE) and response surface modelling (RSM) enhance the parameter sensitivity analysis and optimisation of the PSGA design. After the optimisation of the structure, a very high solder joint fatigue reliability of this flip chip to PSGA package has been achieved.

Foreword contributions from the 1998 intersociety conference on thermal and thermomechanical phenomena in electronic packages

HE Thermomechanical analysis of electronic packages is a critical aspect of reliability assessment. Although the focus of earlier Intersociety Conferences on Thermal and Thermomechanical Phenomena in Electronic Packages (ITherm) was on thermal analysis, thermomechanical issues that ensue from thermally-induced strains and stresses are receiving increased attention at the Conference. ITherm has been making steady progress in terms of quantity and quality of papers in this area over the years and we expect it to hold for ITherm 2000. In this special section of this TRANSACTIONS ,w e showcase outstanding papers that were presented at ITherm 98 on thermomechanical issues related to electronic packaging. Seven papers are selected for this special issue based on a rigorous review process. The majority of the papers deal with various aspects of the solder joint reliability, mainly in the flip-chip ball grid array (BGA) packages. Based on a parametric study of the effect of voids in the underfill of a ceramic BGA, Niu et al. have concluded that the edge voids decrease C4 fatigue life where as middle and center voids have less impact. A comparison of solder joint reliability for ceramic quad-flat-pack and CBGA packages for two typical accelerated temperature cycles (0 C to 100 C and 40 C to 125 C) of interest for microprocessors has been carried out by Gerke et al. They have also looked at the effect of temperature gradient on solder joint reliability by using experimentally measured temperatures. Bailey et al. have integrated the effect of fluid flow, heat transfer during solidification, and stress evolution on solder joint formation. Ayhan and Nied have applied enriched crack tip finite elements for prediction of interface fracture parameters. They have evaluated two-dimensional and three-dimensional models for moisture absorption and thermal cycling. Material properties and BGA model validation issues are addressed in the last three papers. Using a three-point bending test, Tay and Lin have measured the effect of temperature and moisture on interfacial fracture toughness for molded QFPs. They have also examined the effect of interfacial defect location of fixed initial size on interfacial crack growth. Tran et al. have characterized fracture toughness for various underfill materials for improved adhesion. Finally, Zhang et al. have Publisher Item Identifier S 1521-3331(99)10361-1. used a combined experimental and numerical approach to evaluate various material and geometric assumptions made in the analyses of area-array packages. We hope the papers presented here will add to the knowledge of predictive engineering. We wish to acknowledge the efforts of many individuals who helped with this special section on mechanics. We would like to thank all the reviewers for their tireless efforts in completing the reviews in a short period of time. In some cases, this involved two rounds of reviews. We would like to thank J. Starbird and K. Mauch of the Editor’s office for administrative assistance. Last, but not least, this effort would not have been possible but for the encouragement and guidance of Editor-in-Chief Avram Bar-Cohen.

Manufacture of high density interconnection substrates by co‐lamination of inner layers and programmed interconnection joining layers

While promising significant improvements in the cost and performance of electronic systems, the advent of new area array packaging concepts such as the BGA and newer area array CSPs has placed significant new demands on the substrates used in their interconnection. New methods such as build‐up multilayers and micro vias and co‐lamination of inner layers have been described and implemented by a number of different firms in an attempt to address this important issue. One such method employs simple double‐sided plated through hole flex circuits and the use of conductive pastes and bondplies to provide reliable electrical and mechanical connection between layers during a simple lamination cycle. The process, briefly described herein as a co‐laminated multilayer flex, is detailed in terms of both process steps and manufacturing flow. The structure of the interconnection substrate is also modeled and examined to determine its electrical performance potential according to electrical modeling software. Finally, detailed are the performance of the structure in reliability testing and an analysis of the expected design and performance advantages that might be obtained by such type constructions in combination with BGAs and area array CSPs.

Interconnect solutions for advanced area array packaging

CSP (chip scale packaging) and flip chip area array technologies are emerging within the electronics packaging industry to provide solutions capable of fulfilling the technological demands of computer, telecom and consumer electronic products. However, the full potential of area array attach can only be realised if the next level of interconnect is capable of supporting the fine pitch and high I/O characteristics of emerging CSP and flip chip technology. Celestica has addressed this issue by investigating next generation printed circuit board (PCB) technology, to assess the capability of organic based laminate as a high density interconnect. This paper describes the manufacturing experiments performed to produce a laser microvia interconnect solution. The mechanical performance of the interconnect is also presented to confirm its compatibility with area array assembly.

Materials issues in area-array microelectronic packaging

The important issues in advanced area-array electronic packaging for semiconductor devices are materials driven. Some of the processing-driven materials issues include the effect of introducing a silicon device interface with copper pads and a low-κ dielectric, the effect of decreasing pitch and feature size on the package interconnects, the development and implementation of organic substrates, and advanced underfills for fine-pitch flip-chip applications. From a materials reliability aspect, important materials issues include enhanced solder interconnect reliability, α-particle-induced soft errors, and the introduction of lead-free solder alloys.

The accuracy of structural approximations employed in analysis of area array packages

At the present time, area-array packages are a very common electronics packaging approach. One of the major concerns in designing such packages is the reliability of solder joints, die, and the various material interfaces present in the package. Currently, analytical, numerical, and experimental methods are employed in the analysis of thermo-mechanical stresses/strains in area array packages. The sources of error in these analytical and numerical models may be broadly characterized as being due to geometry representation, material behavior, solution procedure, and due to the accuracy in representing the load history. In this paper we assess the errors in package models due to geometry representation and material behavior using a representative area-array package, namely the 225 input/output (I/O) plastic ball grid array (PBGA). The package deformation due to a fixed temperature change is experimentally characterized using Moire interferometry and numerically simulated using both two- and three-dimensional finite element models. The difference in behavior between the finite element prediction and experimental results is explained using solder material behavior data available in the literature. A comparison of accuracy as well as efficiency is made between the different finite element models. Finally, conclusions are drawn on the aspects of package construction and material that influence behavior, and on the most efficient finite element model to accurately capture this behavior.

S-parameter based technique for simultaneous switching noise analysis in electronic packages

A method based on S-parameters is developed for the analysis of simultaneous switching noise (SSN) in electronic packages. A two-port Z matrix of the package pin/trace, and the coupling between the pins/traces are modeled by analytical equations. SSN is analyzed as a function of the number of switching drivers and switching time. Frequency domain measurements are performed to demonstrate the accuracy of the model. The modeling methodology is applied to both leaded and area array packages.

An Effective Approach for Three-Dimensional Finite Element Analysis of Ball Grid Array Typed Packages

In the literature, the local-global finite element analysis technique plays a very important role in the area array packaging. In this study, the underlying goal is to propose an improved equivalent model for the use in the local/global analysis, and most importantly, provide a systematic procedure in approaching this equivalent model. In addition, the choice of the equivalent beam model will also be extensively investigated. Since the configuration of the solder joint is far from being close to a “beam-like” structure, defining the corresponding equivalent beam involves great levels of difficulties. In order to remove the possible difficulties, an effective way is proposed: incorporating analytical derivations and optimization. To this end, one practical application is presented to substantiate the proposed methodology.

AN EXPERIMENTAL STUDY OF THE SELF CENTERING OF BGA PACKAGES

The use of area array devices, specifically Ball Grid Arrays (BGAs) on Printed Circuit Boards (PCBs) has increased over the past couple of years. One of the advantages offered by BGAs is that they tend to self-align during reflow soldering. This phenomenon can compensate for a substantial amount of component misregistration that can result from the component placement process or from subsequent handling. The mechanism by which an area array package attains self centering is indeed complicated. This study used an experimental approach to identify the acceptable range of misalignment that can be compensated by the package's self centering capability for a given set of process parameters. A variety of BGA components were considered in this research and their placement process window was identified. In addition, weights were added to the packages which were intentionally misregistered during placement to understand the effect of weight on self centering as well as to simulate other possible package configurations (such as the addition of a heat sink).

REWORK OF BGA COMPONENTS

Area array packages are being increasingly used in the surface mount printed circuit board assembly domain due to their unique characteristics and high process yields. Several researchers have indicated that the process defects associated with the ball grid array components on printed circuit board assemblies are dramatically lower than those experienced with traditional leaded components. However, there are a number of other reasons to remove and replace components including package defects, engineering changes that are required after a number of components have been assembled, device or system upgrades, misregistration, wrong component orientation, etc.The rework of ball grid array components is a challenging task since the solder joints are hidden from view and cannot be readily accessed. Traditional approaches to rework that are applied to peripheral leaded or leadless components might not be applicable to ball grid array components. This paper provides a detailed discussion of the rework process for ball grid arrays. Topics that are addressed include the characterization of the rework system, nozzle design, the component removal process, the need for site redressing and the technique to be used, solder and flux application, and the component replacement process. A comprehensive set of process-related recommendations is provided for the rework of ball grid arrays.

Controlled Thermal Expansion Printed Wiring Boards based on Liquid Crystal Polymer Dielecrics

L iguid crystal polymer (LCP) dielectric materials have been used to fabricate surface mount PWBs with a coefficient of thermal expansion matched to leadless ceramic chip carriers. Proprietary and patented polymer processing technology results in self‐reinforcing material with balanced in‐plane mechanical properties. In addition, LCPs possess excellent electrical properties, including a low dielectric constant (∼3) and very low moisture absorption (< 0.02 %). Laser drilling of blind vias in the LCP dielectric provides a very high density for use in direct chip attach and area array packages. Modelling indicates that the high out‐of‐plane CTE of LCPs does not affect the reliability of the plated‐through‐holes vias. RF characterisation indicates that the material is suitable up to very high frequencies. The material is ideally suited to MCM‐L and PCMCIA applications involving very thin dielectric layers of the LCP.

Stress Simulation in Area Array Packaging

Abstract

Development of JEDEC standard thermal measurement test boards

A combination of experimental and modeling studies has been performed to define the impact of printed circuit board (PCB) design on the measured thermal performance of integrated circuit (IC) packages. These results have been used to develop a joint electron device engineering council (JEDEC) test card standard that allows less than 10% measurement variability between the minimum and maximum limits of the design parameters. At the same time, the standard allows wide latitude in layout for various components. The modeling and measurement studies that were performed to set the limits of the standard test coupons for surface mounted components and area array packages such as ball grid arrays (BGAs) are described, along with extensions in principle to actual devices operating in systems.

The Optimal Choice of High Pin Count ASIC Packages

The choice of high pin count ASIC packages has a major impact on the total cost and performance of the whole packaging system. Six different types of ASIC packages have been compared with respect to production aspects, availability, reliability, thermal and electrical properties and cost. Recommendations for the proper choice of packages for different types of applications are given. All packages have been directly assembled to PWBs in order to study problems with handling, solder process, testing and repairability. Some of the assembled packages have been temperature cycled in order to test the solder joint reliability. The pin grid array packages are the most frequently used high pin count packages today. However, they are expensive and through‐hole mounting reduces the routing capability of the board. Pad area array packages are a hermetic alternative with a lower price for the package as well as very good thermal and electrical properties, but they need to be mounted on expensive PWBs. Another surface mountable package which is hermetic is the ceramic leaded chip carrier with fine lead pitch. This package is even more expensive than the pin grid array package and is difficult to handle. In the future, non‐hermetic alternatives will probably predominate. Plastic quad flat pack and TapePak can be used below 160–180 leads, while direct assembled TAB would be the best alternative for very high pin counts. Before one can use non‐hermetic packages in telecom products, a large qualification programme must be performed to evaluate the long‐term reliability.