Processor Architecture Research Articles

AESware: Developing AES-enabled low-power multicore processors leveraging open RISC-V cores with a shared lightweight AES accelerator

As open-source RISC-V cores continue to be released, the development of low-power multicore processors utilizing these cores is invigorating the edge/IoT device market. Nevertheless, comprehensive research on developing low-power multicore processors with integrated security features using existing open RISC-V cores remains limited. This study addresses this gap by introducing AESware, a dedicated lightweight hardware designed for energy-efficient AES (Advanced Encryption Standard) task execution, contributing to the development of AES-specific low-power RISC-V multicore processors. AESware supports variable key lengths and ensures minimal power consumption with a compact design. This standalone IP (Intellectual Property) is compatible with various open RISC-V cores, offering scalability and convenience. And importantly, we propose the most energy-efficient architecture for multicore processors equipped with AESware. Instead of assigning dedicated AESware to each core, we introduce a shared AESware architecture to maximize energy efficiency. We develop an operational algorithm for task scheduling in AESware, achieving maximum utilization and minimal latency while maintaining its lightweight nature. To evaluate our solution, we developed 24 processors into three groups: AESware-equipped, baseline, and those with an external AES accelerator per core. After FPGA (Field-Programmable Gate Array) prototyping for functional verification and power consumption analysis via 45 nm process technology synthesis, our findings revealed significant energy savings. AESware-equipped processors achieved up to 76%, 47%, and 33% energy savings at dual-, quad-, and octa-core configurations compared to baseline, respectively, and were more energy-efficient in running AES applications than those with individual accelerators.

Constant Values Distribution Investigation in the C Programs Source Code

Currently, software engineering plays a key role in software development, one of the criteria for the development of which is the investigation of its factology and various scientific and practical patterns. An important aspect of this area is the logic of program execution, operating with internal data, and, in particular, constant values, the identification of patterns in which actualizes this research. The main applications of this pattern include obtaining fundamental knowledge about algorithms, creating new and expanding existing metrics for evaluating and comparing program code, developing methods for its optimization, using it in genetic programming, etc.The purpose of this article is to obtain the frequency distribution of constant values in the source code of programs in the C programming language.The essence of the presented approach is to create a method for statistical analysis of the text of the source codes of programs contained in the ExeBench dataset (which consists of a huge amount of source code of functions in the C programming language, their assembler code for various processor architectures, compilation errors and other information).The proposed method is based on the use of algorithms for lexical and syntactic analysis of source code functions, semantic definition of constant types, and conversion of the recording of programming language symbols into the corresponding numeric or string values.The method has an implementation in the form of a software tool in the Python programming language, given in the form of an intuitive pseudocode. Experiments using this prototype allowed us to obtain the desired distribution of constant values for the source code of programs in the C programming language. Analysis of the obtained results allowed us to make a number of important theoretical and practical conclusions regarding the most frequently used constants, the correspondence of the obtained distribution to the Zipf law and its proximity to the exponential function, the anomalous appearance of a number of constants in the Top 50, etc.The scientific novelty of the proposed approach lies in the fact that the distribution of constant values for the source code of programs in the C programming language is obtained for the first time.The theoretical significance consists in obtaining new fundamental knowledge regarding the features and patterns of source code constructions, which can be extended to other programming languages.The practical significance consists in applying the distribution to a wide range of tasks, including the author's genetic reverse engineering, which in itself is a qualitatively new direction.

Physiological signal analysis and open science using the Julia language and associated software.

In this mini review, we propose the use of the Julia programming language and its software as a strong candidate for reproducible, efficient, and sustainable physiological signal analysis. First, we highlight available software and Julia communities that provide top-of-the-class algorithms for all aspects of physiological signal processing despite the language's relatively young age. Julia can significantly accelerate both research and software development due to its high-level interactive language and high-performance code generation. It is also particularly suited for open and reproducible science. Openness is supported and welcomed because the overwhelming majority of Julia software programs are open source and developed openly on public platforms, primarily through individual contributions. Such an environment increases the likelihood that an individual not (originally) associated with a software program would still be willing to contribute their code, further promoting code sharing and reuse. On the other hand, Julia's exceptionally strong package manager and surrounding ecosystem make it easy to create self-contained, reproducible projects that can be instantly installed and run, irrespective of processor architecture or operating system.

A High Scalability Memory NoC with Shared-Inside Hierarchical-Groupings for Triplet-Based Many-Core Architecture

Innovative processor architecture designs are shifting towards Many-Core Architectures (MCAs) to meet the future demands of high-performance computing as the limits of Moore’s Law have almost been reached. Many-core processors utilize shared memory hierarchies to achieve high-speed memory systems, improving memory access efficiency. However, as the number of cores multiplies, the scalability of this system is significantly constrained by the increased proportion of long-distance and Non-Uniform Memory Access (NUMA). Improving the scalability of MCAs is crucial for achieving large/super-scale general-purpose many-core processors. This work proposes a high scalability memory Network-on-Chip (NoC) for Triplet-Based Many-Core Architecture (TriBA), named TriBA-mNoC. TriBA-mNoC maintains a consistent core-to-core spacing as the network scale increases, effectively preventing increased long-distance memory access latency. Moreover, it leverages an inherent advantage of shared-inside hierarchical-groupings, alleviating common NUMA issues in the NoC design. Evaluations of static network characteristics show that TriBA-mNoC outperforms most classical NoCs in network diameter, average distance, and cost. TriBA-mNoC can be integrated with TriBA in the same silicon die with a tile-like floorplan, forming a novel NoC called TriBA-NoC, which can combine the strengths of both networks to maximize the architecture performance. We evaluated the memory access performance and scalability of TriBA-NoC using the mathematical evaluation models and actual simulations with real traffic (PARSEC 3.0 and SPLASH-2) at different network scales. The mathematical evaluation results indicate that TriBA-NoC achieves an aggregate speedup of approximately 3x compared with 2D-Mesh for a similar number of cores. Furthermore, TriBA-NoC’s single-core speedup efficiency remains stable as the number of cores increases under the same cache hit ratio, while 2D-Mesh experiences a rapid decline, highlighting TriBA-NoC’s exceptional scalability. Finally, the actual traffic simulation results show that TriBA-NoC achieves an average memory access latency and time reduction of 25.90% − 40.50% and 5.61% − 31.69% respectively, compared with 2D-Mesh.

Conflict Management in Vector Register Files

The instruction set architecture (ISA) of vector processors operates on vectors stored in the vector register file (VRF) which needs to handle several concurrent accesses by functional units (FUs) with multiple ports. When the vector processor is running with high utilization, access conflicts become a major source of performance degradation. With a software model of a vector processor, we take a deep dive into the runtime impact of conflicts, their characteristics, and on ways to manage them, i.e., avoidance, resolution, and mitigation. For conflict avoidance, we study the existing approaches of banking with different static bank layouts and propose a dynamic bank layout to overcome their shortcomings. Our approach assigns newly written registers a temporarily unique starting bank. For conflict resolution, we compare different arbitration algorithms and optimize round-robin arbitration for mixed-width arithmetics by prioritizing wide operands. For conflict mitigation, operand queues (OPQs) of varying depths are studied. Our inventions are likely to increase the area efficiency of vector processors. Either, because they allow to use shallower operand queues (OPQs) while keeping the same performance, or reduce the area even further by using less banks, albeit at a performance impairment of 10 % or less. The insights of the study can further be applied to other shared-memory systems.

Efficient Decoupling of a Nonlinear Qubit Mode from Its Environment

To control and measure the state of a quantum system, it must necessarily be coupled to external degrees of freedom. This inevitably leads to spontaneous emission via the Purcell effect, photon-induced dephasing from measurement backaction, and errors caused by unwanted interactions with nearby quantum systems. To tackle this fundamental challenge, we make use of the design flexibility of superconducting quantum circuits to form a multimode element—an artificial molecule—with symmetry-protected modes. The proposed circuit consists of three superconducting islands coupled to a central island via Josephson junctions. It exhibits two essential nonlinear modes, one of which is flux insensitive and used as the protected qubit mode. The second mode is flux tunable and serves via a cross-Kerr-type coupling as a mediator to control the dispersive coupling of the qubit mode to the readout resonator. We demonstrate the Purcell protection of the qubit mode by measuring relaxation times that are independent of the mediated dispersive coupling. We show that the coherence of the qubit is not limited by photon-induced dephasing when detuning the mediator mode from the readout resonator and thereby reducing the dispersive coupling. The resulting highly protected qubit, which we refer to as P-mon, with tunable interactions may serve as a basic building block of a scalable quantum processor architecture, in which qubit decoherence is strongly suppressed. Published by the American Physical Society 2024

Image Classification with Hypertensive Angle Disease Detection with Geometric Local Derivative Pre-Processing

It is recognized as conjunctivitis stands as that of the second-greatest source of disability. Early detection and management of ophthalmology are essential for preventing disease owing to the benign character of loss of vision mostly in early stages of the illness and the permanent condition of vision in later stages. Straight retinal inspection, commercial digital images, laser scanners spectroscopy, scanning infrared additional factor and confocal tomography (OCT) images can all is used it to identify hypertension. These findings suggest using a Vertical Harmonic oscillator Dynamic Hinge Supporting Machine Classifier (Embedded systems) to predict glaucoma. There really are three stages to the Repository system. All those are ophthalmology identification, extraction and classification, and processing. The retina source images first were analyzed using a Geometric Local Derivative Pre - processor architecture to extract the major characteristics required for early diagnosis. The precompiled images then are submitted to Harmonic oscillator Discontinuous Single - input single Probability distribution Extraction Of features to identify significant characteristics with the sensitivity for disease prediction. Lastly, Inter Hinge Gradient Boosting Retinal Identification employs the derived features to detect glaucoma early and effectively. The Retina Mri image datasets was utilized in Simulation experiments to examine the effectiveness of the suggested method, embedded systems. Computational complexity, sensitivities, and correctness performance criteria must be looked at with respect to different Optical image quantities.

Environmental sound classification on an embedded hardware platform

Convolutional neural networks (CNNs) have exhibited state-of-the-art performance in various audio classification tasks. However, their real-time deployment remains a challenge on resource constrained devices such as embedded systems. In this paper, we analyze how the performance of large-scale pre-trained audio neural networks designed for audio pattern recognition changes when deployed on a hardware such as a Raspberry Pi. We empirically study the role of CPU temperature, microphone quality and audio signal volume on performance. Our experiments reveal that the continuous CPU usage results in an increased temperature that can trigger an automated slowdown mechanism in the Raspberry Pi, impacting inference latency. The quality of a microphone, specifically with affordable devices such as the Google AIY Voice Kit, and audio signal volume, all affect the system performance. In the course of our investigation, we encounter substantial complications linked to library compatibility and the unique processor architecture requirements of the Raspberry Pi, making the process less straightforward compared to conventional computers (PCs). Our observations, while presenting challenges, pave the way for future researchers to develop more compact machine learning models, design heat-dissipative hardware, and select appropriate microphones when AI models are deployed for real-time applications on edge devices.

PF‐GEMV: Utilization maximizing architecture in fast matrix–vector multiplication for GPT‐2 inference

AbstractOwing to the widespread advancement of transformer‐based artificial neural networks, artificial intelligence (AI) processors are now required to perform matrix–vector multiplication in addition to the conventional matrix–matrix multiplication. However, current AI processor architectures are optimized for general matrix–matrix multiplications (GEMMs), which causes significant throughput degradation when processing general matrix–vector multiplications (GEMVs). In this study, we proposed a port‐folding GEMV (PF‐GEMV) scheme employing multiformat and low‐precision techniques while reusing an outer product‐based processor optimized for conventional GEMM operations. This approach achieves 93.7% utilization in GEMV operations with an 8‐bit format on an 8 8 processor, thus resulting in a 7.5 increase in throughput compared with that of the original scheme. Furthermore, when applied to the matrix operation of the GPT‐2 large model, an increase in speed by 7 is achieved in single‐batch inferences.

The RAS Paradigm in Mainframe Systems: A Comprehensive Analysis of Design Principles and Operational Benefits

This article examines the critical role of Reliability, Availability, and Serviceability (RAS) in mainframe computing systems. We explore how RAS principles have become fundamental design features in modern mainframes, enhancing their ability to meet the demanding requirements of enterprise-level data processing. The article provides an in-depth analysis of each RAS component, detailing how reliability is achieved through robust hardware self-checking and extensive software testing, availability is maintained via seamless component failover and layered error recovery, and serviceability is ensured through advanced diagnostic capabilities and modular replacement units. We argue that the holistic integration of RAS principles in mainframe architecture not only maximizes system uptime and operational continuity but also significantly impacts application design and overall system efficiency. Through a comprehensive review of current mainframe technologies and industry practices, this article highlights the enduring importance of RAS in an era of increasing computational complexity and datadriven decision making. Our findings suggest that RAS principles will continue to evolve, playing a crucial role in shaping the future of high-performance, mission-critical computing systems.

Design and implementation in power-efficient and thermal conductivity of vedic processor for embedded applications

An embedded system that handles critical applications requires power economy, performance and thermal management, and an efficient Vedic processor with highly efficienct thermal conductivity. The proposed contemporary processor architecture has been designed to use Vedic mathematics and elaborate power and thermal optimization approaches to formulate an Arithmetic Logic Unit (ALU). This ALU is based on Vedic Sutras to enable quick computation, high precision floating point operations, and low power consumption. Since thermal management leads to energy loss in the form of heat, the embedded processor’s thermal conductivity is enhanced using novel materials and unique ways of heat dissipation. This improves performance as well as power efficiency. The proposed approach uses extensive simulation thermal analysis by EDA tools to build an optimised embedded processor that consumes 35% less power, has 40% high thermal conductivity, is 25% faster, and utilizes 15% less area when compared to conventional embedded processors. This paper helps in furthering embedded systems research by showing how old mathematical ideas can be used in a new engineering approach to solve current technology issues. The suggested novel embedded system is more efficient and thermally resistant for IOT, mobile computing, and industrial control systems.

Docker Performance Evaluation across Operating Systems

Docker has gained significant popularity in recent years. With the introduction of Docker Desktop for Windows and macOS, there is a need to determine the impact of the operating system on the performance of the Docker platform. This paper aims to investigate the performance of Docker containers based on the operating system. One of the fundamental goals of this study is to conduct a comprehensive analysis of the Docker architecture. This technology utilizes Linux kernel virtualization mechanisms such as namespaces and cgroups. Upon analyzing the distribution of Docker Desktop for Windows and Docker Desktop for macOS, it was discovered that running the Docker environment on these requires a lightweight virtual machine that emulates the Linux system. This information suggests that the additional virtualization layer may hinder the performance of non-Linux operating systems hosting Docker containers. The paper presents a performance test of the Docker runtime on Linux, Microsoft Windows, and macOS. The test evaluated specific aspects of operating system performance on a MacBook computer with an ×86/64 processor architecture. The experiment carried out examined the performance in terms of CPU speed, I/O speed, and network throughput. This test measured the efficiency of software that utilizes various system resources.

Implementation and optimization of SpMV algorithm based on SW26010P many-core processor and stored in BCSR format

The irregular distribution of non-zero elements of large-scale sparse matrix leads to low data access efficiency caused by the unique architecture of the Sunway many-core processor, which brings great challenges to the efficient implementation of sparse matrix–vector multiplication (SpMV) computing by SW26010P many-core processor. To address this problem, a study of SpMV optimization strategies is carried out based on the SW26010P many-core processor. Firstly, we design a memorized data storage transformation strategy to transform the matrix in CSR storage format into BCSR (Block Compressed Sparse Row) storage. Secondly, the dynamic task scheduling method is introduced to the algorithm to realize the load balance between slave cores. Thirdly, the LDM memory is refined and designed, and the slave core dual cache strategy is optimized to further improve the performance. Finally, we selected a large number of representative sparse matrices from the Matrix Market for testing. The results show that the scheme has obviously speedup the processing procedure of sparse matrices with various sizes and sizes, and the master–slave speedup ratio can reach up to 38 times. The optimization method used in this paper has implications for other complex applications of the SW26010P many-core processor.

Wearable Processors Architecture: A Comprehensive Analysis of 64-bit ARM Processors

Wearable Processors Architecture: A Comprehensive Analysis of 64-bit ARM Processors

Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators - Trends in Quantum Computing, Heterogeneous Systems and Reliability

Rapid progress in CMOS technology since the late 1990s has increased the vulnerability of processors toward faults. Subsequently, the focus of computer architects has shifted toward designing fault-tolerance methods for processor architectures. Concurrently, chip designers have encountered high-order challenges for designing fault-tolerant processor architectures. For processor cores, redundancy-based fault-tolerance methods for fault detection at the core, micro-architectural, thread, and software levels are discussed. Similar applicable redundancy-based fault-tolerance methods for cache memory and hardware accelerators are also presented in the article. Recent trends in fault-tolerant quantum computing and quantum error correction are also discussed. The classification of state-of-the-art techniques presented will help researchers organize their work on established lines.

Применение нейроморфных электроактивных макроячеек для повышения надежности пространственной ориентации

Neural network architecture based on polymer macrocells acting as neural elements and capable to generate electrically conductive synaptic junctions is developed. The architecture of a neural network processor where each component can record and produce a response to energy effects of different nature: electrical, optical and electrostatic has been developed. This function of the neural network eliminates the limitations related to the perception of the input information only by the input layer of the neural network processor. The impact of the influence of different input data representations on the information processing by the macrocell has been studied. The efficiency of temporal and electrical degradation of a neural network macrocell as a complex phenomenon directed on adaptation of a neural network to this process and generation of an algorithm for distribution of elements of a tutorial sample evenly over the total volume of available neural cells has been studied. The article studies a method of generation of episodic circulating memory, which significantly improves the speed of generation of a solution by the network, taking into account the gravitational interaction with macrocells. The revealed specific nature of the influence of the gravitational field on the functioning of neural network clusters was the basis for natural selection of cells by the performed properties depending on the spatial position in the neural network architecture. A method of exposure of the cell to physical equivalents of tutorial sample elements converted into different energy patterns to control the configuration of the macrocell using all available modes of information perception has been provided. Each exposure containing information on the tutorial element (optical and electrostatic) supports the generated generalising abilities of the neural macrocells composition. Practical significance of the performed research comprises the designed neural network system, which achieves an increase in performance due to self-organising oscillating neural clusters. The developed neural network model is used to reduce radio deviation and associated navigation errors due to conductive obstacles or atmospheric formations.

Using hardware-transactional-memory support to implement speculative task execution

Loops take up most of the time of computer programs, so optimizing them so that they run in the shortest time possible is a continuous task. However, this task is not negligible; on the contrary, it is an open area of research since many irregular loops are hard to parallelize. Generally, these loops have loop-carried (DOACROSS) dependencies and the appearance of dependencies could depend on the context. Many techniques have been studied to be able to parallelize these loops efficiently; however, for example in the OpenMP standard there is no efficient way to parallelize them. This article presents Speculative Task Execution (STE), a technique that enables the execution of OpenMP tasks in a speculative way to accelerate certain hot-code regions (such as loops) marked by OpenMP directives. It also presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support for executing tasks speculatively and describes a careful evaluation of the implementation of STE using HTM on modern machines. In particular, we consider the scenario in which speculative tasks are generated by the OpenMP taskloop construct (Speculative Taskloop (STL)). As a result, it provides evidence to support several important claims about the performance of STE over HTM in modern processor architectures. Experimental results reveal that: (a) by implementing STL on top of HTM for hot-code regions, speed-ups of up to 5.39× can be obtained in IBM POWER8 and of up to 2.41× in Intel processors using 4 cores; and (b) STL-ROT, a variant of STL using rollback-only transactions (ROTs), achieves speed-ups of up to 17.70× in IBM POWER9 processor using 20 cores.

The SpinBus architecture for scaling spin qubits with electron shuttling

Quantum processor architectures must enable scaling to large qubit numbers while providing two-dimensional qubit connectivity and exquisite operation fidelities. For microwave-controlled semiconductor spin qubits, dense arrays have made considerable progress, but are still limited in size by wiring fan-out and exhibit significant crosstalk between qubits. To overcome these limitations, we introduce the SpinBus architecture, which uses electron shuttling to connect qubits and features low operating frequencies and enhanced qubit coherence. Device simulations for all relevant operations in the Si/SiGe platform validate the feasibility with established semiconductor patterning technology and operation fidelities exceeding 99.9%. Control using room temperature instruments can plausibly support at least 144 qubits, but much larger numbers are conceivable with cryogenic control circuits. Building on the theoretical feasibility of high-fidelity spin-coherent electron shuttling as key enabling factor, the SpinBus architecture may be the basis for a spin-based quantum processor that meets the scalability requirements for practical quantum computing.

Lightweight Hardware-Based Cache Side-Channel Attack Detection for Edge Devices (Edge-CaSCADe)

Cache Side-Channel Attacks (CSCAs) have been haunting most processor architectures for decades now. Existing approaches to mitigation of such attacks have certain drawbacks, namely software mishandling, performance overhead, and low throughput due to false alarms. Hence, “mitigation only when detected” should be the approach to minimize the effects of such drawbacks. We propose a novel methodology of fine-grained detection of timing-based CSCA using a hardware-based detection module. We discuss the design, implementation, and use of our proposed detection module in processor architectures. Our approach successfully detects attacks that flush secret victim information from cache memory like Flush+Reload, Flush+Flush, Prime+Probe, Evict+Probe, and Prime+Abort, commonly known as cache timing attacks. Detection is on time with minimal performance overhead. The parameterizable number of counters used in our module allows detection of multiple attacks on multiple sensitive locations simultaneously. The fine-grained nature ensures negligible false alarms, severely reducing the need for any unnecessary mitigation. The proposed work is evaluated by synthesizing the entire detection algorithm as an attack detection block, Edge-CaSCADe, in a RISC-V processor as a target example. The detection results are checked under different workload conditions with respect to the number of attackers and the number of victims having RSA-, AES-, and ECC-based encryption schemes like ECIES, and on benchmark applications like MiBench and Embench. More than 98% detection accuracy within 2% of the beginning of an attack can be achieved with negligible false alarms. The detection module has an area and power overhead of 0.9% to 2% and 1% to 2.1% for the targeted RISC-V processor core without cache for one to five counters, respectively. The detection module does not affect the processor critical path and hence has no impact on its maximum operating frequency.

P‐52: Scalable Multi‐layered Real‐time Holography Processor Architecture with High Bandwidth Memory (HBM)

In this paper, we present a fast and efficiently scalable 3D holographic video processor using a layer‐based method using a modified inverse Fresnel transform. In our previous paper, we designed a single‐layer holographic core using a fixed‐point model and tested its operation on an FPGA. This paper implements an 8‐layer, 15FPS real‐time hologram processor by receiving RGB and depth input. For fast CGH processing, we utilized HBM memory, which is faster than DDR4, to store FFT results. After applying 2× linear interpolation, the implemented real‐time holography processor converts into real‐time holograms using a 4K color space light modulator