Architecture Overhead Research Articles

Frame Selection Using Spatiotemporal Dynamics and Key Features as Input Pre-processing for Video Super-Resolution Models

This paper presents a novel approach to video super-resolution (VSR) by focusing on the selection of input frames, a process critical to VSR. VSR methods typically rely on deep learning techniques, those that are able to learn features from a large dataset of low-resolution (LR) and corresponding high-resolution (HR) videos and generate high-quality HR frames from any new LR input frames using the learned features. However, these methods often use as input the immediate neighbouring frames to a given target frame without considering the importance and dynamics of the frames across the temporal dimension of a video. This work aims to address the limitations of the conventional sliding-window mechanisms by developing input frame selection algorithms. By dynamically selecting the most representative neighbouring frames based on content-aware selection measures, our proposed algorithms enable VSR models to extract more informative and accurate features that are better aligned with the target frame, leading to improved performance and higher-quality HR frames. Through an empirical study, we demonstrate that the proposed dynamic content-aware selection mechanism improves super-resolution results without any additional architectural overhead, offering a counter-intuitive yet effective alternative to the long-established trend of increasing architectural complexity to improve VSR results.

COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing

To achieve high accuracy, convolutional neural networks (CNNs) are increasingly growing in complexity and diversity in layer types and topologies. This makes it very challenging to efficiently deploy such networks on custom processor architectures for resource-scarce edge devices. Existing mapping exploration frameworks enable searching for the optimal execution schedules or hardware mappings of individual network layers, by optimizing each layer’s spatial (dataflow parallelization) and temporal unrolling (TU, execution order). However, these tools fail to take into account the overhead of supporting different unrolling schemes within a common hardware architecture. Using a fixed unrolling scheme across all layers is also not ideal, as this misses significant opportunities for energy and latency savings from optimizing the mapping of diverse layer types. A balanced approach assesses the right amount of mapping flexibility needed across target neural networks, while taking into account the overhead to support multiple unrollings. This article, therefore, presents cross-layer optimization of accelerator configurability (COAC), a cross-layer design space exploration and mapping framework to optimize the flexibility of neural processing architectures by balancing configurability overhead against resulting energy and latency savings for end-to-end inference. COAC does not only provide a systematical analysis of the architectural overhead in function of the supported spatial unrollings (SUs), but also builds an automated flow to find the best unrolling combination(s) for efficient end-to-end inference with limited hardware overhead. Results demonstrate that architectures with carefully optimized flexibility can achieve up to 38% energy-delay-product (EDP) savings for a set of six neural networks at the expense of a relative area increase of 9.5%.

MTHAEL: Cross-Architecture IoT Malware Detection Based on Neural Network Advanced Ensemble Learning

The complexity, sophistication, and impact of malware evolve with industrial revolution and technology advancements. This article discusses and proposes a robust cross-architecture IoT malware threat hunting model based on advanced ensemble learning (MTHAEL). Our unique MTHAEL model using stacked ensemble of heterogeneous feature selection algorithms and state-of-the-art neural networks to learn different levels of semantic features demonstrates enhanced IoT malware detection than existing approaches. MTHAEL is the first of its kind that effectively optimizes recurrent neural network (RNN) and convolutional neural network (CNN) with high classification accuracy and consistently low computational overheads on different IoT architectures. Cross-architecture benchmarking is performed during the training with different architectures such as ARM, Intel80386, MIPS, and MIPS+Intel80386 individually. Two different hardware architectures were employed to analyze the architecture overhead, namely Raspberry Pi 4 (ARM-based architecture) and Core-i5 (Intel-based architecture). Our proposed MTHAEL is evaluated comprehensively with a large IoT cross-architecture dataset of 21,137 samples and has achieved 99.98 percent classification accuracy for ARM architecture samples, surpassing prior related works. Overall, MTHAEL has demonstrated practical suitability for cross-architecture IoT malware detection with low computational overheads requiring only 0.32 seconds to detect Any IoT malware.

Packet Size Optimization for Cognitive Radio Sensor Networks Aided Internet of Things

Cognitive radio sensor networks (CRSNs) is the state-of-the-art communication paradigm for power constrained short range data communication. It is one of the potential technologies adopted for Internet of Things (IoT) and other futuristic machine-to-machine-based applications. Many of these applications are power constrained and delay sensitive. Therefore, CRSN architecture must be coupled with different adaptive and robust communication schemes to take care of the delay and energy efficiency at the same time. Considering the tradeoff that exists in terms of energy efficiency and overhead delay for a given data packet length, it is proposed to transmit the physical layer payload with an optimal packet size (OPS) depending on the network condition. Furthermore, due to the cognitive feature of CRSN architecture overhead energy consumption due to channel sensing and channel handoff plays a critical role. Based on the above premises, in this paper, we propose a heuristic exhaustive search-based Algorithm-1 and a computationally efficient suboptimal low complexity Karuh–Kuhn–Tucker (KKT) condition-based Algorithm-2 to determine the OPS in CRSN architecture using variable rate m-QAM modulation. The proposed algorithms are implemented along with two main cognitive radio assisted channel access strategies based on distributed time slotted-cognitive medium access control (DTS-CMAC) and centralized common control channel-based cognitive medium access control (CC-CMAC) and their performances are compared. The simulation results reveal that proposed Algorithm-2 outperforms Algorithm-1 by a significant margin in terms of its implementation time. For the exhaustive search-based Algorithm-1 the average time consumed to determine OPS for a given number of cognitive users is 1.2 s, while for KKT-based Algorithm-2, it is of the order of 5–10 ms. CC-CMAC with OPS is most efficient in terms of overall energy consumption but incurs more delay as compared to DTS-CMAC with OPS scheme.

Optimizing virtual machine consolidation performance on NUMA server architecture for cloud workloads

Server virtualization and workload consolidation enable multiple workloads to share a single physical server, resulting in significant energy savings and utilization improvements. The shift of physical server architectures to NUMA and the increasing popularity of scale-out cloud applications undermine workload consolidation efficiency and result in overall system degradation. In this work, we characterize the consolidation of cloud workloads on NUMA virtualized systems, estimate four different sources of architecture overhead, and explore optimization opportunities beyond the default NUMA-aware hypervisor memory management Motivated by the observed architectural impact on cloud workload consolidation performance, we propose three optimization techniques incorporating NUMA access overhead into the hypervisor's virtual machine memory allocation and page fault handling routines. Among these, estimation of the memory zone access overhead serves as a foundation for the other two techniques: a NUMA overhead aware buddy allocator and a P2M swap FIFO. Cache hit rate, cycle loss due to cache miss, and IPC serve as indicators to estimate the access cost of each memory node. Our optimized buddy allocator dynamically selects low-overhead memory zones and "proportionally" distributes memory pages across target nodes. The P2M swap FIFO records recently unused PFN, MFN lists for mapping exchanges to rebalance memory access pressure within one domain. Our real system based evaluations show a 41.1% performance improvement when consolidating 16-VMs on a 4- socket server (the proposed allocator contributes 22.8% of the performance gain and the P2M swap FIFO accounts for the rest). Furthermore, our techniques can cooperate well with other methods (i.e. vCPU migration) and scale well when varying VM memory size and the number of sockets in a physical host

Exploring garbage collection with haswell hardware transactional memory

Intel's latest processor microarchitecture, Haswell, adds support for a restricted form of transactional memory to the x86 programming model. We explore how this can be applied to three garbage collection scenarios in Jikes RVM: parallel copying, concurrent copying and bitmap marking. We demonstrate gains in concurrent copying speed over traditional synchronisation mechanisms of 48-101%. We also show how similar but portable performance gains can be achieved through software transactional memory techniques. We identify the architectural overhead of capturing sufficient work for transactional execution as a major stumbling block to the effective use of transactions in the other scenarios.

PipeRoute: a pipelining-aware router for reconfigurable architectures

We present a pipelining-aware router for fieldprogrammable gate arrays (FPGAs). The problem of routing pipelined signals is different from the conventional FPGA routing problem. The two-terminal N/sub D/ pipelined routing problem is to find the lowest cost route between a source and sink that goes through at least N (N/spl ges/1) distinct pipelining resources. In the case of a multiterminal pipelined signal, the problem is to find a minimum spanning tree (MST) that contains sufficient pipelining resources such that pipelining constraints at each sink are satisfied. In this paper, we first present an optimal algorithm for finding a lowest cost 1/sub D/ route. The optimal 1/sub D/ algorithm is then used as a building block for a greedy two-terminal N/sub D/ router. Next, we discuss the development of a multiterminal routing algorithm (PipeRoute) that effectively leverages both the 1/sub D/ and N/sub D/ routers. Finally, we present a preprocessing heuristic that enables the application of PipeRoute to pipelined FPGA architectures. PipeRoute's performance is evaluated by routing a set of benchmark netlists on the reconfigurable pipelined datapath (RaPiD) architecture. Our results show that the architecture overhead incurred in routing netlists on RaPiD is less than 20%. Further, the results indicate a possible trend between the architecture overhead and the percentage of pipelined signals in a netlist.