ABSTRACT Multiplication plays a major role in fundamental arithmetic operations in all real-time deployments. The fundamental arithmetic circuits in many digital image processing (DIP) applications are multipliers and adders. A developing technology called approximate computing involves designing power-efficient circuits with less complexity, although at the expense of some accuracy loss. These circuits are appropriate for applications when precise measurements are not necessary. To overcome these challenges a novel approximate TFIE adder, approximate 5:2 compressor, approximate 4:2 compressor, Approximate TFIE Booth Multiplier1 (ATBM1), Approximate TFIE Booth Multiplier2 (ATBM2), Approximate TFIE Booth Multiplier3 (ATBM3) uses logic such as AND, OR, NOT, modified FA, half adder. The proposed Approximate booth multiplication utilises TFIE FA, TFIE 4:2, and TFIE 5:2 and forms three versions of TFIE multipliers (ATBM1, ATBM2, ATBM3) for high-performance and low-power computing. Additionally, the proposed TFIE multiplier for image processing applications provides higher-resolution output images with lower power consumption. A limited amount of accuracy loss can be tolerated in image sharpening and related applications where approximation computing improves performance and energy economy. The total power required for the proposed ATBM1, ATBM2, ATBM3, approximated 4:2 compressor, and 5:2 compressor method is 0.150 mW, 0.105 mW, 0.103 mW, 0.103 mW, and 0.104 mW respectively. Finally, the proposed technique provides superior performance based on area, power, and delay compared with the prior method.
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