Application-specific Instruction Set Processor Design Research Articles

Lightweight ASIP Design for Lattice-Based Post-quantum Cryptography Algorithms

AbstractLattice-based cryptography (LBC) algorithms are considered suitable candidates for post-quantum cryptography (PQC), as they dominate the standardization process put forward by the National Institute of Standards and Technology (NIST). Indeed, three of the four key encapsulation mechanism (KEM) algorithms in the third round of the process are based on computationally hard lattice problems. On the other hand, there is an urgent need for processor designs that can run PQC algorithms efficiently, especially for embedded systems. This study presents an application-specific instruction set processor (ASIP) design for the Kyber, Saber, and NewHope algorithms based on transport triggered architecture (TTA). Custom hardware accelerators are added to the baseline processor architecture for computation-intensive steps without applying any software optimization to the reference code. We compared FPGA and ASIC implementations of our design with the prominent RISC-V cores and instruction set extension studies in the literature. According to the results, the proposed design offers greater efficiency, better performance, and lower resource utilization than its competitors in most cases.

Identification of Research Gaps in an Efficient Designing of Application Specific Instruction Set Processor (ASIP) for Neural Prosthetics

Neural Prosthetics have the potential to help restore motor functionality for patients suffering from a wide range of neurological injuries and disorders. A variety of designs have been used for these systems. In today’s scenario in neuro prosthetics we use Application Specific Instruction Set Processor. By study we thought that it requires improvement so an effective ASIP design can be done for Neural Prosthetics for betterment of life. Many researcher studies have addressed the issue of Neural Prosthetics. In this research work, we develop new kind of algorithm or technique for ASIP so that it can provide an efficient way and flexibility. The proposed work focuses on efficient ASIP design for Neural Prosthetics which is useful for neural prosthetic devices. This method of BMI’s is important for medical deployment of prosthetics. Adaptive filters are used where signals are changing slowly. Filters compensate this condition. It is useful for amputees for physical and mental health. Robotics and biomedical engineering prosthesis reflects complete application of this technology.

Compact and low‐power ASIP design for lightweight PUF‐based authentication protocols

There is a disconnection between the theory and the practice of lightweight physical unclonable function (PUF)-based protocols. At a theoretical level, there exist several PUF-based authentication protocols with unique features and novel efficiency claims, but most of these solutions lack real-world implementations with simple performance figures. On the other hand, practical protocol implementations are ad-hoc designs fixed to a specific functionality and with limited area optimisations. This work aims to bring these approaches on PUF protocols closer. The authors' contribution is twofold. First, they provide a novel ASIP (application-specific instruction set processor) that can efficiently execute PUF-based authentication protocols. The key novelty of the proposed ASIP is optimisation for area without degrading the performance. Second, they demonstrate the capability of their ASIP by mapping three secure PUF-based authentication protocols and benchmark their execution time, memory footprint, communication overhead, and power/energy consumption. Their results demonstrate the advantage of ASIP over dedicated architectures and also as opposed to general-purpose programming on an MSP430. The results further demonstrate various efficiency metrics that can be used to compare PUF-based protocol implementations.

An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics.

Neural coding is an essential process for neuroprosthetic design, in which adaptive filters have been widely utilized. In a practical application, it is needed to switch between different filters, which could be based on continuous observations or point process, when the neuron models, conditions, or system requirements have changed. As candidates of coding chip for neural prostheses, low-power general purpose processors are not computationally efficient especially for large scale neural population coding. Application specific integrated circuits (ASICs) do not have flexibility to switch between different adaptive filters while the cost for design and fabrication is formidable. In this research work, we explore an application specific instruction set processor (ASIP) for adaptive filters in neural decoding activity. The proposed architecture focuses on efficient computation for the most time-consuming matrix/vector operations among commonly used adaptive filters, being able to provide both flexibility and throughput. Evaluation and implementation results are provided to demonstrate that the proposed ASIP design is area-efficient while being competitive to commercial CPUs in computational performance.

CoEx

Application-Specific Instruction Set Processors (ASIPs) provide the adequate performance/efficiency tradeoff for their particular application domain. Nevertheless, their design methodologies have stagnated during the past decade and are still based on a series of manual and time-consuming iterative steps. Furthermore, there exists a productivity gap between the point where an application is given as the target for processor customization and the time a customized architecture is available. Therefore, new tools are required that reduce the number of design iterations and bridge the aforementioned productivity gap. This can be achieved by (1) profiling technologies that, by adapting to the designer’s needs, help to gain insight into application specifications, and (2) prearchitectural design technologies that give early yet accurate feedback on the impact of algorithmic/architectural design decisions. The first requirement is addressed in this article by proposing the multigrained profiling approach, which identifies the profiling needs at each step of ASIP design and lets the designer tailor the level of detail for application inspection. CoEx, a practical implementation of the approach, is also introduced. The second requirement is addressed by creating a prearchitectural estimation engine . This engine couples CoEx reports for an application with an abstract processor model and generates an estimate of the achievable performance. Both CoEx and the performance estimation engine are respectively evaluated for instrumentation-induced execution overhead and accuracy. Finally, the development of an ASIP architecture for an augmented reality computer vision application is presented. The ASIP achieves a gain of six times compared to the original application performance, after being developed in only 2 days.

Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors

This paper presents a systematic approach to the design of application-specific instruction-set processors for high speed computation of local neighborhood functions and intra-field deinterlacing. The intended application is real-time processing of high definition video. The approach aims at an efficient utilization of the available memory bandwidth by fully exploiting the data parallelism inherent to the target algorithm class. An appropriate choice of custom instructions and application-specific registers is used together with a very long instruction word architecture in order to mimic a pipelined systolic array. This leads to a processing speed close to the limit imposed by memory bandwidth constraints. For three intra-field deinterlacing algorithms and 2-D convolution with four kernel sizes, the design approach yields speedup factors between 36 and 1330, Area-Time (AT) product improvements between 12× and 243×, and energy consumption reduction factors between 13 and 262.

A Hardware/Software Cooperative Custom Register Binding Approach for Register Spill Elimination in Application-Specific Instruction Set Processors

Application-Specific Instruction set Processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processor core and high performance and energy efficiency offered by the dedicated hardware extensions. Although a lot of efforts have been devoted to computation acceleration, for example, automatic custom instruction identification and synthesis, limited on-chip data storage elements including the register file and data cache have become a potential performance bottleneck. For custom instructions that have more inputs and/or outputs than the generic register file I/O ports, custom registers are added in ASIPs to satisfy the need of additional inputs and outputs, and traditionally they are used only by custom instructions. In this article, we propose a hardware/software cooperative approach with a linear scan register allocation algorithm, which allows base instructions to utilize the existing custom registers in ASIPs for eliminating register spills of the program. The data traffic between the base processor and off-chip memory can be replaced with energy-efficient on-chip communications between the processor core and custom hardware extensions. Our experimental results demonstrate that a significant performance gain can be achieved, orthogonal to improvements by other techniques in ASIP design.

Comparison between the Simulator and Scheduler based approach of Design Space Exploration for Application Specific Instruction set Processor

An Application Specific Instruction set Processor (ASIP) is a processor designed for a particular application or for a set of applications. An ASIP exploits special characteristics of application(s) to meet the desired performance, cost and power requirements. ASIP Design Space Exploration can be carried out by one of the two popular available techniques as Simulator or Scheduler based approach. This paper is an attempt to survey and compare both the mentioned techniques of design space exploration of ASIP. A list of explored design space parameters using simulator based approach is included in this paper. This paper also highlights few potential parameters which can be explored using the scheduler based approach.

Application Source Codes Profiling for ASIP Memory Subsystem Design

Application Specific Instruction-set Processors (ASIPs) are a realistic solution for domain-specific applications. To reach optimal system-level performance, memory subsystem design is considered in the pre-architecture design stage, which narrows down the huge design space to applications of a specific domain. Source code profiling approach aims to understand the characteristics of applications to guide ASIP design. The memory profiler proposed in the paper uses dynamic profiling technique to generate memory traces, and the live intervals of memory objects are computed by load-store information. Then memory requirement diagram is plotted according to instruction counts. The minimum memory requirement of the application is acquired from the diagram and guides the design of memory subsystem. The profiler is tested using a computing kernel, and the memory subsystem design suggestions are given according to the profiling results.

Pre- and postfabrication architecture exploration for partially reconfigurable VLIW processors

Modern application-specific instruction-set processors (ASIPs) face the daunting task of delivering high performance for a wide range of applications. For enhancing the performance, architectural features, for example, pipelining, VLIW, are often employed in ASIPs, leading to high design complexity. Integrated ASIP design environments, like template-based approaches and language-driven approaches, provide an answer to this growing design complexity. At the same time, increasing hardware design costs have motivated the processor designers to introduce high flexibility in the processor. Flexibility, in its most effective form, can be introduced to the ASIP by coupling a reconfigurable unit to the base processor. Because of its obvious benefits, several reconfigurable ASIPs (rASIPs) have been designed for years. This design paradigm gained momentum with the advent of coarse-grained FPGAs, where the lack of domain-specific performance common in general-purpose FPGAs are largely overcome by choosing application-dependent basic functional units. These rASIP designs lack a generic flow from high-level specification, resulting in intuitive design decisions and hard-to-retarget processor design tools. Although partial, template-based approaches for rASIP design is existent, a clear design methodology especially for the prefabrication architecture exploration is not present. In order to address this issue, a high-level specification and design methodology for partially reconfigurable VLIW processors is proposed in this article. To show the benefit of this approach, a commercial VLIW processor is used as the base architecture and two domains of applications are studied for potential performance gain.

Integrated verification approach during ADL-driven processor design

Nowadays, architecture description languages (ADLs) are getting popular to achieve quick and optimal design convergence during the development of application specific instruction-set processors (ASIPs). Verification, in various stages of such ASIP development, is a major bottleneck hindering widespread acceptance of ADL-based processor design approach. Traditional verification of processors are only applied at register transfer level (RTL) or below. In the context of ADL-based ASIP design, this verification approach is often inconvenient and error-prone, since design and verification are done at different levels of abstraction. In this paper, this problem is addressed by presenting an integrated verification approach during ADL-driven processor design. Our verification flow includes the idea of automatic assertion generation during high-level synthesis and support for automatic test-generation utilizing the ADL-framework for ASIP design. We show the benefit of our approach by trapping errors in a pipelined SPARC-compliant processor architecture and in an application-specific DSP architecture.

Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors

Modern application-specific instruction-set processors (ASIPs) face the daunting task of delivering high performance for a wide range of applications. For enhancing the performance, architectural features, for example, pipelining, VLIW, are often employed in ASIPs, leading to high design complexity. Integrated ASIP design environments, like template-based approaches and language-driven approaches, provide an answer to this growing design complexity. At the same time, increasing hardware design costs have motivated the processor designers to introduce high flexibility in the processor. Flexibility, in its most effective form, can be introduced to the ASIP by coupling a reconfigurable unit to the base processor. Because of its obvious benefits, several reconfigurable ASIPs (rASIPs) have been designed for years. This design paradigm gained momentum with the advent of coarse-grained FPGAs, where the lack of domain-specific performance common in general-purpose FPGAs are largely overcome by choosing application-dependent basic functional units. These rASIP designs lack a generic flow from high-level specification, resulting in intuitive design decisions and hard-to-retarget processor design tools. Although partial, template-based approaches for rASIP design is existent, a clear design methodology especially for the prefabrication architecture exploration is not present. In order to address this issue, a high-level specification and design methodology for partially reconfigurable VLIW processors is proposed in this article. To show the benefit of this approach, a commercial VLIW processor is used as the base architecture and two domains of applications are studied for potential performance gain.

Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design

To improve the computation efficiency of the application specific instruction-set processor (ASIP), a strategy of hardware/software collaborative design is usually utilized. In this process, the autocustomization of specific instruction set has always been a key part to support the automated design of ASIP. The key issue of this problem is how to effectively reduce the huge exponential exploration space in the instruction identification process. To address this issue, we first formulate it as a feasible sub-graph enumeration problem under multiple constraints, and then propose a fast instruction identification algorithm based on a new model called basic convex pattern (BCP). The kernel technique in this algorithm is the transformation from the graph exploration to the formula-based computations. The experimental results have indicated that the proposed algorithm has a distinct reduction in the execution time.

ASIP architecture exploration for efficient IPSec encryption

Application-Specific Instruction-Set Processors (ASIPs) are becoming increasingly popular in the world of customized, application-driven System-on-Chip (SoC) designs. Efficient ASIP design requires an iterative architecture exploration loop---gradual refinement of the processor architecture starting from an initial template. To accomplish this task, design automation tools are used to detect bottlenecks in embedded applications, to implement application-specific processor instructions, and to automatically generate the required software tools (such as instruction-set simulator, C-compiler, assembler, and profiler), as well as to synthesize the hardware. This paper describes an architecture exploration loop for an ASIP coprocessor that implements common encryption functionality used in symmetric block cipher algorithms for internet protocol security (IPSec). The coprocessor is accessed via shared memory and, as a consequence, our approach is easily adaptable to arbitrary main processor architectures. This paper presents the extended version of our case study that has been already published on the SCOPES conference in 2004. In both papers, a MIPS architecture is used as the main processor and Blowfish as encryption algorithm.

ASIP design for partially structured LDPC codes

A new class of partially structured LDPC codes is proposed and their performance evaluated. Part of the parity check matrix has a very regular structure that strongly simplifies implementation; a few randomly distributed ones, supported by a programmable ASIP (application specific instruction set processor), improve error correcting capabilities.

Application specific instruction-set processor template for motion estimation in video applications

The gap between application specific integrated circuits (ASICs) and general-purpose programmable processors in terms of performance, power, cost and flexibility is well known. Application specific instruction-set processors (ASIPs) bridge this gap. In this work, we demonstrate the key benefits of ASIPs for several video applications. One of the most compute- and memory-intensive functions in video processing is motion estimation (ME). The focus of this work is on the design of a ME template, which is useful for several video applications like video encoding, obstacle detection, picturerate up-conversion, 2-D-to-3-D video conversion, etc. An instruction-set suitable for performing a variety of ME functions is developed. The ASIP is based on a very long instruction word (VLIW) processor template and meets low-power and low-cost requirements still providing the flexibility needed for the application domain. The ME ASIP design consumes 27 mW and takes an area of 1.1 mm/sup 2/ in 0.13 /spl mu/m technology performing picturerate up-conversion, for standard definition (CCIR601) resolution at 50 frames per second.

Custom wide counterflow pipelines for high-performance embedded applications

Application-specific instruction set processor (ASIP) design is a promising technique to meet the performance and cost goals of high-performance systems. ASIPs are especially valuable for embedded computing applications (e.g., digital cameras, color printers, cellular phones, etc.) where a small increase in performance and decrease in cost can have a large impact on a product's viability. Sutherland, Sproull, and Molnar originally proposed a processor organization called the counterflow pipeline (CFP) as a general-purpose architecture. We observed that the CFP is appropriate for ASIP design due to its simple and regular structure, local control and communication, and high degree of modularity. We describe a new CFP architecture, called the wide counterflow pipeline (WCFP), that extends the original proposal to be better suited for custom embedded instruction-level parallel processors. This presents a novel and practical application of the CFP to automatic and quick turnaround design of ASIPs. We introduce the WCFP architecture and describe several microarchitecture capabilities needed to get good performance from custom WCFPs. We demonstrate that custom WCFPs have performance that is up to four times better than that of ASIPs based on the CFP. Using an analytic cost model, we show that custom WCFPs do not unduly increase the cost of the original counterflow pipeline architecture, yet they retain the simplicity of the CFP. We also compare custom WCFPs to custom VLIW architectures and demonstrate that the WCFP is performance competitive with traditional VLIWs without requiring complicated global interconnection of functional devices.

A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language

The development of application-specific instruction-set processors (ASIP) is currently the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that building such an architecture is a difficult task that requires expertise in different domains: application software development tools, processor hardware implementation, and system integration and verification. This paper presents a retargetable framework for ASIP design which is based on machine descriptions in the LISA language. From that, software development tools can be generated automatically including high-level language C compiler, assembler, linker, simulator, and debugger frontend. Moreover, for architecture implementation, synthesizable hardware description language code can be derived, which can then be processed by standard synthesis tools. Implementation results for a low-power ASIP for digital video broadcasting terrestrial acquisition and tracking algorithms designed with the presented methodology are given. To show the quality of the generated software development tools, they are compared in speed and functionality with commercially available tools of state-of-the-art digital signal processor and /spl mu/C architectures.

System Level Modeling Methodology of Application Specific Instruction Set Processor (SIP) Using SystemC

In recent years, the development of application specific instruction set processors (ASIP) is the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that constructing such architecture is a difficult assignment that needs skilled knowledge in distinct domains: application software development tools, processor hardware implementation, and system integration and verification. To specify the design and implementation of such systems and incorporate the functionality implemented in both hardware and software forms, we are compelled to move on from traditional Hardware Description Languages (HDLs). Since C and C++ are dominant languages used by chip architects, system engineers and software engineers today, we believe that a C++ based approach to hardware modeling is necessary. This will enable codesign, providing a more natural solution to partitioning fuctionality between hardware and software. In this paper, we discuss a design approach of SystemC (a C++ class library) for ASIP at the system-level which provides necessary features for modeling design hierarchy, concurrency and reactivity in hardware. To exemplify and validate the method we employed it to the design of a 32-bit ASIP for Hindi Text-to-Speech Synthesis developed by CEERI, Pilani (INDIA). Keywords: ASIP; System; System Level Design DOI: http://dx.doi.org/10.3329/diujst.v7i1.9647 Daffodil International University Journal of Science and Technology Vol.7(1) 2012 44-49