Analytical Surface Potential Model Research Articles

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

In this paper, a simple structure for short channel junction-less double gate (JLDG) MOSFET is proposed. Further expression for surface potential of JLDG has been derived using 2D Poisson׳s equation. Based on the proposed analytical model for surface potential distribution along channel thickness and channel length is derived. The proposed junction-less MOSFET has no p-n junction as the doping of channel is same to that of Source/Drain region. The analytical model is compared with numerical solution using ATLAS device simulator. The result shows the variation of channel potential with channel length, channel thickness, doping concentration and applied gate bias. Further, in this paper the analog performance and RF figure of merits (FOMs) have been investigated. The purpose of this research is to provide a physical explanation for improved analog and RF performance exhibited by the device. In this paper major FOMs such as trans-conductance (gm), output conductance (gd), early voltage (VEA), intrinsic gain (AV), trans-conductance generation factor (TGF), cut-off frequency (fT), trans-conductance frequency product (TFP), gain frequency product (GFP), gain trans-conductance frequency product (GTFP) are analyzed. The simulation result shows that the JLDG exhibit a higher trans-conductance, higher cut-off frequency and lower drain conductance.

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

SummaryThis paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.

An Analytical Surface Potential Model Accounting for the Dual-Modulation Effects in Tunnel FETs

In this paper, an analytical model of the channel surface potential in the tunnel field effect transistors (TFETs) is established and verified. The dual-modulation effects in TFETs that the surface potential of the channel is alternatively controlled by the gate bias and drain bias in different operating regimes are emphasized and studied. The transition point corresponding to the switching between the two operating regimes is also analyzed quantitatively. For the first time, a closed-form analytical model of the surface potential in TFETs, including the impacts of both the gate voltage and drain voltage is proposed. Furthermore, a compact current model of the TFET-based on the derived surface potential expression is given. The model predicted tunneling current agree well with the TCAD simulation results in all operating regions of TFETs, which will be helpful for the circuit properties simulation of the TFET.

Compact Analytical Drain Current Model of Gate-All-Around Nanowire Tunneling FET

In this paper, we propose a 2-D analytical model for surface potential and drain current for a long channel p-type gate-all-around nanowire tunneling field effect transistor with a circular cross section. This model includes the effect of drain voltage, gate metal work function, oxide thickness, and radius of the silicon nanowire without assuming a fully depleted channel. The proposed model also includes the effect of the variation in the tunneling volume with the applied gate voltage. The model is tested using 3-D numerical simulations and is found to be accurate for all gate voltages except for subthreshold region.

A Pseudo-2-D-Analytical Model of Dual Material Gate All-Around Nanowire Tunneling FET

In this paper, we have worked out a pseudo two dimensional (2D) analytical model for surface potential and drain current of a long channel p-type Dual Material Gate (DMG) Gate All-Around (GAA) nanowire Tunneling Field Effect Transistor (TFET). The model incorporates the effect of drain voltage, gate metal work functions, thickness of oxide and silicon nanowire radius. The model does not assume a fully depleted channel. With the help of this model we have demonstrated the accumulation of charge at the interface of the two gates. The accuracy of the model is tested using the 3D device simulator Silvaco Atlas.

Deterioration Of Short Channel Effects In Dual Halo Based Triple Material Surrounding Gate (Dh-Tmsg) Mosfet

In the proposed work, the analytical model for Surface potential and Electric field has been carried out in a novel structure named dual halo triple material Surrounding-gate metal-oxide-semiconductor field effect transistor (DHTMSG). The new device has been incorporated with symmetrical dual halo regions near source and drain ends, while the gate terminal consists of three different metals with different work functions. The results prove that the device significantly deteriorates the short channel effects which are studied by analytical model for surface potential and electric field using parabolic approximation method. The analytical results are endorsed by the simulation results.

Compact Analytical Model of Dual Material Gate Tunneling Field-Effect Transistor Using Interband Tunneling and Channel Transport

In this paper, we have developed a 2-D analytical model for surface potential and drain current for a long channel dual material gate (DMG) silicon-on-insulator (SoI) tunneling field-effect transistor (TFET). This model includes the effect of drain voltage, gate metal work function, oxide thickness, and silicon film thickness, without assuming a fully depleted channel. The proposed model also includes the effect of charge accumulation at the interface of the two gates and the variation in the tunneling volume with the applied gate voltage. The accuracy of the model is tested using 2-D numerical simulations. In comparison with the conventional TFET, the proposed model predicts that a DMGTFET provides a higher ON-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ), a better ON-state to OFF-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) ratio, and a better subthreshold slope.

Analytical Surface Potential Model with TCAD Simulation Verification for Evaluation of Surrounding Gate TFET

In this paper, a new two dimensional (2D) analytical modeling and simulation for a surrounding gate tunnel field effect transistor (TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunneling generation rate and thus we numerically extract the tunneling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

Modeling of parameters for nano‐scale surrounding‐gate MOSFET considering quantum mechanical effect

In this paper, an analytical surface potential and threshold voltage model for surrounding gate metal‐oxide semiconductor field‐effect transistor are proposed considering the quantum mechanical effect (QME). Considering variable Fermi potential along the channel, a simple relation between the eigen energies and the potential energy distribution is also provided for the first time. The variation of surface potential and the threshold voltage due to QMEs are computed analytically without using any numerical iteration technique in the model. QME on drain‐induced barrier lowering and threshold voltage roll‐off are also studied to provide a more accurate model. The proposed models are compared with existing surface potential and threshold voltage models and validated by comparing with the simulated results obtained from the 2D device simulator ATLAS of Integrated Systems Engineering Technology Computer Aided Design (ISE TCAD). Very good agreement of our model with TCAD is obtained for a wide variation of device parameters. Hence, the models will aid the designing of practical surrounding gate nano‐wire transistors. Copyright © 2013 John Wiley &amp; Sons, Ltd.

A Compact Model for Dual Material Gate Stack (DUMGAS) Fully Depleted SOI MOSFET

An analytical surface potential model for the Dual Material Gate Stack (DUMGAS) fully depleted SOI MOSFET is developed based on the exact resultant solution of two dimensional Poisson equation. The model includes the effects of drain biases, gate workfunction, different combination length of Gate1 and Gate2, gate oxide thickness, source/drain doping concentration, substrate doping concentration and buried oxide thickness. More attention has been paid on seeking to explain the attributes of the DUMGAS fully depleted SOI MOSFET such as suppressing Drain-induced Barrier Lowering (DIBL), accelerating carrier drift velocity and device speed. The model is verified by comparison to the simulated results using the device simulator MEDICI. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations. The model not only offers the physical insight into device physics but also provides the basic designing guideline for the device.

A compact model for single material double work function gate MOSFET

An analytical surface potential model for the single material double work function gate (SMDWG) MOSFET is developed based on the exact resultant solution of the two-dimensional Poisson equation. The model includes the effects of drain biases, gate oxide thickness, different combinations of S-gate and D-gate length and values of substrate doping concentration. More attention has been paid to seeking to explain the attributes of the SMDWG MOSFET, such as suppressing drain-induced barrier lowering (DIBL), accelerating carrier drift velocity and device speed. The model is verified by comparison to the simulated results using the device simulator MEDICI. The accuracy of the results obtained using our analytical model is verified using numerical simulations. The model not only offers the physical insight into device physics but also provides the basic designing guideline for the device.

Interface traps and quantum size effects on the retention time in nanoscale memory devices

Based on the analysis of Poisson equation, an analytical surface potential model including interface charge density for nanocrystalline (NC) germanium (Ge) memory devices with p-type silicon substrate has been proposed. Thus, the effects of Pb defects at Si(110)/SiO2, Si(111)/SiO2, and Si(100)/SiO2 interfaces on the retention time have been calculated after quantum size effects have been considered. The results show that the interface trap density has a large effect on the electric field across the tunneling oxide layer and leakage current. This letter demonstrates that the retention time firstly increases with the decrease in diameter of NC Ge and then rapidly decreases with the diameter when it is a few nanometers. This implies that the interface defects, its energy distribution, and the NC size should be seriously considered in the aim to improve the retention time from different technological processes. The experimental data reported in the literature support the theoretical expectation.

Modeling of cylindrical surrounding gate MOSFETs including the fringing field effects

A physically based analytical model for surface potential and threshold voltage including the fringing gate capacitances in cylindrical surround gate (CSG) MOSFETs has been developed. Based on this a subthreshold drain current model has also been derived. This model first computes the charge induced in the drain/source region due to the fringing capacitances and considers an effective charge distribution in the cylindrically extended source/drain region for the development of a simple and compact model. The fringing gate capacitances taken into account are outer fringe capacitance, inner fringe capacitance, overlap capacitance, and sidewall capacitance. The model has been verified with the data extracted from 3D TCAD simulations of CSG MOSFETs and was found to be working satisfactorily.

An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET

In this paper, an analytical short-channel threshold voltage model is presented for a dual-metal-gate (DMG) fully depleted recessed source/drain (Re-S/D) SOI MOSFET. For the first time, the advantages of recessed source/drain (Re-S/D) and of dual-metal-gate structure are incorporated simultaneously in a fully depleted SOI MOSFET. The analytical surface potential model at Si-channel/SiO2 interface and Si-channel/buried-oxide (BOX) interface have been developed by solving the 2-D Poisson’s equation in the channel region with appropriate boundary conditions assuming parabolic potential profile in the transverse direction of the channel. Thereupon, a threshold voltage model is derived from the minimum surface potential in the channel. The developed model is analyzed extensively for a variety of device parameters like the oxide and silicon channel thicknesses, thickness of source/drain extension in the BOX, control and screen gate length ratio. The validity of the present 2D analytical model is verified with ATLAS™, a 2D device simulator from SILVACO Inc.

An Analytic Model for Estimating the Length of the Velocity Saturated Region in Double Gate Bilayer Graphene Transistors

An analytical model for surface potential of asymmetric double gate Bilayer Graphene (BLG) transistors is presented on the basis of two‐dimensional Poisson’s equation. To verify the accuracy of potential model, the modelling data are compared with the simulation data of FlexPDE program and a good agreement is observed. From surface potential expression, the device behaviour in velocity saturation region is investigated. As a result, lateral electric field and length of velocity saturation region (Ld) are formulated and their dependence on several device parameters is carefully examined.

Asymmetric halo and symmetric Single‐Halo Dual‐Material Gate and Double‐Halo Dual‐Material Gate n‐MOSFETs characteristic parameter modeling

SUMMARYThis paper presents an analytical subthreshold surface potential model of novel structures called asymmetric pocket‐implanted Double‐Halo Dual‐Material Gate (DHDMG) and Single‐Halo Dual‐Material Gate (SHDMG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which combines the advantages of both the channel engineering (halo) and the gate engineering techniques (dual‐material gate) to effectively suppress the short‐channel effects (SCEs). The model is derived using the pseudo‐2D analysis by applying the Gauss's law to an elementary rectangular box in the channel depletion region, considering the surface potential variation with the channel depletion layer depth. The asymmetric pocket‐implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends. The inner fringing field capacitances are also considered in the model for accurate estimation of the subthreshold surface potential at the two ends of the MOSFET. The same model is used to find the characteristic parameters for dual‐material gate with single‐halo and double‐halo implantations. It is concluded that the DHDMG device structure exhibits better suppression of the SCEs and the threshold voltage roll‐off than a pocket‐implanted and SHDMG MOSFET after investigating the characteristics parameter improvement. In order to validate our model, the modeled expressions have been extensively compared with the simulated characteristics obtained from the 2D device simulator DESSIS. A nice agreement is achieved with a reasonable accuracy over a wide range of device parameter and bias condition. Copyright © 2012 John Wiley &amp; Sons, Ltd.

Analytical V TH and S models for (DMG–GC–stack) surrounding-gate MOSFET

This article presents an analytical model of surface potential, threshold voltage and subthreshold swing for a new structure of surrounding-gate MOSFET by combining dual-material gate, graded channel and gate stack. By comparison with published results, it is shown that the new MOSFET structure can improve the immunity of CMOS-based devices in the nanoscale regime against short-channel effects.

A Unified Analytical One-Dimensional Surface Potential Model for Partially Depleted (PD) and Fully Depleted (FD) SOI MOSFETs

In this work, we present a unified analytical surface potential model, valid for both PD and FD SOI MOSFETs. Our model is based on a simplified one dimensional and purely analytical approach, and builds upon an existing model, proposed by Yu et al. [4], which is one of the most recent compact analytical surface potential models for SOI MOSFETs available in the literature, to improve its accuracy and remove its inconsistencies, thereby adding to its robustness. The model given by Yu et al. [4] fails entirely in modeling the variation of the front surface potential with respect to the changes in the substrate voltage, which has been corrected in our modified model. Also, [4] produces self-inconsistent results due to misinterpretation of the operating mode of an SOI device. The source of this error has been traced in our work and a criterion has been postulated so as to avoid any such error in future. Additionally, a completely new expression relating the front and back surface potentials of an FD SOI film has been proposed in our model, which unlike other models in the literature, takes into account for the first time in analytical one dimensional modeling of SOI MOSFETs, the contribution of the increasing inversion charge concentration in the silicon film, with increasing gate voltage, in the strong inversion region. With this refinement, the maximum percent error of our model in the prediction of the back surface potential of the SOI film amounts to only 3.8% as compared to an error of about 10% produced by the model of Yu et al. [4], both with respect to MEDICI simulation results.

An Analytical Threshold Voltage Model for the Vertical Sidewall Mosfet with a Curved-Channel

We present a new analytical model for surface potential and threshold voltage (Vth) for Single Gate Vertical MOSFET with curved channel. The influence of the corner effect in single gate vertical MOSFET is studied using two dimensional Poisson equation in both planar and spherical geometries. The electric field of the channel in single gate vertical MOSFET and impact on the threshold are studied. The relationship between the threshold voltage (Vth), channel length (L), channel concentration (NA), and the curved corner radius (r0) is given. The comparison with planar devices is provided. The characterization of single gate MOSFETs with curved-channel devices is attributed to the corner effect of the surface potential along the channel. The relationship between the minimum surface potential and the structure parameters is theoretically analyzed. Results confirm that the curved-channel of device gives contribution of the threshold voltage value and the Short Channel Effect (SCE)reduction of the device due to effects of the corner and gate oxide capacitance. These results show a good agreement with the numerical 2-D TCAD simulations. Keywords: Vertical MOSFET, Curved Channel, Analytical Model, Threshold Voltage, Short Channel Effect (SCE), Potential Barrier.

Modelling of parameters for asymmetric halo and symmetric DHDMG n-MOSFETs

This article presents an analytical surface potential, threshold voltage and drain current model for asymmetric pocket-implanted, single-halo dual material gate and double-halo dual material gate (DHDMG) n-MOSFET (MOSFET, metal–oxide–semiconductor field-effect transistor) operating up to 40 nm regime. The model is derived by applying Gauss's law to a rectangular box, covering the entire depletion region. The asymmetric pocket-implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends along with the inner fringing capacitances at both the source and the drain ends and the subthreshold drain and the substrate bias effect. Using the surface potential model, the threshold voltage and drain currents are estimated. The same model is used to find the characteristic parameters for dual-material gate (DMG) with halo implantations and double gate. The characteristic improvement is investigated. It is concluded that the DHDMG device structure exhibits better suppression of the short-channel effect (SCE) and the threshold voltage roll-off than DMG and double-gate MOSFET. The adequacy of the model is verified by comparing with two-dimensional device simulator DESSIS. A very good agreement of our model with DESSIS is obtained proving the validity of our model used in suppressing the SCEs.