Analog-to-digital Converter Structure Research Articles

A High-Resolution Discrete-Time Second-Order ΣΔ ADC with Improved Tolerance to KT/C Noise Using Low Oversampling Ratio.

This work presents a novel ΣΔ analog-to-digital converter (ADC) architecture for a high-resolution sensor interface. The concept is to reduce the effect of kT/C noise generated by the loop filter by placing the gain stage in front of the loop filter. The proposed architecture effectively reduces the kT/C noise power from the loop filter by as much as the squared gain of the added gain stage. The gain stage greatly relaxes the loop filter's sampling capacitor requirements. The target resolution is 20 bit. The sampling frequency is 512 kHz, and the oversampling ratio (OSR) is only 256 for a target resolution. Therefore, the proposed ΔΣ ADC structure allows for high-resolution ADC design in an environment with a limited OSR. The proposed ADC designed in 65 nm CMOS technology operates at supply voltages of 1.2 V and achieves a peak signal-to-noise ratio (SNR) and Schreier Figure of Merit (FoMs) of 117.7 dB and 180.4 dB, respectively.

A 0.012‐mm2 0.244‐pJ/bit successive approximation register analog‐to‐digital converter‐based true random number generator for Internet of Things applications in a 65‐nm complementary metal–oxide–semiconductor

SummaryThis paper proposes a true random number generator (TRNG) based on a successive approximation register (SAR) analog‐to‐digital converter (ADC). A top‐plate sampling SAR ADC structure and a new MSB‐isolation switch scheme (MISS) are combined to achieve low‐power operation and small area occupancy at the same time. When the SAR ADC has completed its conversion, a secondary firing of the comparator measures the remaining signal. This 1‐bit quantized residue serves as the true random sequence, thus eliminating the need for extra circuitry in the TRNG. A 65‐nm prototype of the proposed TRNG was found to occupy an area of 0.012 mm2 and successfully passed all the National Institute of Standards and Technology (NIST) tests without post‐processing. It achieved a figure‐of‐merit of 0.244 pJ/bit for a 1 Mb/s random sequence with a 0.8‐V power supply. Its resilience to power noise injection attacks was also verified.

500 MS/s 4-Bit Flash ADC with Complementary Architecture

This paper proposes a 500 MS/s 4-bit flash analog-to-digital converter (ADC) featuring a differential input voltage range of 1.2 V<sub>pp</sub> operating at a supply voltage of 1.2 V. Although the proposed circuit utilizes a conventional flash ADC structure, its track and hold circuit, driving buffer, and preamp circuits corresponding to the analog stages are designed using complementary architecture to attain a sufficient swing range even at a low supply voltage. Notably, the proposed structure satisfies the error requirements. The error source of the flash ADC, such as the comparator’s input referred offset, did not degrade its performance, while the use of a calibration circuit, characterized by power consumption and area burdens and increased complexity, could also be avoided. Therefore, the proposed flash ADC met the error requirements, such as the comparator’s input referred offset, without the need for calibration circuits. The chip, fabricated using the TSMC 65 nm process, covers an area of 1,160 × 950 μm<sup>2</sup> and consumes 78 mW of power. Furthermore, its signal-to-noise and distortion ratio and spurious-free dynamic range were measured to be 23.36 dB and 30.26 dB, respectively, at a sampling frequency of 500 MHz.

Performance Limits of Generalized Sampling Based 2-Channel Analog-to-Digital Converter

This brief proposes an analog-to-digital converter (ADC) based on Generalized Sampling Theorem and derives a closed form expression of its performance, viz., signal-to-quantization noise ratio (SQNR) and alias-suppression (AS). The ADCs in the 2-channels sample the signal and its filtered version, respectively, at half the Nyquist rate. The outputs of the two ADCs are upsampled by a factor of 2, passed through appropriate reconstruction filters, and then added to give an effective sample-rate which is double that of the sample-rate of each channel ADC. Performance of the proposed ADC has been summarized for simple filters like differentiator, integrator, passive RC low-pass filter, and passive CR high-pass filters. The proposed ADC could therefore be used as an alternative to other popular ADC structures like time-interleaved, frequency-interleaved, and filter-bank ADCs, to achieve high sample-rate with minimal analog circuit overhead.

A low‐power 10‐bit CCP‐based pipelined ADC using a multi‐level variable current source MDAC and an ultra‐low‐power double‐tail dynamic latch

SummaryIn this paper, a low‐power 10‐bit 15‐MS/s opamp‐less pipelined analog‐to‐digital converter (ADC) has been proposed. The circuit is comprised of eight 1.5‐bit/stage MDACs and a 2‐bit backend flash ADC. Each 1.5‐bit/stage structure comprises a CCP‐based MDAC which uses a modified multilevel variable‐current‐source (ML‐VCS) scheme. The modified ML‐VCS CCP structure facilitates its usage in a pipeline ADC structure. Also, the proposed ML‐VCS structure improves the speed behavior as well as the power consumption of a 1.5‐bit/stage CCP‐based MDAC structure. In order to further reduce power consumption, an ultra‐low‐power low‐delay double‐tail dynamic latch has been offered which features high‐speed operation. The suggested ADC is simulated using 180‐nm scaled CMOS technology with a 2‐Vp‐p differential full‐scale input voltage. Hspice simulation results show that the ADC exhibits an SNDR of 60‐dB, an ENOB of 9.67 bits, and the FOM of 0.546 PJ/Conv.step at a Nyquist‐rate input frequency. According to the results, the proposed 10‐bit ADC consumes only 6.7‐mW under a 1.8‐V supply voltage.

Расширение динамического диапазона устройства выборки и хранения весовым интегрированием узкополосного колебания

The most bottleneck of high-frequency digital radio receivers in terms of dynamic characteristics is the process of analog-to-digital conversion. Most often, to meet the requirements for the speed and dynamic range of the analog-to-digital conversion, a sampling and storage device (UHF) is included in front of the analog-to-digital converter (ADC), which is significantly simpler in structure than the ADC structure, but reduces the requirements for its speed and dynamic range [1, 2]. A method for expanding the dynamic range of the integrating sampling and storage device for digital radio receivers using the weight integration of the input narrow-band oscillation is proposed

A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration

A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with a front end of 6-bit Flash ADC with five channels of 6-bit time interleaved synchronous Successive Approximation Register (SAR) ADC. The proposed architecture with a shared 6-bit Flash ADC and time interleaved SAR ADC provides a power and area efficient high speed ADC. The proposed Time-skew calibration is implemented to minimize the discrepancy between the output of Flash ADC and SAR ADC’s channels. To rectify the decision error of the Flash ADC and extract the time-skew information, 1-bit redundancy is included in the CDAC of the SAR conversion. The decision error between the Flash ADC and the SAR ADC is covered with designed redundancy and the mismatch between the ADCs is covered with the time-skew calibration. To reduce the offset mismatch between Flash and SAR ADC and within SAR ADCs, all comparators are calibrated to minimize their absolute offset by utilizing background offset calibration. The modified dynamic strong ARM comparator is used for flash ADC and dynamic latched comparator is used for SAR ADCs. For fine offset calibration and low power consumption, the comparator’s offset calibration circuit is implemented. To reduce the kickback noise and enhance the overall energy efficiency for fast operation of SAR ADCs, rail-to-rail dynamic latch comparator with modified adaptive power control (APC) is implemented. The proposed ADC structure has been implemented in 130 nm CMOS process. The ADC has an effective number of bit (ENOB) of 10.97 bits while consuming 7.08 mW current consumption from the 1.2 V supply voltage.

Performance analysis of mixed‐ADC receiver multiuser massive MIMO relaying system under imperfect CSI

In this paper, the authors investigate a multiuser massive multi-input-multi-output (MIMO) relay system with mixed analog-todigitalconverter (ADC) architecture. It is assumed that the channel state information (CSI) is imperfect between the relay and the user. Sum Spectral efficiency (SE) and Energy efficiency (EE) with the maximum-ratio combining (MRC) detector are derived. In addition, the authors have studied the trade-off between achievable Spectral efficiency and energy efficiency. it is revealed that the trade-off between the sum SE and EE with respect to key system parameters, including number of BS antennas, user transmit power, the power of the CSI error, and the quantization bits. Finally, numerical results show that the mixed-ADC structure can obtain a better energy-rate trade-off than low-precision ADC structure.

On the performance of double resolution ADC receivers for massive MIMO relaying systems

High power consumption and hardware cost are the two challenges for practical massive MIMO systems. One promising solution is to employ low resolution analog to digital converter (ADC). In this paper, massive MIMO relaying systems are investigated with double resolution ADCs at base station receiver, where some antennas are connected to low resolution ADCs, while the rest of the antennas are connected to high resolution ADCs. Closed form expression for uplink spectral efficiency (SE) is derived using the maximum ratio combining receiver assuming perfect channel state information. Some asymptotic analysis is discussed to explore the effects of system parameters on SE such as; the number of receive antennas, ADC quantization bits, user transmit power and the rate of high precision ADC in double resolution ADC structure. Moreover, energy efficiency with some system parameters is studied. It is shown that the performance wastage owing to low precision ADCs can be recompensed by growing the number of receive antennas $$ \varvec{N} $$, following a logarithmic scaling law instead of increasing the transmit power at both of source and relay. The double resolution ADCs can achieve a better tradeoff between power consumption and SE when using 4 quantization bits. By using only around 30 antennas, the double resolution ADCs achieves its optimal energy efficiency for selecting system parameters.

Spectral‐Energy Efficiency Tradeoff in Mixed‐ADC Massive MIMO Uplink with Imperfect CSI

An uplink multi-user massive Multi-input multi-output (MIMO) system is considered with a mixed Analog-to-digital converter (ADC) architecture under imperfect Channel state information (CSI). A closed-form approximation for the Spectral efficiency (SE) is derived for a general mixed ADC structure with any resolution profile. To achieve a balance between the SE and receive Energy efficiency (EE) of the system, the ADC resolution profile optimization problem that maximizes a linear combination of the SE and the Base station (BS) receive power consumption is formulated. An algorithm based on gradient search is proposed whose complexity is linear in the number of BS antennas. Numerical results verify that the proposed ADC resolution design largely outperforms the two-level structure especially in the lower SE region and provides more choices than the uniform-ADC architecture for resolving the SE-EE tradeoff.

A 10- and 12-Bit Multi-Channel Hybrid Type Successive Approximation Register Analog-to-Digital Converter for Wireless Power Transfer System

This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) designed for a wireless power transfer system. This is a four–channel SAR ADC structure with 10-bit resolution for each channel, which can also be applied as a single 12-bit ADC. To reduce the area and the number of the required devices in the ADC module, a hybrid-type structure with capacitor and resistor DACs is applied, in which the resistor DAC is shared between channels and determines the seven least significant bits (LSB)s, while the capacitor DAC determines the three most significant bits (MSBs). For the 12-bit operation mode, and to reduce the number of capacitors required in the capacitor DAC, the capacitors of the four channels are shared to determine the five MSBs. A foreground calibration is applied to the capacitor DAC to remedy the gain and offset errors after fabrication. An additional low resistive path is also implemented in the resistor DAC for error correction. The conversion speed for 10- and 12-bit operations reaches up to 1 and 0.5 MS/s, respectively. The prototype ADC is designed in a 180 nm complementary metal-oxide semiconductor (CMOS) process. For 10- and 12-bit operating modes, this ADC module achieves up to 9.71 and 11.76 effective number of bits (ENOBs), respectively.

Outage Probability Analysis and Resolution Profile Design for Massive MIMO Uplink With Mixed-ADC

This paper analyzes the outage probability for the uplink of multi-user massive multi-input-multi-output systems with a mixed analog-to-digital converter (ADC) architecture, in which the base station (BS) is equipped with ADCs of different resolution levels. Maximum-ratio combining (MRC) is used at the BS. By deriving the distribution of the user-interference power and statistical properties of other components in the signal-to-interference-plus-noise-ratio (SINR), a tight closed-form approximation for the outage probability is obtained for a general mixed ADC structure with any resolution profile. Then, two methods for the ADC resolution profile optimization are proposed considering both the outage probability and the BS energy consumption. The first method uses low-complexity incremental search to minimize the BS energy consumption for given outage probability constraint. The other method is based on multi-objective optimization and adopts a discrete-variation of the classic non-dominated sorting genetic algorithm II (NSGA-II). Numerical results are presented to validate the outage probability results. Furthermore, it is shown that the two proposed mixed-resolution ADC designs largely outperform a two-level ADC structure and provide more choices than the uniform ADC structure for resolving the tradeoff between outage probability and BS energy consumption.

Evaluation of Room-Temperature Performance of Ultra-Small Single-Electron Transistor-Based Analog-to-Digital Convertors

In this paper, in order to analyze the performance of single-electron transistor (SET)-based analog-to-digital converter (ADC) circuits at room temperature, first, the quantum Coulomb blockade regime is explained and based on it we calculate and discuss the inherent Coulomb oscillation characteristics of room-temperature-operating SETs (or, in other words, ultra-small SETs). Then, to explain the performance of SET-based ADC structures, we explore the sensitivity of converter section of these structures to the inherent periodic oscillation characteristics. By simulating two different temperatures of 100[Formula: see text]K and 300[Formula: see text]K, we demonstrate that for proper performance of converter section of the SET-based ADCs, SETs must have inherent Coulomb oscillations with the same and high peak-to-valley current ratio (PVCR) and equal Coulomb peak spacing (i.e., equal [Formula: see text]. The Coulomb oscillation characteristics of the room-temperature-operating silicon SET show the Coulomb oscillations with unequal PVCRs and unequal Coulomb peak spacings (i.e., unequal [Formula: see text]. As a result, it can be seen that the room-temperature-operating SET-based ADCs never have a suitable output.

Receiver Energy Efficiency and Resolution Profile Design for Massive MIMO Uplink With Mixed ADC

This paper considers the uplink of multiuser massive multi-input multi-output systems with a mixed analog-to-digital converter (ADC) architecture, in which the base station (BS) is equipped with ADCs of different resolution levels. While higher resolution, ADCs reduce the quantization error to improve the performance; they also incur higher energy. This paper studies the receive energy efficiency (EE) and the ADC resolution profile design under the maximum-ratio combining receiver. First, closed-form approximations for the spectral efficiency (SE) and receive EE are derived for a general mixed ADC structure. Then, the ADC resolution profile optimization problem that maximizes the receive EE with respect to SE requirement is formulated. An algorithm based on decremental searching and dynamic programming is proposed whose complexity is linear in the number of BS antennas. Numerical results verify that with the proposed design, the mixed-ADC receiver can have nearly the same SE performance as the all full-resolution one but with considerably lighter burden of energy consumption.

A taxonomy of ADC architectures for ICT engineering curricula

This paper presents the various Analog to Digital Converter (ADC) architectures within a structured frame in order to outline the basic design choices and to point out some additional degrees of freedom beyond the classic ADC circuits. The parameters for a detailed analysis of performance, speed, precision, costs are identified and discussed. Within this frame, the paper identifies variations to the classic ADC structures, which provide additional speed/cost tradeoffs. The aim is to provide students an understanding of various ADC techniques, allowing a motivated choice of the most suitable structure for each specific application at the systems design level. This approach has been used in teaching ADCs for several years, and the paper includes a discussion of results and student feedback.

A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs

A digital background calibration technique based on the concept of split analog-to-digital converter (ADC) structure is proposed for pipelined ADCs to correct the gain error induced by the capacitors mismatch and finite dc gain of the residue amplifiers and nonlinearity of the residue amplifiers. In the proposed technique, one of the channels in split ADC structure is virtually implemented by using two extra comparators in each ADC’s stage and an interpolation filter to eliminate the mismatch between channels. Several circuit-level simulation results in the context of a 12-bit 100-MS/s pipelined ADC are provided to verify the usefulness of the proposed calibration technique. The simulation results show 51-dB signal-to-noise and distortion ratio and 65-dB spurious free dynamic range improvement, respectively, in comparison with the noncalibrated ADC.

Low-Power and Compact Analog-to-Digital Converter Using Spintronic Racetrack Memory Devices

Current-induced domain wall (DW) motion in spintronic racetrack memory promises energy-efficient analog computation using compact magnetic nanowires. This paper explores the feasibility of analog-to-digital converter (ADC) based on current-induced DW motion and introduces an n-bit ADC using n racetrack magnetic nanowires. With each magnetic nanowire having a different configuration granularity, an n-bit binary or gray code is generated simultaneously. The proposed ADC structure achieves 21 fJ/conversion-step at 20 MHz with an area of about $10~\mu \text{m}^{2}$ . The racetrack ADC is suitable for applications requiring dense ADC arrays, such as image sensors. This paper describes one ultrahigh speed digital pixel sensor imaging system benefiting from the racetrack ADC.

An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS

This paper presents an 11 bit 450 MS/s three-way time-interleaved (TI) subranging pipelined-successive approximation register (SAR) analog-to-digital converter (ADC). The proposed hybrid architecture combines the design benefits of different ADC structures to achieve a high conversion rate and accuracy with good power efficiency. The design employs multiple offset calibration schemes to compensate the offset mismatches at each stage. The solutions require less calibration efforts, thus allowing the ADC to achieve a compact area. Furthermore, a dynamic SAR controller embedded with error-decision-correction (EDC) logic is proposed to reduce large transition error. Measurement results on a 65 nm CMOS prototype operated at 450 MS/s and 1.2 V supply show 7.4 mW total power consumption with a peak signal-to-noise distortion ratio (SNDR) of 60.8 dB and an FOM of 32 fJ/conv.step at Nyquist.

A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

The use of VCO-based quantization within continuous-time (CT) SigmaDelta analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 mum CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth while consuming 40 mW from a 1.2 V supply and occupying an active area of 640 mum times 660 mum. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which achieves first-order noise shaping of its quantization noise. The quantizer structure allows the second-order CT SigmaDelta ADC topology to achieve third-order noise shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching of the DAC elements.

A high-frequency double-sampling second-order /spl Delta//spl Sigma/ modulator

As the minimum feature size of VLSI technologies scales down, more of the signal processing tasks are performed in the digital domain. This results in increased speed, resolution, and dynamic range requirements for the analog-to-digital converter (ADC). High-speed and high-accuracy designs can be achieved by using oversampling ADC structures, which demand amplifiers with a high gain and a high unity-gain frequency. Due to the difficulty to meet both of these specifications, the ADC resolution at a frequency in the megahertz range appears to be limited by amplifier settling requirements. Design techniques to improve the ADC performance are presented. The proposed modulator structure uses the double-sampled technique, which increases by a factor of two the maximum speed of operation and correctly operates even with low dc gain amplifiers. Furthermore, the signal-to-noise ratio is significantly improved by a calibration stage, which dynamically estimates the offset errors to be removed by a simple subtraction from the output signal.