Analog Delay Line Research Articles

A low-cost digital delay line for bat biosonar research

Bat biosonar research and bat neuroscience as a whole relies heavily on experiments to determine bat responses to various stimuli. Typically, these are presented to the bat using real world targets such prey insects, but also via artificial stimuli using an ultrasonic loudspeaker. One key component of artificial target creation is the use of delay lines. Analog delay lines have been used for decades to generate artificial targets at programmable ranges. More recently, digital delay lines have become the norm. This talk will present the details of the development of a very low-cost digital delay line that can produce bat echoes with up to three glints. The main delay between the bat and the target as well as the inter-glint spacing are programmable with delays as small as 5 μ s possible. The platform used is a commonly available SAMD51 microcontroller with a total system cost under $50. The talk will present experimental results, code development using commonly available programming tools, and schematics for an add-on board that uses microphone or general differential inputs. Finally, the talk will introduce an approach implement wideband Doppler shift (time-scaling) of digitally delayed echoes using direct memory access tools native to the SAMD51 microcontroller.

A Time-Domain Binary CNN Engine With Error-Detection-Based Resilience in 28nm CMOS

Due to the increasing demand of high energy-efficient processor for deep neural networks, traditional neural network engines with high-precision weights and activations that usually occupies huge on/off-chip resources with large power consumption are no longer suitable for Internet-of-Things applications. Binary neural networks (BNNs) reduce memory size and computation complexity, achieving drastically increased energy efficiency. In this brief, an energy-efficient time-domain binary neural network engine is optimized for image recognition, with time-domain accumulation (TD-MAC), timing error detection based adaptive voltage scaling design and the related approximate computing. The proposed key features are: 1) an error-tolerant adaptive voltage scaling system with TD-MAC chain truncation for aggressive power reduction, working from near-threshold to normal voltage; 2) architectural parallelism and data reuse with 100% TD-MAC utilization; 3) low power TD-MAC based on analog delay lines. Fabricated in a 28nm CMOS process, the whole system achieves a maximum 51.5TOPS/W energy efficiency at 0.42V and 25MHz, with 99.6% accuracy on MNIST dataset. When the length of the TD-MAC chain is truncated by configuration, with a 90% accuracy on MNIST and a 150MHz, the proposed BNN achieves a power-saving of 13.2% and a further energy efficiency increasing of 67.6%.

Beamforming Algorithm Architectures for Medical Ultrasound

Medical ultrasound scanners are amongst the most sophisticated signal processing machines in use today. The Beamformer is the brain of whole signal processing system of the scanner [1]. Beamforming allows message transmission or reception to be directed or spatially selective. It is used in receiving beamforming to concentrate the noise signals obtained in the region of concern as reflections from various tissue structures. This paper reviews the various receive beamformer architectures implemented in FPGA/ASIC for ultrasound imaging. Most of the receive beamformers are implemented using the standard technique Delay and Sum. Beamforming in ultrasound instruments for medical imaging has traditionally been implemented using analog delay lines. The concept of dynamic focusing in near field has resulted more complex analog delay structures and were replaced by digital structures. By the availability of high-speed analog to digital converters, and VLSI Technology improvements have now made real time implementation of digital beamformers feasible. The current innovations involve hybrid beamformers utilizing the pros of both analog and digital structures. This paper discusses the evolution of beamforming architectures from analog to digital environment and the current beamformer designs. The changes in beamformer designs in order to be compatible to high frequency probes and yield improved imaging performance, resource optimization, etc. are discussed.

A Low-Power Analog Delay Line Using a Current-Splitting Method for 3-D Ultrasound Imaging Systems

We propose an analog delay line (ADL) that adopts a current-splitting method (CSM) to reduce power consumption. The proposed ADL employs a pipelined sample-and-hold architecture and includes a buffer in the analog memory cell to prevent a charge sharing problem. The CSM reduces power consumption without distorting the sampled data by dividing the current source of the buffer into a holding current source and a buffering current source, which are, respectively, located inside and outside of the analog memory cell. The simulated power consumption of the proposed ADL without and with the CSM is 1080 and $90~{\mu }\text{W}$ , respectively, indicating that the CSM reduces power consumption by 91.7%. The proposed ADL was fabricated using a 0.18- ${\mu }\text{m}$ CMOS process with a 1.8-V supply voltage and occupies an active area of $120 \times 140~{ \mu }\text{m}^{ 2}$ . The sampling capacitor in the analog memory cell was implemented with MOS capacitors instead of metal-insulator-metal capacitors, resulting in an area per unit delay of the proposed ADL of only $600~{ \mu }\text{m}^{ 2}$ , which is much smaller than that in prior works. The measurement results show that the delay of the proposed ADL is accurately controlled from 25 to 475 ns with a unit delay step of 25 ns at a sampling frequency of 40 MHz.

A simple delay-line 4-PPM demodulator with near-optimum performance

We describe a simple 4-PPM demodulator that uses analog delay lines and simple 1-bit comparators to determine the least-significant bit and most-significant bit of the 4-PPM encoded data without additional digital signal processing. We show that with good optical filtering the comparator-based demodulator can theoretically operate with sensitivity only 0.23 dB from the optimum 4-ary receiver. We describe as an example of this approach the demodulator built for the Lunar Laser Communication Demonstration and show measured performance within 1.1 dB of the expected sensitivity. The technique is extendable to higher-order, and higher-symbol-rate orthogonal modulation formats.

Compact self-powered CMOS strain-rate monitoring circuit for piezoelectric energy scavengers

Self-powered sensing refers to an energy scavenging approach where the power for sensing, computation and storage is harvested directly from the signal being sensed. Presented is a 16-transistor CMOS circuit that can be used for the self-powered sensing of strain-rates using signals produced by piezoelectric energy scavengers. By exploiting operational primitives inherent in impact-ionised hot-electron injection on a floating-gate transistor, the proposed circuit achieves computation and non-volatile storage of signal-rate statistics without the aid of batteries, intermediate energy storage, power regulation or analogue-to-digital conversion. By using a diode based analogue delay-line, the proposed circuit computes and stores the number of times the signal-rate (strain-rate) exceeds a threshold which can be programmed from 0.6 to 12 V/s. The circuit occupies 500×340 µm of silicon when prototyped in a 0.5 µm CMOS technology and measured results demonstrate power dissipation less than 200nW, which is ideal for self-powered sensing applications.

A compressed sensing receiver for UWB impulse radio in bursty applications like wireless sensor networks

We propose a novel receiver for Ultra-Wide-band Impulse-Radio communication in Wireless Sensor Networks, which are characterized by bursty traffic and severe power constraints. The receiver is based on the principle of Compressed Sensing, and exploits the sparsity of the transmitted signal to achieve reliable demodulation from a relatively small number of projections. The projections are implemented in an analog front-end as correlations with tractable test-functions, and a joint decoding of the time of arrival and the data bits is done by a DSP back-end using an efficient quadratic program. The proposed receiver differs from extant schemes in the following respects: (i) It needs neither a high-rate analog-to-digital converter nor wide-band analog delay lines, and can operate in a significantly under-sampled regime. (ii) It is robust to large timing uncertainty and hence the transmitter need not waster power on explicit training headers for timing synchronization. (iii) It can operate in a regime of heavy inter-symbol interference (ISI), and therefore allows a very high baud rate (close to the Nyquist rate). (iv) It has a built-in capability to blindly acquire and track the channel response irrespective of line-of-sight/non-line-of-sight conditions. We demonstrate that the receiver’s performance remains close to the maximum likelihood receiver under every scenario of under-sampling, timing uncertainty, ISI, and channel delay spread.

A Low-Power Integrated Circuit for Interaural Time Delay Estimation Without Delay Lines

A low-power IC for the estimation of the delay between two infinitely clipped (digital) signals is designed and implemented in a 0.35-mum standard CMOS technology. The proposed circuit is based on a sliding-mode control system and does not need past values of the inputs, which are usually stored using chains of digital registers or analog delay lines and significantly increase the power consumption. The IC is intended to work in ultralow-power miniature sensor network nodes performing localization in the audio range [20, 1000] Hz, as part of a forest environmental protection network. Power dissipation results show a core power consumption of 1.04 muW at 3.3 V and only 282 nW at 1.8 V-in both cases with a clock frequency of 200 kHz. The circuit is fully operative and was successfully tested on field as part of a low-power bearing sensor unit.

Monobit digital Eigen-based receiver for transmitted-reference UWB communications

Transmitted-reference impulse radio (TR-IR) is a low complexity UWB system which is suitable for highly dispersive multipath channel. However, TR-IR requires a wideband analog delay line which has high complexity and high energy consumption. In this letter, we propose a digital eigen-based (EB) receiver which first converts the analog signal to digital signal and then demodulates the received signal in digital domain. Computer simulation results show that the proposed receiver can outperform the conventional autocorrelation receiver. We also proposed a monobit digital EB (MEB) receiver as a low complexity alternative to the EB receiver. The bit-error-rate performance of MEB receiver have also been studied theoretically to show the quantization effect in this letter.

Code-multiplexed UWB transmitted-reference radio

In traditional transmitted reference (TR) ultrawideband systems the reference component is time-shifted and orthogonal relative to the data-bearing signal. This paves the way to a correlation receiver in which the local template is derived from the incoming waveform using a delay line. As analog delay lines are difficult to implement with current technology, an alternative TR system has recently been proposed in which reference and data components are made orthogonal by a frequency shift rather than a time shift. The resulting receiver has no delay lines and has better performance compared to the traditional scheme. In the present paper we discuss a third way to achieve orthogonality, i.e., by modulating reference and data components with two distinct code sequences. Even in this case the receiver has no delay lines. However, it is simpler to implement and has better performance than the frequency-shift based receiver.

Transmitted-Reference Impulse Radio Systems Based on Selective Combining

Transmitted-reference impulse radio with autocorrelation receiver (TR-IR/AcR) generally requires wideband analog delay line (WADL) with length of several tens nanoseconds. To maximally reduce the length, we propose a TR-IR system based on selective combining, which intelligently selects integration regions for symbol detection. It was shown that when the WADL with a total length of 8 ns is employed, the proposed system has a signal-to-noise ratio gain of 0.5 dB, 2.3 dB, 2,.3 dB and 3.7 dB over the TR-IR/AcR at bit-error-rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> for ultra-wideband channel models CM 1 ~ 4, respectively.

A CMOS Hard-Decision Analog Convolutional Decoder Employing the MFDA for Low-Power Applications

The use of analog circuits to reduce the size and power consumption of channel decoders such as Viterbi decoders has been an active area of research over the recent years. However, the need for digital memory to store the history of the path elimination decisions in a Viterbi decoder, limits the potential advantages that could be offered by an all-analog convolutional decoder implementation. This is especially so in cases where the use of an older silicon process technology is dictated by the application; hence, the power-reduction benefits offered by deep sub-micrometer digital designs cannot be exploited. A novel alternative convolutional decoding method which allows for an entirely analog implementation is the modified feedback decoding algorithm (MFDA). This paper describes the first integrated realization of a convolutional decoder employing the MFDA. The rate-1/2, constraint-length-3 decoder, employs a current-mode analog signal processing core and was fabricated in a 0.6-mum CMOS process technology, occupying an area of 0.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Measured results show that decoding speeds in excess of 1-Mb/s are possible with virtually no loss in coding gain. Total power consumption is 2.45 mW from a single 3-V supply. Although a hard-decision decoder, conversion to soft-decision decoding requires only the inclusion of a simple analog delay line as shown in the paper. The decoder is dedicated to an implantable biotelemetry system, but it can also find use in other low-power applications. System-level coding simulations are also presented which are useful for the construction of larger decoders where the benefits of the MFDA approach would be more pronounced.

FPGA implementation of a delay-line readout system for a particle detector

We describe a novel Time to Digital Conversion (TDC) architecture implemented in an FPGA (Field Programmable Gate Array). FPGA technology was employed due to its development flexibility and low cost. The various concepts investigated and tested are application specific. An FPGA is used to measure and code the time difference between two input pulses. The time measurement incorporated floorplanning and the manual placing of propagation delay elements (delay chains) inside the chip to mimic a real passive delay-line. Tests employing simulated passive analogue delay-line circuits and results using real passive delay-lines have produced very encouraging results. Pending some more testing this design practice will be used for a space instrumentation application due for launch in 2006.

A virtual clock enhancement method for DDS using an analog delay line

In this paper, we describe an analog delay line (DL) used for virtual clock enhancement in a direct digital synthesis (DDS). The novelty of the proposed method is the immediate application of the output signal of the phase accumulator for the generation of the desired frequency. To obtain the necessary spectral purity of the generated frequency, additional digital signal processing (DSP) based on a delay-locked loop (DLL) and noise shaping is applied. The consequences of nonlinear effects within the DL for the spectral performance of the DDS are explained.

A Low-Power 100 MHz Analog FIR Filter for PRML Equalization

This paper presents design of a low-power 100 MHz analog FIR filter for PRML equalization used in the read channel of hard disk drives. The chip consists of 16 channels to provide 15-tap FIR filter operation. By using rotating clocks for sample/hold operation with one dummy channel, timing constraints can be relieved, which results in low-power consumption. The chip incorporates the parallel array of sample-and-hold amplifiers for analog delay line. The sample-and-hold amplifier includes the open-loop unity-gain amplifier with gain-control circuit using replica-biasing scheme, which also improves uniformity among amplifiers. It was fabricated in a 0.8-mm CMOS technology and consumes power of 200 mW for \pm 1.65 V power supply voltage.

Noise Analysis of Switched-Current Circuits

The understanding of noise in analog sampled data systems is vital for the design of high resolution circuitry in the discrete time domain. In this paper a general description of sampled and held noise is presened. The noise calculations are verified by measurements on an analog delay line implemented using switched-current (SI) technique. The SI delay line is based on a new topology current copier (CCOP). For the verification of the theory a new measurement technique is used. This technique enables one to measure the power spectral density of sampled and held noise which is below the continuous time noise floor.

Beam test of a prototype readout system for precision tracking detectors at LHC

A prototype of a readout system developed for high spatial precision tracking detectors at LHC has been tested in a beam at CERN. It is based on a radiation hard CMOS front-end chip which includes signal amplification, storage in an analogue delay line and a deconvolution filter. Data were transferred from the front-end chip using an analogue fibre optic link employing a novel reflective electro-optic modulator and continuous laser light source remote from the detector. This is the first time such a system has been used in an experimental environment and is the basis of the system proposed for the CMS experiment at LHC.

High-density and high-quality frame transfer CCD imager with very low smear, low dark current, and very high blue sensitivity

When the channel width of an FET becomes of the same order of magnitude as the depth of the gate depletion region, an increase of the threshold voltage is observed. This narrow channel effect has been applied successfully in creating an asymmetric potential well under an electrode for two-phase CCD operation. The feasibility of this structure has been confirmed in a 242-element analog delay line. The application is now extended to a 800 H/spl times/492 V frame transfer-type buried channel CCD imager with 14.31818 MHz frame shift, which results in a very low smear level of 0.01%, which is good enough for low-cost multimedia video camera applications.

Dispersion compensation for 10 Gb/s lightwave systems based on a semiconductor Mach-Zehnder modulator

For 10 Gb/s lightwave systems based on a semiconductor Mach-Zehnder modulator, the following dispersion compensating schemes are examined theoretically; asymmetry in the splitting ratio of the modulator input Y-branch waveguide, linear equalization using an analog delay line equalizer, dispersion compensating fiber, and direct prechirping for NRZ signals. It is shown that the combination of an asymmetric input Y-branch waveguide push-pull operation of the optical modulator, and dispersion compensating fiber offers the best dispersion limited transmission performance. With dispersion compensating fiber, a larger portion of the optical power is applied to the arm of the modulator with more absorption, whereas without dispersion compensating fiber. A larger portion of the optical power is applied to the arm of the modulator with less absorption.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Multiple delay line shaping: a new class of weighting functions suitable for digital signal processing

We introduce a whole class of weighting functions, that can be implemented with an analog prefilter, an analog-to-digital converter and a FIR or IIR digital filter. These weighting functions feature a finite duration and can have a flat top within less than 1%. General rules are given about the design of such general class of filters. The shape of the obtained weighting function is strictly related to the chosen prefilter, and its duration may be effectively shrinked by the digital processing. However the number of samples required in order to keep a finite duration of the weighting function is shown to increase with the complexity of the prefilter. The developed class of weighting functions can be alternatively implemented with analog delay lines or switched-capacitor filters.