Analog Amplifier Research Articles

All-optical XOR, NOR, and NAND logic functions with parallel semiconductor optical amplifier-based Mach-Zehnder interferometer modules

The performance of XOR, NOR, and NAND functions implemented all-optically (AO) using two parallel semiconductor optical amplifier (SOA)-based Mach-Zehnder interferometers is simulated and investigated. The dependence of the quality factor on key input signals and SOAs parameters is investigated and assessed. The obtained results show that the target AO Boolean functions can simultaneously be realized with the employed scheme with both logical correctness and high quality at 80 Gb/s.

A nullor approach to the design of analog circuits for a desirable performance

A method for the performance design of analog amplifier circuits based on nullors is discussed. It covers the design of AC parameters of the amplifier viz. input and output resistance, gain and bandwidth. Fixator-norator pair, which is a combination of nullor and sources, is the key element in this method. The complete performance design is considered as a two step process. Fixator-norator pair along with the linear equivalent model of the target circuit together does the first step, which is the design for input and output resistance and gain. The second step performs the design for bandwidth, i.e., mainly the cut-off frequencies. This is based on Bode plot analysis, which requires a reference circuit having the same frequency response as that of the desired one. The reference circuit is required only for simulation and it can be removed after the final design is met. Four examples are worked out for better understanding of the method.

Photon-Number-Resolving Transition-Edge Sensors for the Metrology of Quantum Light Sources

Low-temperature photon-number-resolving detectors allow for direct access to the photon number distribution of quantum light sources and can thus be exploited to explore the photon statistics, e.g., solid-state-based non-classical light sources. In this work, we report on the setup and calibration of a detection system based on fiber-coupled tungsten transition-edge sensors (W-TESs). Our stand-alone system comprises two W-TESs, read out by two 2-stage-SQUID current sensors, operated in a compact detector unit that is integrated in an adiabatic demagnetization refrigerator. Fast low-noise analog amplifiers and digitizers are used for signal acquisition. The detection efficiency of the single-mode fiber-coupled detector system in the spectral region of interest (850–950 nm) is determined to be larger than 87 %. The presented detector system opens up new routes in the characterization of quantum light sources for quantum information, quantum-enhanced sensing and quantum metrology.

Efficient two-stage dual-beam noncollinear optical parametric amplifier

We have constructed a noncollinear optical parametric amplifier with two signal beams amplified in the same nonlinear crystal. This dual-beam design is more energy-efficient than operating two amplifiers in parallel. The cross-talk between two beams has been characterized and discussed. We have also added a second amplification stage to enhance the output of one of the arms, which is then frequency-doubled for ultraviolet generation. This single device provides two tunable sources for ultrafast spectroscopy in the ultraviolet and visible region.

Parallel RF Power Amplifiers Temperature Monitoring System Based on FPGA Device

The paper describes FPGA based temperature measurement system, for parallel monitoring of temperatures of the power semiconductors devices in RF power amplifiers. Proposed system allows for fast detection of the asymmetry in parallel RF power amplifier caused by failure of a single semiconductor power device like CMOS or MOSFET high power transistor. This information is important for evaluation of the system efficiency, current flow symmetry, and allowable output power in a given RF amplifier configuration. The article presents original concept of reading measurements from many 1-wire temperature sensors with minimal time delay between individual measurements thanks to digital temperature sensors operating on separate serial 1-Wire buses. FPGA device collects data from the temperature sensors and sends them through wireless interface to a remote terminal. The structure of the system as well as particular devices are described in the paper. The paper also presents selected results of practical experiments performed to confirm that the assumed concept of using an FPGA device to perform the high simultaneous readings from many sensors is feasible.

CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detectors based on CMOS technology. Such detectors can provide charge collection, analog amplification and digital processing in the same silicon wafer. The radiation hardness is improved thanks to multiple nested wells which give the embedded CMOS electronics sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC . A number of alternative solutions have been explored and characterised. In this document, test results of the sensors fabricated in different CMOS processes are reported.

Development of a 32-channel ASIC for an X-ray APD detector onboard the ISS

We report on the design and performance of a mixed-signal application specific integrated circuit (ASIC) dedicated to avalanche photodiodes (APDs) in order to detect hard X-ray emissions in a wide energy band onboard the International Space Station. To realize wide-band detection from 20 keV to 1 MeV, we use Ce:GAGG scintillators, each coupled to an APD, with low-noise front-end electronics capable of achieving a minimum energy detection threshold of 20 keV. The developed ASIC has the ability to read out 32-channel APD signals using 0.35 μm CMOS technology, and an analog amplifier at the input stage is designed to suppress the capacitive noise primarily arising from the large detector capacitance of the APDs. The ASIC achieves a performance of 2099 e− + 1.5 e−/pF at root mean square (RMS) with a wide 300 fC dynamic range. Coupling a reverse-type APD with a Ce:GAGG scintillator, we obtain an energy resolution of 6.7% (FWHM) at 662 keV and a minimum detectable energy of 20 keV at room temperature (20 °C). Furthermore, we examine the radiation tolerance for space applications by using a 90 MeV proton beam, confirming that the ASIC is free of single-event effects and can operate properly without serious degradation in analog and digital processing.

Automated sizing of low-noise CMOS analog amplifier using ALCPSO optimization algorithm

The main aim of the automated design methodology is to improve the design process in terms of cost, robustness and performance. Presence of noise restricts the minimum level of signal that a circuit can processed with an acceptable quality which increases the complexity of the circuit. Optimization is a time consuming and difficult tasks that involves handling wide variety of conflicting constraints or design specifications and wide range of design parameters. In this paper, Particle Swarm Optimization with an Aging Leader and challengers (ALCPSO)-based design methodology is proposed. ALCPSO is used to search the solution space for computing the constraints and design parameters with main aim of simultaneously minimizing the thermal noise and area of the circuit. In other word, the proposed design methodology incorporate noise as design specification along with other specifications which were lacking in previous automated methodology. And this methodology gives a platform to optimize both length and width of MOS transistor which will further minimize the circuit area. The computation of the ALCPSO-design methodology is performed using MATLAB and is linked to CADENCE tool with 0.18 µm parameters technology to verify the ALCPSO-based design methodology.

Fixator-Norator Pair Based Design of Feedback Networks for Analog Amplifier Circuits

Feedback is an integral part of many analog circuits. This paper presents a method for the design of feedback networks for analog amplifiers based on Fixator–Norator Pair (FNP). The design process for required transfer function includes inserting proper FNPs to the equivalent small signal model of the target circuit, with norators lying along the feedback path, and helps to design the feedback network components. Care must be taken to ensure that the added feedback should not alter the original DC biasing of the circuit. A number of examples are worked out in this paper using the proposed method and the results are verified. The FNP approach gives a one-step solution for the design problems which otherwise require tedious analysis and calculations. Although the scope of this paper is limited to design of feedback for amplifiers, a skillful designer can extend the proposed method to other areas of analog circuits.

Study of temperature reliability for a parallel high-efficiency class-E power amplifier

PurposeThe purpose of this paper is to investigate the temperature reliability for a parallel high-efficiency class-E power amplifier (PA).Design/methodology/approachTo explore the relationship between temperature and direct current (DC) characteristics, output power, S parameters and efficiency of the PA quantitatively, a series of reliability experiments have been designed and conducted to study the temperature reliability for this PA.FindingsFrom the results, the prominent performance degradation even failure is found during the testing. Furthermore, the thermal shock test can cause permanent failure, which is a great threat for PA.Research limitations/implicationsTherefore, to ensure the good performance, the influence of temperature on PA reliability should be carefully considered during the stage of PA design.Practical implicationsAll these can provide important guidance for the reliability design of PA.Social implicationsAll these can give some important guidance for PA application.Originality/valueIn addition, PA is usually designed according to the electrical properties at the room temperature. From the results above, it can be concluded that it may be unable to satisfy the performance requirement at high temperature. In turn, if it is designed according to the electrical properties at low temperature, the transistor often works in the super-saturated state, the reliability of PA will become the new problem. Therefore, to ensure the good performance, the influence of temperature on PA reliability should be carefully considered during the design.

Comparative evaluation of physical characteristics of different inflatable penile prostheses

Objective: The aim of this study was to describe and evaluate existing inflatable penile prostheses (IPPs) in an independent laboratory setting.Materials and methods: New IPPs were obtained from two manufacturers: American Medical Systems (AMS) and Coloplast. The AMS 700™ LGX (18 cm), CX (18 cm) and CXR (14 cm), and the Coloplast Titan® Touch (18 cm) and Titan Narrow (14 cm) were investigated. Internal pressure, length and girth of the cylinders were measured at 2 ml increments. A urodynamic individual transducer connected to an analogue amplifier and recording system was used to measure pressure. Rigidity and axial loading of the different IPPs were evaluated with a compression system.Results: Regular-size prostheses were inflated to 22 ml and narrow prostheses to 16 ml. The Titan Touch had a girth of 17.8 mm at 22 ml compared to 15.6 mm for the AMS 700 LGX and 16.5 mm for CX. The AMS 700 LGX increased in length by 13 mm from baseline, a feature that was unique among all the tested prostheses. Rigidity curves as assessed by compression showed significant variability, with both Titan prostheses and the AMS CXR exhibiting similar patterns and requiring a higher load to reach 50% compression. The buckling experiment showed different patterns of deformity.Conclusions: The results suggest that these prostheses exhibit significant physical differences. The clinical impact of these differences is poorly elucidated. These variations in behavior of the prostheses could be considered by physicians and patients when objectively assessing the choice of prosthesis. These findings could aid in objective patient counseling.

Linearized differential current sensor in low-voltage CMOS

PurposeThis work aims to improve upon the linearity of integrated CMOS current sensors used in switch mode power supply topologies, using a low-cost and low-voltage (less than 1.2 V) CMOS technology node. Improved sensor accuracy contributes to efficiency in switched supplies by reducing measurement errors when it is integrated with closed-loop control.Design/methodology/approachIntegrated current-sensing methods were investigated and CMOS solutions were prioritized. These solutions were implemented and characterized in the desired process and shortcomings were identified. A theoretical analysis accompanied by simulated tests was used to refine improvements which were prototyped. The current sensor prototypes were fabricated and tested.FindingsMeasured and simulated results are presented which show improved linearity in current sensor outputs. Techniques borrowed from analog amplifier design can be used to improve the dynamic range and linearity of current-steered CMOS pairs for measuring current. A current sensor with a gain of 5 V/A operating in a 10 MHz switch mode supply environment is demonstrated.Originality/valueThis paper proposes an alternative approach to creating suitable bias conditions for linearity in a SenseFET topology. The proposed method is compact and architecturally simple in comparison to other techniques.

Implementation of a novel efficient low cost method in structural health monitoring

In active structural health monitoring (SHM) methods, it is necessary to excite the structure with a preselected signal. More studies in the field of active SHM are focused on applying SHM on higher frequency ranges since it is possible to detect smaller damages, using higher excitation frequency. Also, to increase spatial domain of measurements and enhance signal to noise ratio (SNR), the amplitude of excitation signal is usually amplified. These issues become substantial where piezoelectric transducers with relatively high capacitance are used and consequently, need to utilize high power amplifiers becomes predominant. In this paper, a novel method named Step Excitation Method (SEM) is proposed and implemented for Lamb wave and transfer impedance-based SHM for damage detection in structures. Three different types of structure are studied: beam, plate and pipe. The related hardware is designed and fabricated which eliminates high power analog amplifiers and decreases complexity of driver significantly. Spectral Finite Element Method (SFEM) is applied to examine performance of proposed SEM. In proposed method, by determination of impulse response of the system, any input could be applied to the system by both finite element simulations and experiments without need for multiple measurements. The experimental results using SEM are compared with those obtained by conventional direct excitation method for healthy and damaged structures. The results show an improvement of amplitude resolution in damage detection comparing to conventional method which is due to achieving an SNR improvement up to 50%.

Trap Healing for High-Performance Low-Voltage Polymer Transistors and Solution-Based Analog Amplifiers on Foil.

Solution-processed semiconductors such as conjugated polymers have great potential in large-area electronics. While extremely appealing due to their low-temperature and high-throughput deposition methods, their integration in high-performance circuits has been difficult. An important remaining challenge is the achievement of low-voltage circuit operation. The present study focuses on state-of-the-art polymer thin-film transistors based on poly(indacenodithiophene-benzothiadiazole) and shows that the general paradigm for low-voltage operation via an enhanced gate-to-channel capacitive coupling is unable to deliver high-performance device behavior. The order-of-magnitude longitudinal-field reduction demanded by low-voltage operation plays a fundamental role, enabling bulk trapping and leading to compromised contact properties. A trap-reduction technique based on small molecule additives, however, is capable of overcoming this effect, allowing low-voltage high-mobility operation. This approach is readily applicable to low-voltage circuit integration, as this work exemplifies by demonstrating high-performance analog differential amplifiers operating at a battery-compatible power supply voltage of 5 V with power dissipation of 11 µW, and attaining a voltage gain above 60 dB at a power supply voltage below 8 V. These findings constitute an important milestone in realizing low-voltage polymer transistors for solution-based analog electronics that meets performance and power-dissipation requirements for a range of battery-powered smart-sensing applications.

Simplified symbolic transfer function factorization using combined artificial bee colony and simulated annealing

Symbolic circuit analysis inherits the exponential growth of transfer function complexity with the circuit size. Therefore, symbolic simplification is an NP-hard problem. Although many simplification techniques have been presented, the simplified transfer functions are not written in a factorized form, and consequently, it is difficult to assess the contribution of poles and zeros on the circuit behavior. In this paper, a swarm intelligence based methodology is presented for the simplified factorized symbolic analysis of analog circuits. In this method, an extension of the root splitting technique is utilized to rewrite the expanded transfer function of the circuit into a factorized form comprising DC-gain, poles, and zeros. Then, the derived factorized transfer function is simplified using a hybrid Global and Local search algorithm based on Artificial Bee Colony and Simulated Annealing (named GLABCSA). The objective function is defined to minimize the complexity of the symbolic factorized transfer function while minimizing the DC-gain error and pole/zero displacements. The presented approach has been successfully developed in MATLAB. The program can derive the simplified factorized symbolic transfer function automatically from the input text netlist of the circuit. Symbolic and numerical results over two analog amplifiers are given to illustrate the efficiency of the presented methodology.

Active Multiple Feed On-Chip Antennas With Efficient In-Antenna Power Combining Operating at 200–320 GHz

The design and measurement of active multiple-feed on-chip antennas realized in a SiGe seven metal layer backend process are presented for millimeter-wave applications. To prevent the excitation of surface waves, the principle of an integrated lens antenna (ILA) is used. In-antenna power-combining is realized by using a novel concept in which the outputs of two or more parallel differential amplifiers are directly combined in the radiating element itself. The proof-of-concept is shown by characterizing the antennas directly without the amplifiers being connected and by using adequate feeding networks capable of demonstrating high ILA bandwidths. Further, the power-splitting is realized through distributed transformer circuits, which offer high bandwidths at low losses. Different antennas are evaluated in order to attain reflection coefficients better than -10 dB over the entire frequency band of 200-320 GHz. Finally, the power-combining capabilities of such antennas are demonstrated by connecting a four-feed differential antenna to four single stage cascode amplifiers in parallel.

Development of RFECT system for in-line inspection robot considering extendibility of receiving sensors based on parallel lock-in amplifier

This paper proposes a new and effective approach to design a remote-field eddy current testing (RFECT) system equipped with a large number of sensors in order to provide full circumferential coverage of pipelines larger than 6 inches. By developing a parallel digital lock-in amplifier (LIA), the extendibility of receiving sensors can be achieved, and therefore, the modification of RFECT systems, which should be accompanied by sufficiently securing the receiving sensors whose number increases with the pipeline size, can be minimized. Using the design method for an RFECT system based on a parallel digital LIA, a new non-destructive testing (NDT) platform that can be applied to RFECT systems of various sizes without modifying the system architecture is developed. It is then applied to an RFECT system that can be mated with an in-line inspection (ILI) robot and has 36 receiving sensors to inspect unpiggable gas pipelines. The performance of the RFECT system is verified with respect to the sensitivity and the accuracy of defect characterization though the pull-rig test having a number of artificial defects.

A Novel Read-Out Electronics Design Based on 1-Bit Sigma-Delta Modulation

The conventional front-end electronics for PET imaging consist of an energy circuit and a timing circuit. A single channel in front-end electronics typically requires several amplifiers, an ADC and a TDC. In this paper, we present a novel front-end electronic design using 1-bit sigma-delta ( $\boldsymbol {\Sigma }$ - $\boldsymbol {\Delta }$ ) modulation and an FPGA. The new design requires only one analog amplifier per channel. The output of the analog amplifier is read directly by the FPGA. Both the energy and timing calculation are implemented in FPGA firmware. The scope of this paper is to introduce the novel design in detail and to evaluate its performance in energy and dark current measurements. Simulink simulations were performed to validate the design with ideal components. A one-channel prototype circuit was built to assess the design with real components. The prototype circuit was tested with different input signals, including test pulses, pulse signals from a PMT detector, DC current signals and dark current signals from an SiPM sensor. Both the simulation and experimental results show that the method is inherently stable and has excellent accuracy and linearity in energy and dark current measurements. The prototype analog board was built with discrete components cost about $ 0.5 in total. The power consumption was about 20 mW. We conclude that the new method provides a cost-efficient and power-efficient way to accurately measure the energies of analog pulses and dark currents from detectors. The timing performance of this method is currently under evaluation.

Doherty Goes Digital: Digitally Enhanced Doherty Power Amplifiers

Efficiency enhancement techniques for high-power amplification systems are now mature technologies, with Doherty power amplifiers (PAs) being widely used in field-deployed wireless base stations. A typical Doherty PA consists of two parallel amplifiers (a carrier amplifier, biased in class-AB, and a peaking amplifier, biased in class-C), an input analog splitter, and a nonisolated output power combiner. The operation of the Doherty PA is based on an active load modulation mechanism, which allows the carrier and peaking amplifiers to operate into optimal load-impedance trajectories that vary according to the amplitude of the input signal. This, in principle, results in increasing the average efficiency of the Doherty PA without compromising its linearity.

EMI Susceptibility of a Digitally Based Analog Amplifier in a 180-nm CMOS Process

This paper investigates and reports the susceptibility to electromagnetic interference (EMI) of a digitally based analog amplifier. The amplifier has been designed in the UMC 180-nm CMOS technology with digital component blocks. Simulations as well as comparative measurements of commercial amplifiers show a superior immunity to EMI of the digitally based amplifier with respect to purely analog topologies.