Analog Amplifier Research Articles

20 GHz substrate crosstalk sensor for mobile communication applications

ABSTRACT A 20 GHz substrate crosstalk noise sensor is presented. It is based on CMOS inverters used as analog amplifiers, in a Cherry-Hooper configuration. A buffer in the feedback path is employed to further enhance the circuit performance. The proposed substrate noise sensor is targeted to high-frequency mobile communication System-on-Chip applications for capturing the high-frequency inter-modulated coupling products through substrate. Superior sensing characteristics are demonstrated via simulation in an RFCMOS 65 nm process. The proposed design is capable of providing a gain of 6.6 dB over a frequency range from 8.5 MHz to 20 GHz with −1 dB compression point equal to 100 mV.

Massive Parallel Current Power Amplifier Concept for Power Hardware in the Loop Applications

The development of the smartgrid increases the complexity of the current electric grid. To verify and validate the operation of the systems involved in it, Power Hardware-In-theLoop (PHIL) technique allows to test the complete system in an exhaustive way. But the reduced bandwidth of the overall test system can cause inaccuracies and instabilities, which can be harmful for the Hardware Under Test (HUT) or the people who are performing the test. To increase PHIL performance and tackle these problems, this paper proposes a new concept of high bandwidth current amplifier. It is based on a topology of massive parallel interleaved buck-boost converter, which distribute in an equal manner the total current in all the branches. This current reduction allows to use transistors with better switching behaviour, which increase the bandwidth of the converter. Furthermore, a Discontinuous Conduction Mode (DCM) is used, obtaining the nominal output current in only one switching cycle. Description of the concept and the design parameters are provided. Finally, the behaviour of the proposed Power Amplifier (PA) at high frequency setpoint currents is shown in a Matlab/Simulink simulation.

Machine Learning and Rules Induction in Support of Analog Amplifier Design

The aim of the paper is to present a two-step method for facilitating the design of analog amplifiers taking into account the bottom–top approach and utilizing machine learning techniques. The X-chart and a framework describing the specificity of analog circuit design using machine learning are introduced. The possibility of libraries with open machine learning models to support the designer is also discussed. The proposed method is verified for a three-stage amplifier design. In the first step, the stage type is predicted with 89.74% accuracy as the applied learner is a Decision Tree machine learning algorithm. Moreover, two induction rule algorithms are used for predictive logic generation. In the second step, some typical parameters for a given stage are predicted considering four learners: Decision Tree, Random Forest, Gradient Boosted Trees, and Support Vector Machine. The most suitable is found to be Support Vector Machine, which is characterized with the smallest obtained errors.

Fast Topology Selection for Analog Amplifier Circuits Using On-The-Fly Cascaded Neural Networks

In this paper, a machine learning-based approach for the automation of topology selection of integrated analog amplifier circuits is presented. A dataset of 480,000 circuits for 30 different amplifier topologies is generated for the prediction algorithm based on a precomputed lookup tables (LUTs) approach. A first approach based on neural networks is presented where the required specifications act as inputs to the networks, and the output of the network is the suitable topology for such a set of specifications. A modified cascaded neural network approach is examined to reduce the training time of the network while maintaining the prediction accuracy. Using the cascaded neural network approach, the network is trained in only one minute on a standard computer, and a 90.8% prediction accuracy is achieved. This allows on-the-fly changes in the input specifications, and consequently the neural network, to enable examining different design scenarios.

A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process

This article presents a high-speed receiver for next-generation 8K ultra-high-definition TVs. The receiver supports error-free communication between the timing controller and the display driver integrated circuits (DDIs) across various channels. Because the receiver must be co-integrated with pixel drivers in the DDI, it must be implemented in a process with high-voltage devices, which poses significant challenges in achieving beyond 5-Gb/s operation. We propose techniques for overcoming such process-induced speed limitations. They include a level-shifting passive continuous-time linear equalizer (CTLE), an active CTLE with extended bandwidth using a negative capacitor, a speculative decision feedback equalizer with a down-sampled edge-sampling path, and a low-dropout regulator with parallel error amplifiers to achieve all-band power supply rejection. A reference-less clock and data recovery circuit with a new frequency detector is also described. Fabricated in a 180-nm CMOS process, the prototype receiver operates at 5.2 Gb/s and can compensate up to 29-dB channel loss while consuming 120 mA from a 1.8-V supply.

A 12-Bit 1 GS/s RF Sampling Pipeline-SAR ADC With Harmonic Injecting Cross-Coupled Pair Achieving 7.5 fj/Conv-Step

We present an RF sampling 1 GS/s 12-bit single-channel successive approximation register (SAR) assisted pipeline analog to digital converter (ADC). A novel Harmonic-injecting Cross-Coupled Pair (HXCP) is proposed in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{G}_{\text {m}}$ </tex-math></inline-formula> -R based residue amplifier design as a critical part of the presented ADC. This technique overcomes the challenges in designing analog amplifiers using advanced nanometer CMOS processes and achieves the gain and linearity required for the ADC. By implementing the HXCP in a residue amplifier (RA), the proposed technique successfully improves the RA linearity by at least 10 dB and meanwhile boosts the gain of the RA to be about 8. The entire ADC consists of three stages each with 4-bit, 4-bit, and 6-bit, respectively. Two one-bit interstage redundancies are implemented between the three stages. Various techniques are also implemented to help the ADC achieve the targeted speed and resolution. The presented ADC was implemented in a 28nm CMOS process and achieves an ERBW of 1 GHz, an SNDR of 60.7 dB, an SFDR of 73 dB at Nyquist input (495 MHz) and an SFDR of 82 dB at 1 GHz input. A 7.5 fj/conv-step FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">w</sub> and a 169.4 dB FoMs are achieved, which demonstrate one of the best Figure of Merits (FoMs) among ADCs of similar speed and resolution.

Intrinsically flexible all-carbon-nanotube electronics enabled by a hybrid organic–inorganic gate dielectric

The advancement of Internet of Things has stimulated huge demands on low-voltage flexible electronics. Carbon-nanotube (CNT)-based electronics are of great promise to this end for their intrinsic flexibility, high carrier mobility, and capability to synthesize as semiconducting or metallic to serve as the channels, electrodes, and interconnects of circuits. However, the gate dielectric often has to adopt brittle oxides, which can seriously limit the device flexibility. Herein, we show that a hybrid polyimide-Al2O3 material can serve as a good gate dielectric to realize truly intrinsic flexibility of transistors and circuits based on CNTs. With this hybrid dielectric, high-performance all-CNT transistors and integrated circuits of inverters, ring oscillators, and logic gates are demonstrated. Particularly, the inverters exhibit a remarkably high gain of 342.5 and can be used as an analog amplifier for millivolt small signals. Ultralow voltage (50 mV) operation is also feasible, which highlights the great promise for low-power applications.

Systematic realization of non-linear arithmetic functions using hexagonal Field Programmable Analog Array

In spite of being the most popular reconfigurable platform for analog and mixed-mode design implementation, Field-Programmable Analog Array (FPAA) structures are limited to analog filters, amplifiers and communication circuits. Hexagonal FPAA is an established alternative to classical square-lattice FPAA but suitable architectures have not been cultivated much. In this paper, a hexagonal FPAA, implementing different nonlinear functions, eliminating global interconnections, and employing a graph-based mapping algorithm, has been proposed. For communication among the fundamental blocks and reconfiguration, it uses a local interconnection network consisting of central and corner switch blocks. The proposed mapping algorithm uses directed graph representations of fundamental blocks and desired circuits to map the nonlinear functions in the presented FPAA. Weights have been assigned to the graphs and manipulated for efficient placement and routing. All the theoretical predictions have been validated through SPICE simulation using 65 nm CMOS technology. The proposed architecture and mapping algorithm can be extended for large-scale FPAA enriched with automatic placement and routing tools.

An X/Ku Dual-Band Switchless Frequency Reconfigurable GaAs Power Amplifier

This letter presents an <inline-formula> <tex-math notation="LaTeX">$X$ </tex-math></inline-formula>/ <i>Ku</i> dual-band switchless power amplifier (PA) with frequency reconfigurable operation in a 0.25-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs pHEMT process. The proposed reconfigurable PA consists of one dual-band drive amplifier and two single-band amplifiers in parallel. The first stage drive amplifier works in dual-band mode of <inline-formula> <tex-math notation="LaTeX">$X$ </tex-math></inline-formula>-band and <i>Ku</i>-band, and the two single-band amplifiers work in <inline-formula> <tex-math notation="LaTeX">$X$ </tex-math></inline-formula>-band and <i>Ku</i>-band, respectively. An interstage coupled line is used to split the dual-band frequencies into high-band (<i>Ku</i>-band) and low-band (<inline-formula> <tex-math notation="LaTeX">$X$ </tex-math></inline-formula>-band), and the output-stage coupled line acts as a combiner. The operating frequency band of the proposed PA can be changed by turning off drain voltages of unused single-band amplifiers. Measurements results show that the proposed reconfigurable PA features a maximum power-added efficiency (PAE) of 44.4&#x0025; and a power gain of 19.6 dB while delivering an output power of 29.6 dBm at 8.5&#x2013;9.5 GHz of the low-band mode. At 15.5&#x2013;16.5 GHz of the high-band mode, the PA achieves a maximum PAE of 38.4&#x0025;, a power gain of 18.1 dB with an output power of 30.1 dBm. The chip area of the proposed reconfigurable PA is 2 <inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 2 mm² including all RF and dc pads.

Integrating Homogeneous Current-Saturation Graphene Transistors Into High-Linearity Amplifiers

In this work, a new type of graphene ICs only comprising multiple graphene field-effect transistor (GFET) components is first reported. Based on the GFET design that enables homogeneous electrical characteristics in batch-made devices, the practicality and functionality significances of multi-GFET integration are experimentally demonstrated via high-fidelity amplifiers for baseband analog signals. Different from the quadratic relationship of the gate-controlled current output (in saturation region) in the traditional silicon-based MOSFETs, the saturation current output of GFETs relating to the gate-controls possesses high linearity. This advantage overcomes the inherent nonlinear distortion issues in the existing silicon MOSFET amplifiers and potentially provides a promising scenario for the accurate preamplification of weak analog signals. Besides, the novel circuit configuration and signaling principle may expand the developmental paradigm of analog amplifiers and set groundwork for the development and practicalization of advanced carbon-based nanoelectronic ICs.

Design Techniques for Ultra-Low Voltage Analog Circuits Using CMOS Characteristic Curves: a practical tutorial

The use of ultra-low-voltage (ULV) analog circuits for IoT applications, in which reduced power consumption is a mandatory specification, is becoming more and morean important design approach. Also, in many IoT applications, power is supplied with energy harvested from environmental sources. It is more efficient for the circuit to operate at a voltage level close to the provided by the energy harvester (between 0.3 and 0.6 V). To deal with this when using low-cost technology process nodes - 180-nm, for example, with |VT| ≈0.5V - it is necessary to apply specific design techniques that take advantage of reverse short channel effect, forward bulk bias-ing (FBB) or bulk-driven circuits. The use of low-VT transistors is also a good alternative when they are available inthe target process node. This paper presents a comprehensive scenery about modern CMOS ULV design techniques from the designer’s point of view, including design trade-offs and comments about design decisions. Four step-by-step design examples of ULV circuits are presented: a cross-coupled negative transconductor, a CMOS inverter as an analog amplifier, a pseudo-differential inverter-based amplifier, and a bulk-driven differential amplifier with active load. All designs require the biasing of transistors in moderate and weak inversion regions.The goal is to demonstrate that it is possible to design ULV analog circuits using standard-VT transistors with a supply voltage much lower than the nominal VDD.

Performance Comparison of Serial and Parallel Hybrid Fiber Amplifier under Optimum Pump Conditions

In this work, two different configurations of hybrid fiber optic amplifiers are investigated and simulated via OptiSystem 7.0 software, namely, serial and parallel hybrid fiber optical amplifiers (S– and P–HFOAs). The investigation involves performance comparison for the S– and P–HFOA under optimum pump conditions to demonstrate the advantages and disadvantages of each configuration. The simulation results show that the serial configuration has a high average gain level of 19.2 dB, an appropriate noise figure about 4.3 dB, but low saturation power, and limited gain bandwidth of approximately 40 nm, which is considered a primary issue in S–HOFA design, in addition to the pump conversion efficiency still insufficient in the Raman amplifier stage. While in P–HFOA design, a wide 3–dB gain bandwidth of more than 60 nm is maintained, along with an average gain level of 13.5 dB, high average noise figure about 8.3 dB and high saturation power due to the absent of cascading effect in parallel configuration

A digital‐controlled gate charge detection circuit for short‐circuit protection and condition monitoring of SiC MOSFET

The safe and reliable operation of power converter requires a protection circuit with fast response when the power device is subjected to the short-circuit (SC) fault. In addition, the on-line condition monitoring circuit is beneficial to provide a suggestion for the replacement of aged device. The silicon carbide (SiC) power devices promise the higher power density in the system performance, but is still limited by the poor SC reliability issue. Thus, it is crucial to improve the robustness of SiC-based power converter from the circuit design. This work proposes a novel gate charge detection circuit for SiC devices. It achieves a high-speed SC protection against hard switching fault (HSF) based on the difference of Miller capacitance between normal condition and SC fault. Meanwhile, the condition monitoring is achieved based on the high gate leakage current of aged device. A high-precision analog amplifier circuit is designed to acquire the gate signal. The normal/fault signal is distinguished and the protection is triggered using a digital-controlled method to reduce the hardware cost. A 600-ns SC response time is achieved, and the monitoring circuit can differentiate the aged device from the healthy one.

Positive-Feedback-Based Design Technique for Inherently Stable Active Load Toward High-Gain Amplifiers With Unipolar a-IGZO TFT Devices

This letter presents analysis of an inherently stable positive-feedback-based active load, first reported in our prior work, to realize high gain analog amplifiers using unipolar a-IGZO TFT technology. Additionally reported are theoretical performance bounds and design guidelines to maximally utilize a general positive-feedback scheme for the active load while maintaining stability. To demonstrate a design implementation, a single stage fully differential operational transconductance amplifier with common mode feedback has been manufactured and measured to have 40-dB open-loop gain at dc and a unity gain frequency of 61 kHz while driving a 30-pF load capacitance.

High frequency RFCMOS substrate noise sensor

A substrate crosstalk sensor featuring high performance gain over a wide frequency range is proposed. The topology is used as high frequency crosstalk noise sensor in modern mobile communication SoC applications. The design is based on a differential amplifier input stage combined with CMOS inverters as analog amplifiers in a Cherry-Hooper topology. The sensor performance is demonstrated via simulation results in an RFCMOS 65 nm process with a gain of 5.7 dB in a frequency range from 24 MHz up to 15 GHz, and –1 dB compression point of 107 mV, appearing as the most advanced and high performance noise sensor in the literature.

An efficient wide flatness gain bandwidth with parallel hybrid fiber amplifier

AbstractIn this article, we experimentally propose an efficient wide flat gain bandwidth with a parallel hybrid fiber amplifier. The setup includes parallel amplifier branches. In the first branch, serial erbium‐doped and Raman fiber amplifiers are used. In the second branch, only a Raman fiber amplifier is used. Three Raman pump power units (i.e., 1410, 1480, and 1495 nm) are used to achieve Raman gain at different optical communication bands. At optimum pump powers and at a small‐signal power of −30 dBm, an average gain of 18.5 dB with a maximum gain variation of 3 dB and a gain flatness bandwidth of 83 nm, that is, from 1527 to 1610 nm, is achieved. This gain flatness is expanded to 92 nm (1525–1617 nm) at a large input signal power of −5 dBm with an average gain level of 13 dB. In our proposed amplifier, the Raman amplification peaks (1510 and 1595 nm) are chosen to be far from the erbium amplification peak (1530–1570 nm) in order to avoid the overlapping and the saturation in the first amplifier branch. Therefore, due to such wavelength optimization in addition to the recycling the residual Raman pump power, a wide flatness gain bandwidth is achieved for both of low and large input signal powers.

A Novel Standard-Cell-Based Implementation of the Digital OTA Suitable for Automatic Place and Route

This paper presents a novel implementation of a digital-based Operational Transconductance Amplifier (OTA) which has been recently introduced in the technical literature as a fully digital alternative to the conventional differential pair to implement low voltage analog amplifiers and comparators. The proposed implementation does not make use of resistors, floating gate resistors nor C-Muller elements and is made up of only digital gates usually available in the standard cell libraries. The resulting analog circuit schematic can be described using structural VHDL or Verilog languages and is suitable to be integrated in an automatic synthesis and place and route flow for digital circuits. The proposed digital-based amplifier has been implemented in a commercial 130 nm CMOS process by using an automatic place and route flow for layout generation starting from the Verilog netlist. Post layout simulations are presented to show the performance of the proposed circuit and compare it against the state of the art.

Surface Passivation Treatment to Improve Performance and Stability of Solution-Processed Metal Oxide Transistors for Hybrid Complementary Circuits on Polymer Substrates.

Hybrid integration of n‐type oxide with p‐type polymer transistors is an attractive approach for realizing high performance complementary circuits on flexible substrates. However, the stability of solution‐processed oxide transistors is limiting the lifetime and reliability of such circuits. Oxygen vacancies are the main defect degrading metal oxide transistor performance when ambient oxygen adsorbs onto metal oxide films. Here, an effective surface passivation treatment based on negative oxygen ion exposure combined with UV light is demonstrated, that is able to significantly reduce surface oxygen vacancy concentration and improve the field effect mobility to values up to 41 cm2 V−1 s−1 with high on–off current ratio of 108. The treatment also reduces the threshold voltage shift after 2 days in air from 5 to 0.07 V. The improved stability of the oxide transistors also improves the lifetime of hybrid complementary circuits and stable operation of complementary, analog amplifiers is confirmed for 60 days in air. The suggested approach is facile and can be widely applicable for flexible electronics using low‐temperature solution‐processed metal oxide semiconductors.

High-power ultrafast fiber lasers for materials processing

Abstract State-of-the-art fiber-laser systems can deliver femtosecond pulses at average powers beyond the kilowatt level and multi-mJ pulse energies by employing advanced large-mode-area fiber designs, chirped-pulse amplification, and the coherent combination of parallel fiber amplifiers. By using sophisticated coherent phase control, one or even several output ports can be modulated at virtually arbitrary power levels and switching speeds. In addition, an all-fiber setup for GHz-burst generation is described allowing to access an even wider range of laser parameters. The combination of all these approaches together with the robustness, efficiency, and excellent beam quality inherent to fiber-laser technology has the potential to strongly improve existing materials-processing applications.

Design and analysis of new ultra compact decoupled XYZ[formula omitted] stage to achieve large-scale high precision motion

A new high precision ultra-compact decoupled XYZθ motion stage based on flexure hinges is designed and analyzed. The stage mainly consists of three components including serial–parallel dual-stage amplifier, Z-shape motion steering mechanism and motion decoupled mechanism. Compared with the existing stages, the proposed high precision motion stage has many advantages such as extremely compact structure, large output decoupling motion and XYZθ four axes output displacement. The function of serial–parallel dual-stage amplifier is to amplify the travel range of nano positioning piezo actuator (PZT) by connecting two parallel bridge type mechanism. The Z-shape mechanism can change the direction of motion transmission to make the stage more compact and form movement in XYZθ four directions. The decouple mechanism can reduce the implicative movement of different piezo actuators. Then, kinetostatic analysis of this new XYZθ stage is conducted to analyze the stage. Finally, the finite-element analysis (FEA) and prototype experiments are implemented to verify the design objectives.