Amplifier Architecture Research Articles

A Super-Resolution Mixed-Signal Doherty Power Amplifier for Simultaneous Linearity and Efficiency Enhancement

This article presents a mixed-signal Doherty power amplifier (MSDPA) architecture for simultaneous linearity and efficiency enhancement. The MSDPA comprises one analog power amplifier (PA) as the main PA and one binary-weighted digital PA as the auxiliary PA. The MSDPA input is a generic envelope-varying complex-modulated signal. Based on the realtime amplitude-modulated (AM) envelope, auxiliary digital PA weightings are dynamically turned-on to perform optimum Doherty load modulation for superior linearity and back-off efficiency. Moreover, quantization noise is largely suppressed by the mixed-signal Doherty operation and nonuniform quantization (NUQ), while spectral images are substantially reduced by the quasi-first-order hold (quasi-FOH) operation, which together achieves super-resolution over conventional digital PAs; this makes the MSDPA conducive to millimeter-wave (mm-Wave) or compound PA designs by obviating the need for a large effective number of bits (ENOB) on AM digital controls. As a proof of concept, a 3-bit MSDPA is implemented at 27 GHz in a 45-nm silicon-on-insulator (SOI) CMOS process. The prototype PA achieves 40.1% peak power-added efficiency (PAE), 23.3-dBm saturated output power (Psat), and 39.4% PAE for 22.4-dBm P1dB at 27 GHz in continuous-wave (CW) measurements. The PAE at 6-dB power back-off (PBO) is 33.1%, which corresponds to a 1.68× improvement over a normalized Class-B PA. With only three control bits, the MSDPA PA supports a 12-Gb/s 64-QAM signal at -24.5-dB rms error vector magnitude (EVM) and average Pout/PAE of +15.6 dBm/27.8% without digital predistortion (DPD).

A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier

This article presents a multi-subharmonic switching (SHS) digital power amplifier (PA) architecture for enhancing power back-off (PBO) efficiency while achieving watt-level output power. The proposed phase-interleaved architecture provides the inherent cancellation of the subharmonic components in the PBO region, alleviating the burden of the matching network. The proposed multi-SHS scheme can be further combined with a class-G operation to create a greater number of efficiency peaks in the PBO region. A transformer-based, three-way power combiner and a triple-stacking class-D driver are utilized to obtain watt-level output power. The proof-of-concept PA prototype is implemented with a switched-capacitor PA (SCPA) architecture in 65-nm CMOS and achieved 30-dBm peak power at 1.9 GHz, with 45.9%/41.3%/35.3%/32.2%/24.2% drain efficiency located at 0-, -3.5-, -7.0-, -9.5-, and -12-dB PBO, respectively. The average efficiency was 31.4% in real-time operation with a 7.2-dB peak-to-average power ratio (PAPR) modulated signal.

Classification and Design Space Exploration of Low-Power Three-Stage Operational Transconductance Amplifier Architectures for Wide Load Ranges

Since operational transconductance amplifiers (OTAs) form the basic building blocks of many analog systems, the compensation of three-stage OTAs has attracted a lot of attention in the literature. Many different solutions to the stability problem of such OTAs have been proposed over the past 20 years, with each solution exhibiting different properties or targeting a different application. This work surveys a broad selection of previously reported architectures and proposes a novel classification scheme that exposes features common to seemingly different compensation architectures and serves as a guideline for which type of OTA is suitable for a given application. In addition, a novel figure of merit (FoM) is proposed to guide the designer in deciding which OTA architecture suits the tradeoffs specific to the application at hand. Theoretical discussions are further reinforced by transistor-level simulation results.

Ultrafast background-free ro-vibrational fs/ps-CARS thermometry using an Yb:YAG crystal-fiber amplified probe.

A novel laser system for ro-vibrational spectroscopy using coherent anti-Stokes Raman Scattering in hybrid fs/ps regime is presented. A single Yb:KGW laser source is used as a master laser to generate the three CARS laser beams, namely the pump and Stokes femtosecond pulses and a 58 ps probe pulse. Master oscillator power amplifier (MOPA) architecture is implemented to increase the probe output power using a custom two stage free space linear amplifier. The probe is 0.37 cm-1 in width and 100 µJ in energy to allow resolving the Q-branch ro-vibrational lines of N2 and recording single shot CARS spectra at kHz repetition rate in flames. An original and simple technique based on the study of the influence of probe delay and polarization has been setup to optimize nonresonant background rejection, with no loss in resonant contribution. CARS performances are reported for N2 thermometry between 300 K and 3000 K, demonstrating state of the art precision.

A 0.25-V fifth-order Butterworth low-pass filter based on fully differential difference transconductance amplifier architecture

This paper presents a fifth-order Butterworth low-pass filter based on the fully differential difference transconductance amplifier (FDDTA) building blocks. At first, the FDDTA has been stated and its operation has been evaluated. Then, a practical implementation using two fully differential inverter-based operational transconductance amplifiers (OTA) was investigated. This particular FDDTA implementation relies on two main features: the intrinsically matched transistors that assure similar transconductances and output conductances for both inverter-based OTA instances; and the inverter-based approach without internal nodes that reduces circuit complexity and power consumption since it requires no supplementary external calibration circuit such as tail current or bias voltage sources. Finally, the filter architecture, which consists of one inverter-based OTA input stage and five FDDTAs in a cascade connection has been evaluated, showing that it presents the expected fifth-order transfer function according to the Butterworth theory. The prototypes, implemented in a 130 nm CMOS process, operate in weak inversion supplied with 0.25 V and consumes 603 nW. Furthermore, they feature a DR of 57 dB in a 100 Hz bandwidth and a maximum THD of 54 dB, therefore, accomplishing specifications that suit for low-frequency applications.

A 28 GHz 0.18-μm CMOS cascade power amplifier with reverse body bias technique

A 28 GHz power amplifier (PA) using CMOS 0.18 μm Silterra process technology is reported. The cascade configuration has been adopted to obtain high Power Added Efficiency (PAE). To achieve low power consumption, the input stage adopts reverse body bias technique. The simulation results show that the proposed PA consumes 32.03mW and power gain (S21) of 9.51 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 11.10 dBm and maximum PAE of 16.55% with output 1-dB compression point (OP1dB) 8.44 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.

Low power CMOS variable gain amplifier design for a multistandard receiver WLAN/WIMAX/LTE

This paper deals with a new compact low-power variable gain amplifier (VGA) architecture design for wireless communication multistandard receivers. The proposed VGA is a two stages cascaded topology that includes a folded cascode operational transconductance amplifier stage and a VGA core. The new “cell” structure has been introduced to demonstrate the performance enhancement with the use of only one VGA stage. The heuristic method is used to optimize the proposed circuit performance for high gain, low noise and low power consumption. This circuit is implemented and simulated using device-level description of TSMC 0.18 µm CMOS process. The simulation results indicate that the new VGA achieves a gain ranging from a minimum of − 25 dB toa maximum reaching 79 dB with a large bandwidth of 200 MHz. The designed VGA circuit acquires a noise figure less than 18 dB, an input referred noise of around 9.3 nV2/Hz and the third order intercept point measured at the input (IIP3) of 15 dBm. The proposed circuit consumes only 0.5 mW under 1.8 V supply voltage.

Analysis of Gain Variation With Changing Supply Voltages in GaN HEMTs for Envelope Tracking Power Amplifiers

Envelope tracking (ET) is a promising power amplifier (PA) architecture for current and future communications systems, which uses dynamic modulation of the supply voltage to provide high efficiency and potentially very wide bandwidth over a large dynamic range of output power. However, the dynamic nature of the supply voltage can lead to a problematic variation in transistor gain, particularly in GaN HEMTs. This paper describes and analyzes this behavior and the detrimental effect it can have on ET PAs. Contributing factors and origins of gain variation are described in detail along with how, for the first time, meaningful comparisons can be made between different devices. Using these guidelines, gain variation is shown to be a widespread issue effecting most GaN HEMTs presented in literature. To allow an analysis of the intrinsic device behavior, an extended transistor model is developed that takes the effect of gate and source field plates into account. This model is refined using measurement data and used to demonstrate the fact that the parasitic gate–drain capacitance ( $C_{\textrm {GD}}$ ) is the main contributor to the small-signal gain variation—a significant part of the overall gain variation. Based on this knowledge, possible strategies to reduce gain variation at the transistor technology level are proposed, allowing the optimization of GaN HEMTs specifically for ET PAs. One identified strategy involves reducing the length of the gate field plate and is shown to be a viable approach to reduce the gain variation in GaN HEMTs, albeit at an increased RF/dc dispersion.

Supply- and Load-Modulated Balanced Amplifier for Efficient Broadband 5G Base Stations

This paper presents a broadband efficient power amplifier (PA) targeting sub-6-GHz 5G base station applications. Due to the demanding requirements in both peak-to-average power ratio (PAPR) and bandwidth in 5G systems, we employ a combination of both load and supply modulation for efficiency enhancement. Active matching, implemented using an RF-input load-modulated balanced amplifier (LMBA) architecture, enables efficient octave-bandwidth operation. Supply modulation, which is carrier frequency agnostic, is then used to further extend the back-off efficiency. This paper focuses on a study of supply modulation strategies for the load-modulated PA using an efficient GaN eight-level discrete supply modulator. To overcome the bandwidth limitations associated with discrete-level switching, a commutation rate reduction (CRR) filter is applied in digital baseband and its effects are analyzed theoretically and experimentally. The supply-modulated LMBA is characterized across 1.8–3.8 GHz with 100-MHz, 10-dB PAPR signals. An output power of 34 dBm with average composite (total) PAE ranging from 22.4% to 43.9% across the band is demonstrated, with an ACLR of about −50 dBc after digital predistortion.

A Dual-Wavelength Pulsed Laser Processing Platform for a-Si Thin Film Crystallization

Interest in laser crystallization (LC) of silicon (Si) thin films has been on the rise in fabrication of polycrystalline silicon (pc-Si) based thin/ultrathin photovoltaic solar cells and Si based thin film transistors (TFT). Laser based fabrication of device quality pc-Si thin films at room temperature is expected to be a key enabling technology because of its low energy, material and process time budget. Fabrication of high-quality pc-Si thin films without pre-/post-treatment at large is a disruptive technology which has the potential to revolutionize the Si thin film industry. We hereby describe in detail a multi-wavelength laser processing platform specially developed for crystallization of amorphous silicon (a-Si) thin films into pc-Si thin films. The platform has three main stages. The first stage consists of a nanosecond pulsed ytterbium (Yt3+) doped fibre-laser with a master oscillator power amplifier architecture, operating at a wavelength of 1064 nm with an adjustable repetition rate between 80 kHz–300 kHz. The output beam has a maximum power of 18 W with a pulse energy of 90 µJ. The pulse durations can be set to values between 15 ns–40 ns. The second stage has free-space optical elements for second harmonic generation (SHG) which produces an emission at a wavelength of 532 nm. Conversion efficiency of the SHG is 25% with an output pulse energy of 20 µJ. The platform provides two wavelengths at either 1064 nm or 532 nm in crystallization of a-Si films for different crystallization regimes. The last stage of the platform has a sample processing assembly with a line-focus, which has an x-y motorized stage on a vibration isolated table. Speed of the motorized stage can be set between 1 mm/s–100 mm/s. Stage speed and repetition rate adjustments help to adjust overlap of successive pulses between 97.22–99.99%. Our platform has variety of tune parameters that make it a uniquely flexible system for delicate Si thin film crystallization. A large selection of operational parameter combinations, the wavelength selection and simultaneous x-y scanning capability allow users to crystallize Si films on various substrates optimally. The operation wavelength choice can be done by considering optical absorption and thickness of a-Si films on different types of substrates. Hence, delivering precise amount of absorbed energy in the line-focus irradiation is useful in increasing the average size of crystalline domains; moreover, nucleation of crystallites can be initiated either from the top or bottom interface of the film. Continuous and simultaneous motion of the stage in two dimensions allows to process arbitrary continuous pc-Si geometries in a-Si film. In summary, our multi-wavelength laser processing platform offers all-in-one LC utility for intricate LC-Si processing.

Highly adaptable gain-switched fiber laser with improved efficiency.

A highly adaptable fiber laser with pulse-on-demand and precision pulse-duration tuning is presented. It is based on a compact optical design combining the gain-switching technique with the all-fiber master oscillator and pump-recovery amplifier architecture. The approach of laser-pulse stability control by compensation pumping and pulse-duration control by changing the pump wavelength are introduced. In order to prove the concept, a laser setup capable of producing laser pulses with an average power of up to 30 W and a peak power of approximately 1 kW at an improved efficiency and an arbitrary repetition rate is presented.

Fourier-domain mode-locked laser combined with a master-oscillator power amplifier architecture

Originally introduced in 2005 for high-speed optical coherence tomography, the rapidly wavelength-swept Fourier-domain mode-locked (FDML) laser still, to this day, enables highest imaging speeds through a very high-speed spectral tuning capability. The FDML laser achieves a tuning bandwidth of over 1/10th of its center wavelength and can sweep this entire bandwidth in less than a microsecond. Interestingly, even though it covers a very broad spectral range, instantaneously it has a narrow spectral linewidth that puts it in a unique space compared to other high-speed broadband laser sources, e.g., mode-locked lasers or supercontinuum sources. Although it has been applied for nonlinear Raman spectroscopy and imaging, a current drawback of this continuous wave laser is the relatively low instantaneous power of 10-100mW. Here, we report the combination of an FDML laser with a master oscillator power amplifier (MOPA) architecture to increase the instantaneous power of the FDML for nonlinear optical interactions. The output of an FDML laser around 1060nm is modulated to short pulses by using an electro-optic amplitude modulator and subsequently amplified using ytterbium-doped fiber amplifiers (YDFAs). This generates a spectral rainbow of 65 picosecond pulses, where each pulse has a distinct, monochromatic wavelength. The instantaneous power can be adjusted by the YDFAs to reach nonlinear optical excitation regimes. This wavelength-swept FDML-MOPA laser will have a vast range of applications in, e.g., nonlinear optics, spectroscopy, imaging, and sensing.

A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement

This paper presents a subharmonic switching (SHS) digital power amplifier (PA) architecture that enhances power efficiency in the power back-off (PBO) region. The proposed technique can be combined with the class-G operation. By using either SHS or dual-power supply switching, it can provide several peak efficiency points, located at 0, -3.5, -9.5, and, -13 dB PBO. By judiciously choosing the optimal operation mode between SHS and dual supplies for each PA cell at different output power levels, we can further improve the efficiency between peaks. The SHS PA prototype is implemented with a switched-capacitor PA (SCPA) architecture in 65-nm CMOS to validate the effectiveness of the proposed technique, which achieves a 26.8-dBm peak output power with a 49.3% peak drain efficiency (DE) at 2.25 GHz and a 27% DE at -13-dB PBO.

Configurable Operational Amplifier Architectures Based on Oxide Resistive RAMs

This paper introduces memristor-based operational amplifiers (OpAmps) in which semiconductor resistors are suppressed and replaced by memristors. The ability of the memristive elements to hold several resistance states is exploited to design programmable closed-loop OpAmps. An inverting OpAmp, an integrator and a differentiator are studied. Such designs are developed based on a calibrated memristor model, and offer dynamic configurability to realize different gains and corner frequencies at reduced chip area.

Hybrid Analog/Digital Continuous Class B/J Mode for Broadband Doherty Power Amplifiers

In this paper, a new digitally driven two input continuous mode Doherty power amplifier (DPA) architecture is proposed along with an analytical-based generic output combiner network design methodology. The load combiner provides the designer a choice to meet the optimum performance for any arbitrary back-off as well as for saturation. The PA’s performance is further optimized with digital input splitting. To verify the proposed theory, a 20-W symmetrical continuous mode DPA is designed using 10-W GaN HEMTs. The proposed amplifier shows a drain efficiency between 56.0% and 75.4% at 41.4–44.6 dBm saturation power and between 45% and 56.5% at 35.7–38.5 dBm output power corresponding to 6-dB back-off. This performance is achieved over the band from 1.25 to 2.3 GHz that corresponds to 59.15% fractional bandwidth. The proposed hybrid analog/digital continuous mode DPA prototype is implemented using field-programmable gate array (FPGA)/DSP platform and qualifies the spectral mask when excited by a modulated long term evolution signal along with digital predistortion.

2-μm double-pulse single-frequency Tm:fiber laser pumped Ho:YLF laser for a space-borne CO2 lidar.

In the framework of space-borne CO2 lidar development, the transmitter is a critical unit. We report on the development and the assessment of performances of a 2-μm single-frequency thulium fiber laser pumped Q-switched Ho:YLF laser. To fulfill the requirements of space-based operation, a master oscillator power amplifier architecture has been chosen, and the oscillator works in double-pulse operation. The transmitter can generate a single-mode dual wavelength emission "ON" and "OFF" around the R30e line of the 20013←00001 band of CO212. It delivers a pair of OFF-ON pulses with 12mJ and 42mJ energy, respectively, at a pulse repetition frequency of 303.5Hz. The pulse energy and central frequency stabilities are especially documented as well as pulse duration, polarization, overall efficiency, beam quality, pointing stability, and spectral purity. The possible limitations by light-induced damage or radiation-induced attenuation on the laser performances are also evaluated.

Analysis and Design of a Doherty-Like RF-Input Load Modulated Balanced Amplifier

This paper presents an analysis and design technique for an RF-input load modulated balanced amplifier (LMBA) with Doherty-like efficiency enhancement characteristics. The LMBA is a recently introduced power amplifier (PA) architecture in which a control signal is injected into the isolation port of the output coupler of a balanced amplifier. This control signal modulates the apparent load impedance of the two main devices. In the RF-input LMBA presented in this paper, the control signal is generated from the single-modulated RF input using a class-C control amplifier, producing an overall Doherty-like response. A complete theoretical analysis of the RF-input LMBA is presented, by assuming generalized networks for the output combiner and input splitter which are then solved in terms of transistor parameters and boundary conditions for high efficiency. Based on this analysis, a generalized design technique is presented. The LMBA is, thereby, shown to have advantages over the Doherty PA, including the device periphery scaling between the main and control devices for a given back-off range. The design technique is demonstrated at 2.4 GHz using packaged GaN devices. The prototype has a peak CW output power of 45.6 dBm, with a power-added efficiency of 60% at peak power and 50% at 6-dB output back-off, including the power dissipated by the control PA. A long-term evolution signal at 2.4 GHz with a 7.5-dB peak-to-average power ratio is demonstrated with an unlinearized ACLR of −27 dBc and an average drain efficiency of 47% for a 38-dBm average output power.

A Review of Advanced CMOS RF Power Amplifier Architecture Trends for Low Power 5G Wireless Networks

The structure of the modern wireless network evolves rapidly and maturing 4G networks pave the way to next generation 5G communication. A tendency of shifting from traditional high-power tower-mounted base stations towards heterogeneous elements can be spotted, which is mainly caused by the increase of annual wireless users and devices connected to the network. The radio frequency (RF) power amplifier (PA) performance directly affects the efficiency of any transmitter, therefore, the emerging 5G cellular network requires new PA architectures with improved efficiency without sacrificing linearity. A review of the most promising reported RF PA architectures is presented in this article, emphasizing advantages, disadvantages and concluding with a quantitative comparison. The main scope of reviewed papers are PAs implemented in scalable complementary metal–oxide–semiconductor (CMOS) and SiGe BiCMOS processes with output powers suitable for portable wireless devices under 32 dBm (1.5 W) in the low- and high- 5G network frequency ranges.

Monolithic CMOS sensor platform featuring an array of 9’216 carbon-nanotube-sensor elements and low-noise, wide-bandwidth and wide-dynamic-range readout circuitry

We present the design and characterization of a monolithic complementary metal–oxide–semiconductor (CMOS) biosensor platform comprising of a switch-matrix-based array of 9′216 carbon nanotube field-effect transistors (CNTFETs) and associated readout circuitry. The switch-matrix allows for flexible selection and simultaneous routing of 96 sensor elements to the corresponding readout channels. A low-noise, wide-bandwidth, wide-dynamic-range transimpedance continuous-time amplifier architecture has been implemented to facilitate resistance measurements in the range between 50 kΩ and 1 GΩ at a bandwidth of up to 1 MHz. The achieved accuracy of the resistance measurements over the whole range is 4%. The system has been successfully fabricated and tested and shows a noise performance equal to 2.14 pArms at a bandwidth of 1 kHz and 0.84 nArms at a bandwidth of 1 MHz. A batch integration of the CNTFETs has been achieved by using a dielectrophoresis (DEP)–based manipulation technique. The current-voltage curves of CNTFETs have been acquired, and the sensing capabilities of the system have been demonstrated by recording resistance changes of CNTFETs upon exposure to solutions with different pH values and different concentrations of NaCl. The smallest resolvable concentrations for the respective analytes were estimated to amount to 0.025 pH-units and 4 mM NaCl.

CMOS Image Sensor for Lateral Flow Immunoassay Readers

Point-of-care (POC) systems for the detection of infectious diseases are in great demand especially in developing countries. Lateral flow immunoassays are considered ideal biosensors for POC diagnostics due to their numerous advantages. However, to quantify their results a low power, robust electronic reader is needed. A low power CMOS image sensor is presented that can be used in quantitative lateral flow immunoassay readers. It uses a single low power processing capacitive transimpedance amplifier architecture which includes noise cancellation. A chip containing $4\times 64$ pixels was fabricated in CMOS 0.35- $\mu\text{m}$ technology. With uniform illumination at 525 nm and 67 frames/s the chip has 1.9 mVrms total output referred noise and a total power consumption of 21 $\mu\text{W}$ . In tests with lateral flow immunoassays the chip detected concentrations of influenza A nucleoprotein from 0.5 ng/mL to 200 ng/mL.