Amplifier Architecture Research Articles

A high-sensitivity flexible bionic tentacle sensor for multidimensional force sensing and autonomous obstacle avoidance applications

Bionic tentacle sensors are important in various fields, including obstacle avoidance, human‒machine interfaces, and soft robotics. However, most traditional tentacle sensors are based on rigid substrates, resulting in difficulty in detecting multidirectional forces originating from the external environment, which limits their application in complex environments. Herein, we proposed a high-sensitivity flexible bionic tentacle sensors (FBTSs). Specifically, the FBTS featured an ultrahigh sensitivity of 37.6 N−1 and an ultralow detection limit of 2.4 mN, which benefited from the design of a whisker-like signal amplifier and crossbeam architecture. Moreover, the FBTS exhibited favorable linearity (R2 = 0.98) and remarkable durability (more than 5000 cycles). This was determined according to the improvement in the uniformity of the sensing layer through a high-shear dispersion process. In addition, the FBTS could accurately distinguish the direction of external stimuli, resulting in the FBTS achieving roughness recognition, wind speed detection and autonomous obstacle avoidance. In particular, the ability of autonomous obstacle avoidance was suitably demonstrated by leading a bionic rat through a maze with the FBTS. Notably, the proposed FBTS could be widely applied in tactile sensing, orientation perception, and obstacle avoidance.

Dual-Band Low-Noise Amplifier for GNSS Applications

A new dual-band low-noise amplifier (LNA) operating at L1/E1 1.575 GHz and L5/E5 1.192 GHz center frequencies for global navigation satellite system receivers is proposed. A doubled common-source amplifier architecture is used with a single input, shared gate inductor, and two outputs to split the RF signal into separate RX channels. The main advantage of the proposed circuit is compatibility with widespread multi-band antennas with single RF connectors dedicated to high-precision applications, as well as the possibility to use cheap SAW filters with small footprints to build low-cost, highly accurate GNSS receiver modules. The input and both outputs are well matched to 50 Ω impedance. The LNA is designed with a 110 nm CMOS process, consuming 6.13 mA current from a 1.5 V supply. The measured noise figures and voltage gains of the dual-band LNA are, respectively, NF1/NF5 = 3.23/3.5 dB and G1/G5 = 21.22/18.2 dB in the band of interest for each channel. The measured impedance matching at the input (S11) and output (S22) of the dual-band low-frequency amplifier is as follows: S11_L1 = −23.89, S11_L5 = −8.42, S22_L1 = −12.65, S22_L5 = −15.08. The one-decibel compression points are L1 band PdB1 = −37.71 dBm and L5 band PdB5 = −34.72 dBm, respectively.

Design and Experimental Validation of a High-Efficiency Sequential Load Modulated Balanced Amplifier

The purpose of this paper is to present a detailed design procedure for a highly efficient sequential load-modulated balanced amplifier (SLMBA) to provide an in-depth analysis of this complex power amplifier (PA) architecture. SLMBA’s basic theory is presented and discussed. An SLMBA with a frequency range from 2.45 GHz to 2.65 GHz was implemented and then measured in order to validate the proposed design methodology. In both saturation and back-off states, the fabricated SLMBA exhibits extremely high efficiency and output power. It delivers a maximum output power of 43~44.4 dBm and a drain efficiency (DE) of 71.6~75% at saturation, a DE of 63.5~66% at 6 dB output back-off (OBO) state, a DE of 61.8~66% at 10 dB OBO state, and a DE of more than 51% at 12 dB OBO state in the targeted frequency band. The achieved results demonstrate the effectiveness of the proposed design procedure.

Amplification technology for spatial division multiplexing signals transmitted using multicore fibres

AbstractAmplification technologies needed for spatial division multiplexing (SDM) signal transmission have been reported, especially focusing on submarine systems, which have stricter requirements than terrestrial ones. As the first step of a large‐scale commercialisation, 2‐core un‐coupled (UC) fibre production has already been announced. However, optical amplifiers for SDM signals are still under investigation because SDM amplifiers have various architectural possibilities, depending on the requirements to be considered in designing systems. The multicore erbium‐doped fibre amplifier (MC‐EDFA) architecture is classified from the viewpoint of the number of erbium‐doped fibre (EDF) cores and its pumping method. Core pumped MC‐EDFA is more compatible with the conventional single‐core fibre (SCF)‐ based system and more mature than cladding pumped MC‐EDFA. However, cladding pumped MC‐EDFA has a unique feature of collective amplification of all cores in a single multicore fibre (MCF) and the potential of large‐scale integration of amplification cores in a single package. For a feasibility study, a C‐band 19‐core cladding pumped MC‐EDFA prototype is fabricated using a 19‐core isolator. A half volume of the equivalent conventional single‐core (SC‐) EDFA is successfully demonstrated. One unique feature of UC‐MCF is bidirectional (BD‐) transmission using a single UC‐MCF. Signal transmission direction can differ from core to core. This feature is useful for efficiently accommodating traffic of asymmetric communication data and expanding transmission capacity at a constant transmission distance. A C‐band 7‐core cladding pumped BD‐MC‐EDFA prototype is fabricated for the bidirectional MCF transmission line. Experimental results show transmission capacity was expanded by 17% using the prototype when bidirectional signal assignment was adapted. Towards practical use, optical components suitable for MC‐EDFA need to be developed to draw out potential advantages of SDM technologies.

0.36 μW/channel capacitively-coupled chopper instrumentation amplifier in EEG recording wearable devices for compressed sensing framework

We evaluated the effectiveness of a low-current-consumption amplifier for a compressed-sensing (CS) framework in wearable electroencephalography (EEG) recording devices. The amplifier uses a capacitively coupled chopper instrumentation amplifier (CCIA) architecture which is often used for low-noise amplifier (LNA) to achieve low consumption and low-noise characteristics. According to measurements of the designed CCIA, the power consumption was 0.36 μW/channel, and the input referred noise (IRN) was 4.47 μVrms. The measured IRN and simulations were used to confirm the effect of CCIA noise on the CS-based EEG measurement framework. The difference in the normalized mean squared error at CR = 4 to the uncompressed conditions could be reduced to 0.008. The findings show that even with the LNA specialized for low power consumption, a slight signal degradation is observed when the compression ratio is increased up to 4 in the CS framework by utilizing the sparsity of EEG in the frequency domain.

D-Band CMOS Power Amplifiers: Challenges, State-of-the-Art, Technological Limitations and Trends

To achieve ultra-high-speed wireless communications, millimeter-wave bands have emerged as bands of interest for these new applications. However, a technological breakthrough linked to power amplifiers has appeared. Indeed, working near the maximum oscillation frequency of the transistor leads to low intrinsic gain and poor efficiency for these devices. This paper presents an overview of sub-terahertz CMOS power amplifiers with a focus on gain enhancement techniques. The paper will also feature state-of-the-art D-Band CMOS power amplifier architectures. The goal is to present how the gain enhancement techniques are used in a complete architecture. Based on the three techniques and the state-of-the-art presented in the paper, a focus on three architectures is proposed. The aim is to highlight the benefits of each method in the design. The final part summarizes the paper and opens up future perspectives and trends identified through the paper.

Design of a Dual-Band Load-Modulated Sequential Amplifier with Extended Back-off

This letter presents a dual-band load-modulated sequential amplifier (LMSA). The proposed amplifier changed the attenuator terminated at the isolation port of the four-port combiner of the traditional sequential power amplifier (SPA) architecture into a reactance modulation network (RMN) for load modulation. The impedance can be maintained pure resistance by designing RMN, thus realizing high efficiency and a good portion of the output power in the multiple bands. Compared to the dual-band Doherty power amplifier with a complex dual-band load modulation network (LMN), the proposed LMSA has advantages as maintaining high output power back-off (OBO) efficiency, wide bandwidth and simple construction. A 10-watt dual-band LMSA is simulated and measured in 1.7-1.9 GHz and 2.4-2.6 GHz with saturated efficiencies 61.2-69.9% and 54.4-70.8%, respectively. The corresponding 9 dB OBO efficiency is 46.5-57.1% and 46.4-54.4%, respectively.

Dual-Band Dual-Output Four-Way Doherty Power Amplifier for Unsynchronized Time-Division Duplexing

This article proposes a dual-input dual-output dual-band four-way Doherty power amplifier (DPA) architecture, capable of linearized operation at one frequency band without being disturbed by arbitrary load switching at the other frequency band. The proposed technique is demonstrated through the design, implementation, and measurement of a prototype circuit operating at 1.85-and 2.65-GHz bands with 70-MHz bandwidth for each band. The prototype dual-band DPA (DB-DPA) achieves a peak output power of 49.1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 0.2 dBm for the 1.85-GHz band and 49.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 0.5 dBm for the 2.65-GHz band. Furthermore, the measured drain efficiency at 9-dB power back-off (PBO) is 59%–64% and 60%–65% for the 1.85-and 2.65-GHz bands, respectively. Concurrent dual-band performance, dynamic power sharing capability, and utility of the proposed DB-DPA in unsynchronized time-division duplexing (TDD) applications are demonstrated by using 20-MHz new radio (NR) signals with 9-dB peak-to-average power ratio (PAPR). For an average output power of 39 dBm per band, the concurrent dual-band measurement yields 49% average drain efficiency and better than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 48-dBc adjacent channel leakage ratio (ACLR).

Watt-level broadband PM Tm-doped fiber amplifier for the 1750–1910 nm window

We report broadband experimental and simulated performance of a single-clad polarization-maintaining (PM) thulium-doped fiber amplifier (TDFA) optimized for operation in the 1750–1910 nm wavelength band. With the two-stage amplifier architecture, a maximum output power of 2.4 W was obtained at 1850 nm for 7.0 W of launched pump power at 1567 nm, with a corresponding optical-to-optical efficiency of 31.4 %. The measured polarization extinction ratio (PER) was larger than 22.6 dB, and the long-term power stability exhibited a peak-to-peak variation of 2.4 %. By employing a tunable seed laser covering the 1750–1910 nm wavelength range, we measured a maximum output power level of 2.38 W with an optical signal-to-noise ratio (OSNR) greater than 53 dB/0.1 nm. Our simulations are in good agreement with the experimental data over the whole 160 nm operating spectral bandwidth.

A Wideband and Highly Efficient Circulator Load Modulated Power Amplifier Architecture

A complete theoretical analysis is presented for a highly efficient power amplifier (PA) architecture based on a non-reciprocal combiner. The architecture consists of two amplifier branches and a microwave circulator acting as the output combiner, referred to as the circulator load-modulated amplifier (CLMA). The continuous-mode (CM) design technique has been further exploited for the CLMA to demonstrate the wideband capabilities of the architecture. The analysis reveals that the CLMA performs active load modulation to maintain high PA efficiency performance across a wide bandwidth and large output power dynamic range. As a proof of concept, a CLMA demonstrator circuit based on gallium nitride (GaN) transistors and a microwave circulator, is designed and characterized with continuous-wave and modulated-signal measurements. The implemented CLMA prototype circuit experimentally demonstrates Doherty-like efficiency enhancement over a large bandwidth covering 2.1 to 3.5 GHz. In measurements, the prototype exhibits a drain efficiency of 46.7-57.5% at peak output power and 35.6-50.6% at 7-dB output power back-off level, within the design bandwidth. When tested with a 60-MHz multi-carrier orthogonal frequency-division multiplexing (OFDM) signal having a 7-dB peak-to-average power ratio (PAPR), an average efficiency of 48.5% with better than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 47.5-dBc adjacent channel leakage ratio (ACLR) is achieved after applying digital pre-distortion (DPD).

A Highly-Efficient Doherty Power Amplifier With Generalized Parallel-Circuit Class-EF Mode

In this letter, a highly-efficient Doherty power amplifier (DPA) architecture with generalized parallel-circuit class-EF mode is proposed. With this topology, the ideal harmonic impedance conditions at the deep power back-off (PBO) region and saturation region can remain the same. Based on it, by adding a single harmonic control network (HCN) and an offset line, the carrier PA can be operated at the ideal high-efficiency conditions within the above two regions. In this case, the overall efficiency of the DPA can be improved simultaneously. As an example, a high-efficiency DPA working at 2.6 GHz is designed and fabricated based on a Wolfspeed CGH40010F GaN HEMT transistor. The measured results of the proposed structure demonstrated that a drain efficiency (DE) of 76.7% with the peak outpower of 45.2 dBm, as well as DE of 74.8 % at the 6dB power back off region.

A High Dynamic Range Protein Sensing Platform for Low-Volume Magneto Immunoassay Automation

Immunoassays have been employed in diagnosing numerous diseases. Typically, these tests require a large volume of biofluid sample and overnight reaction. In this paper, a high dynamic range microfluidic protein sensing platform is presented. This platform reduces the required sample volume, expedites the reactions, and automatically controls the sample processing procedures. The platform includes a high-performance potentiostat circuit for redox signal acquisition, and an 8-channel polydimethylsiloxane (PDMS) microfluidic device for automatic sample processing. The sensing circuit employs a capacitive transimpedance amplifier (CTIA) architecture, which achieves low current noise (15.8pA), wide (116dB) dynamic range, and good linearity. The linearity of the whole platform is verified with electrochemical measurements using potassium ferricyanide (K3[Fe(CN)6]). The immunoassays are performed with patients’ serum samples and horseradish peroxidase (HRP)/3,3’,5,5’-tetramethylbenzidine (TMB) substrate-based assays. The limit-of-detection (LoD) of the whole system is 7pg/mL.

A novel triangular wave quadrature oscillator without passive components for sinusoidal pulse width modulation DC-AC power conversion

In this study, a low-cost quadrature triangle oscillator using a voltage-controlled closed-loop dual operational amplifier (Op-Amp) architecture is proposed. Unlike other typical designs, this oscillator does not require any passive components. The use of an Op-Amp-based circuit is attractive for a triangle oscillator because it is more cost-effective than a microcontroller-based solution. This is especially true for sinusoidal pulse width modulation (SPWM) DC-AC power conversion applications. The slew-rate restriction of an Op-Amp is a useful characteristic for producing a triangle waveform when seen from the perspective of wave shaping techniques. The MC4558 and the JRC4558D are two examples of dual Op-Amps that are evaluated, contrasted, and described in this article. At supply voltages of +7 V and -7 V, the suggested quadrature triangle oscillator that uses Op-Amps MC4558 and JRC4558D has the same oscillation frequency, which is 63 kHz, as demonstrated by simulation and experimental data. The frequency stability is estimated to be around 0.23%. In addition, the findings from the experiment demonstrate that the proposed oscillator is a practical solution for the SPWM DC-AC power conversion application.

Mutually coupled CG-CS current reuse low noise amplifier architecture for 4 – 14 GHz frequency

Abstract The current research paper presents a design of a mutually coupled cascode Common Gate Common Source (CG-CS) Low Noise Amplifier (LNA) using current reuse technique. The proposed design provides a significant improvement in the gain and noise performance of the LNA, while also reducing power consumption. Mutually coupled inductors help in reducing the size of the circuit while transformer connected at the output provide output impedance matching. Proposed LNA simulated for the 4–14 GHz RF frequency. Mathematical analysis of proposed LNA has been analyzed using the small signal model henceforth input impedance; gain and Noise Figure (NF) have been derived from it. The design and simulation results show that the proposed LNA design with current reuse technique achieved a maximum gain of 17.87 dB, minimum NF of 5.45 dB, and input reflection coefficient less than –10 dB for the 10 GHz bandwidth. These results indicate a significant improvement in the overall performance of the LNA compared to conventional designs as Figure of Merit (FoM) is 17.34.

Ultra-Low Power Programmable Bandwidth Capacitively-Coupled Chopper Instrumentation Amplifier Using 0.2 V Supply for Biomedical Applications

This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used in the CCIA. By using a Squeezed inverter amplifier (SQI) that employs a 0.2-V supply, the proposed CCIA addresses the primary noise source in the first stage, resulting in high noise power efficiency. The proposed CCIA is designed using a 0.18 µm CMOS technology process and has a chip area of 0.083 mm2. With a power consumption of 0.47 µW at 0.2 and 0.8 V supply, the proposed amplifier architecture achieves a thermal noise of 28 nV/√Hz, an input-related noise (IRN) of 0.9 µVrms, a closed-loop gain (AV) of 40 dB, a power supply rejection ratio (PSRR) of 87.6 dB, and a common-mode rejection ratio (CMRR) of 117.7 dB according to post-simulation data. The proposed CCIA achieves a noise efficiency factor (NEF) of 1.47 and a power efficiency factor (PEF) of 0.56, which allows comparison with the latest research results.

Fabrication of a tellurite-fiber-based side-pump coupler based on the tapered-fused method.

In this study, (1 + 1) × 1 side-pump couplers made of tellurite fibers were fabricated and investigated. The whole optical design of the coupler was established on the basis of ray tracing models and validated by experimental results. By optimizing the preparation conditions and structural parameters, the tested component achieved a coupling efficiency of 67.52% and an insertion loss of 0.52 dB. To the best of our knowledge, this is the first time a tellurite-fiber-based side-pump coupler was developed. The fused coupler presented will simplify many mid-infrared fiber lasers or amplifier architectures.

A Fully Differential Difference Transconductance Amplifier Topology Based on CMOS Inverters

This manuscript presents a fully differential difference transconductance amplifier (FDDTA) architecture based on CMOS inverters. Designed in a 130-nm CMOS process it operates in weak inversion when supplied with 0.25 V. In addition, the FDDTA requires no supplementary external calibration circuit, like tail current or bias voltage sources, since it relies on the distributed layout technique that intrinsically matches the CMOS inverters. For analytical purposes, we carried out a detailed investigation that describes all the concepts and the whole operation of the FDDTA architecture. Furthermore, a comparison between the modeling equations and measured data assures high performance.

Load-Modulating Loop Combiner for Linear Power Amplification

This work presents a novel power amplifier (PA) architecture employing a feedforward-like loop structure for the linearization of a load-modulated PA. The load-modulating loop combiner (LMLC) is related to a feedforward amplifier, but with the interaction between the main and auxiliary amplifiers to generate both distortion cancellation and load modulation. A brief overview of the underlying theory is presented, followed by a hardware demonstrator operating at 3.5 GHz with 42-dBm peak output power and 55% peak drain efficiency in CW. When excited by a 100-MHz LTE signal, it maintains a 3-ppt EVM improvement and a 2–5-ppt average drain efficiency improvement compared to its standalone main amplifier.

Analog Lock-In Amplifier Design Using Subsampling for Accuracy Enhancement in GMI Sensor Applications.

A frequency downscaling technique for enhancing the accuracy of analog lock-in amplifier (LIA) architectures in giant magneto-impedance (GMI) sensor applications is presented in this paper. As a proof of concept, the proposed method is applied to two different LIA topologies using, respectively, analog and switching-based multiplication for phase-sensitive detection. Specifically, the operation frequency of both the input and the reference signals of the phase-sensitive detector (PSD) block of the LIA is reduced through a subsampling process using sample-and-hold (SH) circuits. A frequency downscaling from 200 kHz, which is the optimal operating frequency of the employed GMI sensor, to 1 kHz has been performed. In this way, the proposed technique exploits the inherent advantages of analog signal multiplication at low frequencies, while the principle of operation of the PSD remains unaltered. The circuits were assembled using discrete components, and the frequency downscaling proposal was experimentally validated by comparing the measurement accuracy with the equivalent conventional circuits. The experimental results revealed that the error in the signal magnitude measurements was reduced by a factor of 8 in the case of the analog multipliers and by a factor of 21 when a PSD based on switched multipliers was used. The error in-phase detection using a two-phase LIA was also reduced by more than 25%.

A 44–64-GHz mmWave Broadband Linear Doherty PA in Silicon With Quadrature Hybrid Combiner and Non-Foster Impedance Tuner

The proliferation of millimeter-wave (mmWave) bands across 24–90 GHz and the strict spectral efficiency requirements demand future transmitter front ends to operate across multiple bands with simultaneously back-off efficiency and high linearity—characteristics that typically trade off strongly with each other. In this article, we propose a simultaneously broadband, back-off efficient and linear mmWave Doherty power amplifier (PA) architecture with a quadrature hybrid, and a non-Foster inspired impedance tuner on-chip. The combination of transformer-based hybrid and the quasi-non-Foster tuner allows the architecture to synthesize optimal impedances to the PA across the 2-D variations of power back-off and frequency, enabling high back-off efficiency across a broad frequency range. In addition, the unique location of the tuner at the isolation port of the hybrid allows us to exploit its benefits while shielding the architecture from effects of tuner non-linearity, power losses, and typical stability concerns of traditional non-Foster circuits. For high linearity, we implement an emitter follower-based class-C bias network with boosting effect. The PA is implemented in a 130-nm SiGe BiCMOS process. Across 44–64 GHz, the PA achieves 18.5–21.5-dBm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {sat}}$ </tex-math></inline-formula> , the peak collector efficiency of 26%–34.7% and 14%–23.2% at 6-dB back-off, maintaining back-off enhancement ratio of 2.77/2.53/2.37 (1.39/1.27/1.19) at 46/52/62 GHz compared to the class-A (class-B) operation. It supports 6-gigabit-per-second (Gb/s) 64-QAM signal with −26.5-dB/−28.3-dBc error vector magnitude (EVM)/adjacent channel leakage ratio (ACLR) at average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {out}}$ </tex-math></inline-formula> /power added efficiency (PAE) of 14.6 dBm/15% at 54 GHz. This work achieves the state-of-the-art bandwidth among silicon-based mmWave PAs where higher than class-B back-off efficiency is achieved.