Amorphous Oxide Thin-film Transistors Research Articles

Trap Assessment and Mobility Simulation of Amorphous Indium Gallium Zinc Oxide Thin Film Transistors

Ultra-broadband photoconduction (UBPC) is used to measure the sub-gap trap density of amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) across the bandgap, from the valence band mobility edge to within 0.15 eV (~6kBT) of the conduction band mobility edge. Figure (a) is a plot of the total integrated trap density (Ntraps, green) and the sub-gap density of states (dNtraps/dE, blue) as measured by UBPC for traps located just below the conduction band mobility edge (E-EC = 0). Three Gaussian sub-gap states are observed with peak energies of 0.9, 0.7, and 0.4 eV below the conduction band mobility edge. Note that the width of the 0.4 eV peak (180 meV) is much larger than that of the other two deeper peaks (45 meV). All three of these peaks are likely associated with oxygen vacancies, but it is unclear why the 0.4 eV trap is so much broader than all the other deeper oxygen vacancy derived donor trap states.The black dotted curves included in Figure (b) are experimental EKV mobility (μEKV) versus overvoltage (VG-VON) plots obtained at three different temperatures (0 °, 20 °, and 100 °C). The red dashed curves are simulated mobility curves obtained assuming that only conduction band tail states act as electron traps to degrade the mobility. Since these red simulated curves grossly overestimate the experimental mobility, other traps must be operative in establishing the black experimental mobility curves. In fact, the inclusion of the 0.4 eV trap measured by UBPC in addition to the conduction band tail states in the simulation (blue curves) leads to excellent agreement between experimental and simulated mobility for all three temperatures (0 °, 20 °, and 100 °C). In summary, it is demonstrated how the mobility of a-IGZO can be simulated by including the experimentally observed DoS of a 0.4 eV centered Gaussian trap state.

Interfacial thermal resistance effect in self-aligned top-gate a-IGZO thin film transistors

This study investigates the interfacial thermal resistance effect, primarily associated with the bottom-gate stack, in self-aligned top-gate amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). We analyze self-heating and heat transfer characteristics across three different a-IGZO TFT configurations: single-gate, dual-gate type 1, and dual-gate type 2. Temperature maps, corresponding to various bias conditions, are acquired using infrared thermal microscopy. The extracted values of thermal resistance reveal a significant disparity between single- and dual-gate configurations. This suggests that the bottom-gate stack in a-IGZO TFTs, including the interfaces, notably impedes heat dissipation. These findings offer crucial insights into the power dissipation aspects of TFT technology, highlighting the importance of interfacial design for thermal management in advanced electronic devices.

The Enhanced Performance of Oxide Thin-Film Transistors Fabricated by a Two-Step Deposition Pressure Process.

It is usually difficult to realize high mobility together with a low threshold voltage and good stability for amorphous oxide thin-film transistors (TFTs). In addition, a low fabrication temperature is preferred in terms of enhancing compatibility with the back end of line of the device. In this study, α-IGZO TFTs were prepared by high-power impulse magnetron sputtering (HiPIMS) at room temperature. The channel was prepared under a two-step deposition pressure process to modulate its electrical properties. X-ray photoelectron spectra revealed that the front-channel has a lower Ga content and a higher oxygen vacancy concentration than the back-channel. This process has the advantage of balancing high mobility and a low threshold voltage of the TFT when compared with a conventional homogeneous channel. It also has a simpler fabrication process than that of a dual active layer comprising heterogeneous materials. The HiPIMS process has the advantage of being a low temperature process for oxide TFTs.

High Performance Amorphous IGO Thin Film Transistors Grown at Low Temperature

Polycrystalline indium gallium oxide has been widely studied in the domain of oxide thin film transistors (TFTs) due to its high mobility. However, there are few researches focus on amorphous IGO (a‐IGO), which has the advantage of large area display. Herein, high‐performance a‐IGO TFTs are demonstrated by magnetron sputtering method with simple process. The efficiency of a‐IGO TFTs fabricated under various conditions are evaluated, and a‐IGO TFTs prepared by 27 nm thin films grown at 220 °C have the best electrical properties. It exhibits the mobility of 35 cm2 V−1 s−1, threshold voltage of 0.5 V, subthreshold swing of 0.8 V dec−1, and the on/off current ratio over 106. This is due to the precise control of the deposition energy state by temperature during sputtering and the influence of the semiconductor layer thickness on the distribution of the accumulation layer. The results present here demonstrate a simple fabrication method for high‐performance amorphous oxide TFT, providing a new option for display driver circuits.

Strengthening Multi-Factor Authentication Through Physically Unclonable Functions in PVDF-HFP-Phase-Dependent a-IGZO Thin-Film Transistors.

For enhanced security in hardware-based security devices, it is essential to extract various independent characteristics from a single device to generate multiple keys based on specific values. Additionally, the secure destruction of authentication information is crucial for the integrity of the data. Doped amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) using poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF-HFP) induce a dipole doping effect through a phase-transition process, creating physically unclonable function (PUF) devices for secure user information protection. The PUF security key, generated at VGS = 20V in a 20×10 grid, demonstrates uniformity of 42% and inter-Hamming distance (inter-HD) of 49.79% in the β-phase of PVDF-HFP. However, in the γ-phase, the uniformity drops to 22.5%, and inter-HD decreases to 35.74%, indicating potential security key destruction during the phase transition. To enhance security, a multi-factor authentication (MFA) system is integrated, utilizing five security keys extracted from various TFT parameters. The security keys from turn-on voltage (VON), VGS = 20V, VGS = 30V, mobility, and threshold voltage (Vth) exhibit near-ideal uniformities and inter-HDs, with the highest values of 58% and 51.68%, respectively. The dual security system, combining phase transition and MFA, establishes a robust protection mechanism for privacy-sensitive user information.

Effect of sputtering working pressure on the reliability and performance of amorphous indium gallium zinc oxide thin film transistors

In this study, the reliability and electrical properties of indium gallium zinc oxide (IGZO) thin film transistors (TFTs) are investigated when the working pressure of the sputtering system is varied. As IGZO is deposited at a low working pressure, the sputtering yield increases and the film density increases from 5.84 to 6.00 g/cm3 based on x-ray reflectivity measurements. IGZO TFT sputtered at low working pressure has a mobility of 8.05 cm2/V s, a threshold voltage of 1.25 V, and a subthreshold swing of 0.25 V/dec. In addition, x-ray photoelectron spectroscopy analysis shows that the oxygen content in the film decreases when IGZO is deposited at a low working pressure, resulting in improved positive bias stress reliability due to the oxygen-poor film. Furthermore, the IGZO film deposited at a low working pressure effectively prevents the formation of defects caused by the environment such as H2O molecules.

Design and simulation of a nano biosensor based on amorphous indium gallium zinc oxide (a-IGZO) thin film transistor

In this study, a biosensor utilizing a dielectric-modulated amorphous indium gallium zinc oxide (a-IGZO) thin film transistor (TFT) is introduced. TFT biosensors have garnered significant attention due to their heightened sensitivity, scalable nature, low power consumption, rapid electrical detection capabilities, and cost-effective means of mass production. By embedding a nano-cavity within the gate insulator of the TFT, biomolecules can accumulate within. As each biomolecule possesses its own dielectric constant, it modulates the effective gate capacitance and, subsequently, changes the channel conductance. To assess the sensitivity of the biosensor, variation in saturation current after the absorption of biomolecules with respect to the drain current in the case of an air-filled cavity has been considered as a precise measure. The efficient operation of a biosensor is contingent upon the sensitivity being highly dependent on the dielectric constant of the biomolecules that are accumulated within the nano-cavity. Consequently, a comprehensive evaluation has been conducted to ascertain the impact of critical design parameters which have the potential to affect the sensitivity of the biosensor. Additionally, a statistical analysis based on coefficient of variation measure has been performed to evaluate the susceptibility of the biosensor’s sensitivity to variations in geometrical and physical design parameters. The utilization of label-free detection methodology in this device presents a notable advantage due to its compatibility with the fundamental CMOS processing technology and its cost-effective potential for macro production.

Dual Role of AgNO3 as an Oxidizer and Chloride Remover toward Enhanced Combustion Synthesis of Low-Voltage and Low-Temperature Amorphous Rare Metal-Free Oxide Thin-Film Transistors

Dual Role of AgNO₃ as an Oxidizer and Chloride Remover toward Enhanced Combustion Synthesis of Low-Voltage and Low-Temperature Amorphous Rare Metal-Free Oxide Thin-Film Transistors

Physical modeling for photo-capacitance characteristics of metal oxide TFTs

We propose an amorphous metal oxide thin film transistor photo-capacitance model in the depletion region that takes Fermi level splitting and band-bending rearrangement into consideration. The split Fermi level is used to characterize the variation in trapped electrons under illumination. Those trapped electrons are excited by optical energy transport under the electric field induced by gate voltage, changing the charge density in the space charge and inducing the rearrangement of band bending. By comparing the data calculated from the model with the test data under three different illumination conditions, that is, 808, 635, and 520 nm, we verify the correctness of this model. Furthermore, the fitting results were in accordance with the general law: the higher the photon energy, the higher the energy level splitting.

Visualization of Mesoscopic Conductivity Fluctuations in Amorphous Semiconductor Thin-Film Transistors.

Charge transport in amorphous semiconductors is considerably more complicated than the process in crystalline materials due to abundant localized states. In addition to device-scale characterization, spatially resolved measurements are important to unveiling electronic properties. Here, we report gigahertz conductivity mapping in amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors by microwave impedance microscopy (MIM), which probes conductivity without Schottky barrier's influence. The difference between the dc and microwave conductivities reflects the efficacy of the injection barrier in an accumulation-mode transistor. The conductivity exhibits significant nanoscale inhomogeneity in the subthreshold regime, presumably due to trapping and release from localized states. The characteristic length scale of local fluctuations, as determined by the autocorrelation analysis, is about 200 nm. Using a random-barrier model, we can simulate the spatial variation of the potential landscape, which underlies the mesoscopic conductivity distribution. Our work provides an intuitive way to understand the charge transport mechanism in amorphous semiconductors at the microscopic level.

PEALD deposited aluminum hafnium mixed oxide dielectrics for amorphous-IGZO TFTs

(Al–Hf) mixed oxide thin films (HfAlO) are attracted by many researchers because of their outstanding optical and electrical properties compared to hafnium oxide (HfO2). This study prepared HfAlO films at 300 °C using plasma-enhanced atomic layer deposition (PEALD). Changing the cycle ratio of HfO2 and aluminum oxide (Al2O3), the mixing effect on the properties of HfAlO film was studied. The characterization of the HfAlO films was investigated using spectroscopic ellipsometry (SE), X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), X-ray reflectivity (XRR), scanning electron microscopy (SEM), and UV–vis spectroscopy. The results show that the aluminum content and optical bandgap of the HfAlO films increased with the increase of the Al2O3 cycle ratio. The dielectric constant of the HfAlO film with a 20 % Al2O3 cycle ratio (cycles of Al2O3/(cycles of Al2O3 + cycles of HfO2)) reaches ∼ 26, and the breakdown electric field is about 6.5 MV/cm. Pure HfO2 and 20 % Al2O3 cycle ratio deposited HfAlO was used as the gate dielectric layer, and the influence on the performance of amorphous indium gallium zinc oxide (a-IGZO) thin film transistor (TFT) was studied. A-IGZO TFT with a 20 % Al2O3 cycle ratio mixed HfAlO film as the gate dielectric exhibits the best performance, showing a high Ion/Ioff ratio of 1.3 × 109, a saturation mobility of ∼5.8 cm2/Vs, a subthreshold slope of 88 mV per decade and a low threshold voltage of −0.1V.

Indium Zinc Oxide Nanosheet Transistor With 2 nm Channel Thickness for Monolithic Three-Dimensional Integrated Circuit

We have successfully fabricated an amorphous indium zinc oxide (a-IZO) thin film transistor (TFT) with a 2 nm-thick nanosheet channel, which demonstrated an impressive mobility of 84 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V-s. By shrinking the channel length and width, the a-IZO TFT exhibited a high drain current density of 1.6 mA/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> = 1V, a sharper subthreshold swing of 72 mV/dec, and better drain-induced barrier lowering (DIBL) of 94 mV/V. By integrating p-type low-temperature poly-Si (LTPS) TFT and n-type a-IZO TFT, we have designed a heterogeneous complementary inverter that can achieve a high voltage gain of 99 V/V, while consuming only a few picowatts of power at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1.5 V. All thermal budgets used in this study are compatible with the back-end-of-line (BEOL) process, making it a suitable approach for fabricating monolithic three-dimensional integrated circuits (M3D-ICs).

Low-Temperature Enhancement-Mode Amorphous Oxide Thin-Film Transistors in Solution Process Using a Low-Pressure Annealing.

The interest in low processing temperature for printable transistors is rapidly increasing with the introduction of a new form factor in electronics and the growing importance of high throughput. This paper reports the fabrication of low-temperature-processable enhancement-mode amorphous oxide thin-film transistors (TFTs) using the solution process. A facile low-pressure annealing (LPA) method is proposed for the activation of indium oxide (InOx) semiconductors at a significantly low processing temperature of 200 °C. Thermal annealing at a pressure of about ~10 Torr induces effective condensation in InOx even at a low temperature. As a result, the fabricated LPA InOx TFTs not only functioned in enhancement mode but also exhibited outstanding switching characteristics with a high on/off current ratio of 4.91 × 109. Furthermore, the LPA InOx TFTs exhibit stable operation under bias stress compared to the control device due to the low concentration of hydroxyl defects.

Homojunction structure amorphous oxide thin film transistors with ultra-high mobility

Amorphous oxide semiconductors (AOS) have unique advantages in transparent and flexible thin film transistors (TFTs) applications, compared to low-temperature polycrystalline-Si (LTPS). However, intrinsic AOS TFTs are difficult to obtain field-effect mobility (μ FE) higher than LTPS (100 cm2/(V·s)). Here, we design ZnAlSnO (ZATO) homojunction structure TFTs to obtain μ FE = 113.8 cm2/(V·s). The device demonstrates optimized comprehensive electrical properties with an off-current of about 1.5 × 10–11 A, a threshold voltage of –1.71 V, and a subthreshold swing of 0.372 V/dec. There are two kinds of gradient coupled in the homojunction active layer, which are micro-crystallization and carrier suppressor concentration gradient distribution so that the device can reduce off-current and shift the threshold voltage positively while maintaining high field-effect mobility. Our research in the homojunction active layer points to a promising direction for obtaining excellent-performance AOS TFTs.

A Pixel Circuit for Compensating Electrical Characteristics Variation and OLED Degradation

In recent years, the active-matrix organic light-emitting diode (AMOLED) displays have been greatly required. A voltage compensation pixel circuit based on an amorphous indium gallium zinc oxide thin-film transistor is presented for AMOLED displays. The circuit is composed of five transistors–two capacitors (5T2C) in combination with an OLED. In the circuit, the threshold voltages of both the transistor and the OLED are extracted simultaneously in the threshold voltage extraction stage, and the mobility-related discharge voltage is generated in the data input stage. The circuit not only can compensate the electrical characteristics variation, i.e., the threshold voltage variation and mobility variation, but also can compensate the OLED degradation. Furthermore, the circuit can prevent the OLED flicker, and can achieve the wide data voltage range. The circuit simulation results show that the OLED current error rates (CERs) are lower than 3.89% when the transistor’s threshold voltage variation is ±0.5V, lower than 3.49% when the mobility variation is ±30%.

Enhancement of electrical properties of a-IGZO thin film transistor by low temperature (150 °C) microwave annealing for flexible electronics

A relatively low-temperature process is required to fabricate amorphous oxide thin film transistor (TFT) display backplanes for flexible electronics. However, in order to ensure the outstanding electrical property of TFT, a typical post-annealing process should be performed at 300 °C or above. This is not compatible with flexible substrates in the process. In our work, we applied microwave annealing (MWA) at a low-temperature (150 °C) to the oxide TFT and verified its feasibility through the evaluation of various electrical properties. Even an a-IGZO TFT by MWA at such a low-temperature shows high mobility (29.0 cm2/V s) by DC ID-VG measurement, which is 4 ∼ 5 times higher than other counterparts, indicating that the MWA process is very effective to minimize the defects in an oxide semiconductor channel. To further investigate the intrinsic mobility of TFT with negligible charge trapping, we carried out fast and pulse ID-VG measurement methods. The intrinsic mobility extracted from this measurement is found to be 35.3 cm2/V s, 21.7% higher than that of DC ID-VG. We are expecting that the low-temperature MWA process would be widely used for the process of oxide TFT in a flexible platform.

산화물 박막 소자의 단기 열화 특성 분석 및 예측식 모델링

Gate bias stress can change the threshold voltage of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT). Especially, short-term degradation of threshold voltage should be compensated since it causes motion artifacts in the display. Therefore, a new short-term degradation model was proposed based on the stretched-exponential model. Moreover, the accuracy of the proposed model was confirmed by calculating the coefficient of determination between the measured data and the fitted data.

High-Performance Amorphous InGaSnO Thin-Film Transistor with ZrAlOx Gate Insulator by Spray Pyrolysis

Here, we report the high-performance amorphous gallium indium tin oxide (a-IGTO) thin-film transistor (TFT) with zirconium aluminum oxide (ZAO) gate insulator by spray pyrolysis. The Ga ratio in the IGTO precursor solution varied up to 20%. The spray pyrolyzed a-IGTO with a high-k ZAO gate insulator (GI) exhibits the field-effect mobility (μFE) of 16 cm2V−1s−1, threshold voltage (VTH) of −0.45 V subthreshold swing (SS) of 133 mV/dec., and ON/OFF current ratio of ~108. The optimal a-IGTO TFT shows excellent stability under positive-bias-temperature stress (PBTS) with a small ΔVTH shift of 0.35 V. The enhancements are due to the high film quality and fewer interfacial traps at the a-IGTO/ZAO interface. Therefore, the spray pyrolyzed a-IGTO TFT can be a promising candidate for flexible TFT in the next-generation display.

Fully Transparent and Highly Sensitive pH Sensor Based on an a-IGZO Thin-Film Transistor with Coplanar Dual-Gate on Flexible Polyimide Substrates

In this paper, we propose a fully transparent and flexible high-performance pH sensor based on an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) transducer with a coplanar dual-gate structure on polyimide substrates. The proposed pH sensor system features a transducer unit consisting of a floating gate (FG), sensing gate (SG), and control gate (CG) on a polyimide (PI), and an extended gate (EG) sensing unit on a separate glass substrate. We designed a capacitive coupling between (SG) and (CG) through the FG of an a-IGZO TFT transducer to contribute to sensitivity amplification. The capacitance ratio (CSG/CCG) increases linearly with the area ratio; therefore, the amplification ratio of the pH sensitivity was easily controlled using the area ratio of SG/CG. The proposed sensor system improved the pH sensitivity by up to 359.28 mV/pH (CSG/CCG = 6.16) at room temperature (300 K), which is significantly larger than the Nernstian limit of 59.14 mV/pH. In addition, the non-ideal behavior, including hysteresis and drift effects, was evaluated to ensure stability and reliability. The amplification of sensitivity based on capacitive coupling was much higher than the increase in the hysteresis voltage and drift rate. Furthermore, we verified the flexibility of the a-IGZO coplanar dual-gate TFT transducer through a bending test, and the electrical properties were maintained without mechanical damage, even after repeated bending. Therefore, the proposed fully transparent and highly sensitive a-IGZO coplanar dual-gate TFT-based pH sensor could be a promising wearable and portable high-performance chemical sensor platform.

Effect of passivation layer on back channel etching InGaZnO thin film transistors

Amorphous indium gallium zinc oxide (IGZO) thin film transistors (TFT) are widely used in active-matrix displays because of their excellent stability, low off-current, high field-effect mobility, and good process compatibility. Among IGZO TFT device structures, back channel etching (BCE) is favorable due to low production cost, short channel length and small SD-to-gate capacitance. In this work, prepared are the BCE IGZO TFTs each with the passivation layer of silicon dioxide (SiO&lt;sub&gt;2&lt;/sub&gt;), polyimide (PI) or SiO&lt;sub&gt;2&lt;/sub&gt;-PI stacked structure to study their difference in back channel hydrogen impurity and diffusion behavior. Comparing with the conventional SiO&lt;sub&gt;2&lt;/sub&gt; passivation BCE TFT, the performance of PI passivation TFT is improved greatly, specifically, the saturation field effect mobility increases from 4.7 to 22.4 cm&lt;sup&gt;2&lt;/sup&gt;/(V·s), subthreshold swing decreases from 1.6 to 0.28 V/decade, and the an on-off current ratio rises dramatically from 1.1×10&lt;sup&gt;7&lt;/sup&gt; to 1.5×10&lt;sup&gt;10&lt;/sup&gt;. After the SiO&lt;sub&gt;2&lt;/sub&gt; passivation layer is substituted with PI, the I&lt;sub&gt; off&lt;/sub&gt; decreases from 10&lt;sup&gt;–11&lt;/sup&gt; A to 10&lt;sup&gt;–14&lt;/sup&gt; A, which indicates that there exist less shallow-level donor states of hydrogen impurities, which might be explained by the following three mechanisms: first, in the film formation process of PI, the direct incorporation of hydrogen-related radicals from SiH&lt;sub&gt;4&lt;/sub&gt; precursor into the back channel is avoided; second, the hydrogen content in the PI film is lower and harder to diffuse into the back channel; third, the hydrogen impurity of back channel that is introduced by the H&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;2&lt;/sub&gt;-based etchant in the SD etching process could diffuse more easily toward the PI layer. The TFTs with PI passivation layer also shows the less electrical degradation after the annealing treatment at 380 ℃ and better output performance, which confirms less defects and higher quality of the back channel. The bias stabilities of PI devices are improved comprehensively, especially negative bias illumination stability with the threshold voltage shifting from –4.8 V to –0.7 V, which might be attributed to the disappearance of hydrogen interstitial sites and hydrogen vacancies that are charged positively in the back channel. The PI passivation layer is effective to avoid back channel hydrogen impurities of BCE TFT and promises to have broad applications in the display industry.