Alternative Device Structures Research Articles

The Secret Ingredient for Exceptional Contact‐Controlled Transistors

AbstractContact‐controlled transistors are rapidly gaining popularity. However, simply using a rectifying source contact often leads to unsatisfactory operation, merely as a thin‐film transistor with low drain current and reduced effective mobility. This may cause otherwise promising experiments to be abandoned. Here, data from literature is analyzed in conjunction with devices that have been recently fabricated in polysilicon, organic and oxide semiconductors, highlighting the main factor in achieving good saturation, namely keeping saturation coefficient γ well below 0.3. Secondary causes of suboptimal electrical characteristics are also discussed. Correct design of these alternative device structures will expedite their adoption for high gain, low‐frequency applications in emerging sensor circuits.

Robust Impact-Ionization Field-Effect Transistor Based on Nanoscale Vertical Graphene/Black Phosphorus/Indium Selenide Heterostructures.

Maintaining the rapid development of information technology by scaling down a metal-oxide semiconductor field-effect transistor faces two serious challenges. First, the gate field loses control of the channel as it continuously decreases. Second, the fundamental thermionic limit restricts the reduction in supply voltage. Thus, further scaling down necessitates alternative device structures and different switching mechanisms. Here, we report impact-ionization transistors (IITs) based on nanoscale (∼30 nm) vertical graphene/black phosphorus (BP)/indium selenide (InSe) heterostructures. By facilitating the carrier multiplication of the ballistic impact-ionization process as the internal gain mechanism in sub-mean-free-path (sub-MFP) channels, the IITs exhibit a low average subthreshold swing (SS < 1 mV/dec) over five current levels. High stability (>10 000 cycles) and small hysteresis (<1%) switching properties are also obtained. The experimental demonstration of such transistor combining steep SS, high ON-state current density, reliable robustness, miniature footprint, and low bias voltage approaches fulfillments of targets for next-generation devices in the International Technology Roadmap for Semiconductors.

Role of direct and inverted undoped spiro-OMeTAD-perovskite architectures in determining solar cells performances: an investigation via electrical impedance spectroscopy.

The present study involved an investigation on the reasoning behind the dependence of the perovskite solar cells photovoltaic efficiencies on the relative position of the undoped spiro-OMeTAD hole-transport material with respect to the perovskite in the device. We adopted impedance spectroscopy to investigate the modification of the carrier transport mechanisms across the spiro-OMeTAD/perovskite interface constituting the active part where the main device processes occur. We investigated two interface structures, referred to as the direct (or regular, n-i-p) and the inverted (p-i-n) configuration. This work also intended to further stress the possible adoption of alternative device structures working with undoped hole-transport materials.

2D analytical modeling and simulation of dual material DG MOSFET for biosensing application

In the recent times, the performance of MOSFET in the nanoscaled region attains improvisations through several alternative device structures. Amongst many advanced MOSFET structures, the Double Gate (DG) MOSFET is one such structure which mitigates short channel effects because of its excellent scalability. Among the various structures, FET- based biosensors have shown an accelerated growth recently. Even though many analytical models are available for the Dual Material DG (DMDG) MOSFET structures, this work endeavours to introduce an analytical modeling of nanocavity embedded DMDG structure for the first time. The expression for surface potential is obtained by solving the 2-D Poisson’s equation using a parabolic-potential approach. The threshold voltage is determined from the minimum surface potential model. Sensitivity is computed in terms of relative change in the threshold voltage and it is derived using the model. The influence of various device geometrical parameters like length and thickness of the nanocavity on the sensitivity has been investigated. Further, a comparison of the sensitivity of DG MOSFET and DMDG MOSFET has also been made and the derived results are validated against TCAD simulation results.

Materials for Energy Harvesting

This special issue of physica status solidi (a) contains a selection of papers with contributions related to Materials for Energy Harvesting originated from research and innovation projects as presented at the EUROMAT conference in Thessaloniki (September 17–22, 2017). The papers include results of ongoing research and recent scientific achievements within the fields of photovoltaic and thermoelectric materials. Emphasis is given on selected innovative solutions and technological initiatives related to most promising materials and associated device structures, which are under consideration in many research groups worldwide. The field of photovoltaics is briefly covered with respect to advanced silicon based material structures as well as potential “post silicon” alternatives such as kesterites and perovskites. For each type of the photovoltaic materials mentioned above, advanced characterization methods as well as selected innovative technological processing steps are presented. Various alternative thermoelectric materials and related device structures are also presented in this issue including silicides and skutterudites. Consideration of several competing materials toward cost effective options in the processing of photovoltaic and thermoelectric advanced structures reflects current trends and status in the field of this category of energy harvesting materials. Despite the remarkable progress related to PV/thermoelectric advanced structures and concepts demonstrated during last decades, further developments and comparative analysis targeting to cost reduction as well as increase of fundamental efficiency limits are still required. The Guest Editors

Contact resistance at planar metal contacts on bilayer graphene and effects of molecular insertion layers

The possible origins of metal–bilayer graphene (BLG) contact resistance are investigated by taking into consideration the bandgap formed by interfacial charge transfer at the metal contacts. Our results show that a charge injection barrier (Schottky barrier) does not contribute to the contact resistance because the BLG under the contacts is always degenerately doped. We also showed that the contact-doping-induced increase in the density of states (DOS) of BLG under the metal contacts decreases the contact resistance owing to enhanced charge carrier tunnelling at the contacts. The contact doping can be enhanced by inserting molecular dopant layers into the metal contacts. However, carrier tunnelling through the insertion layer increases the contact resistance, and thus, alternative device structures should be employed. Finally, we showed that the inter-band transport by variable range hopping via in-gap states is the largest contributor to contact resistance when the carrier type of the gated channel is opposite to the contact doping carrier type. This indicates that the strategy of contact resistance reduction by the contact-doping-induced increase in the DOS is effective only for a single channel transport branch (n- or p-type) depending on the contact doping carrier type.

Alternative device structures for CIGS-based solar cells with semi-transparent absorbers

Abstract In this work, we discuss two alternative structures of CIGS-based solar cells, a bi-facial configuration and a back-wall configuration. One of the critical issues in these structures is fabrication of a transparent back contact which facilitates not only ohmic contact for holes in the valance but also an effective reflector for electrons in the conduction band. In order to meet these requirements of the transparent back contact, a p-type amorphous Si (p-a-Si)/intrinsic amorphous Si (i-a-Si) bi-layer was deposited onto the ITO back contact. Absorber films were formed by a metal precursor reaction in H2Se and H2S, and their thicknesses were adjusted to about 0.25 µm to enhance current collection from back-side illumination. The resulting devices with a bi-facial structure of SLG/ITO/p-Si/i-Si/Cu(In, Ga)(Se,S)2/CdS/i-ZnO/ITO/Ni-Al exhibited a comparable open-circuit voltage to a Cu(In, Ga)(Se,S)2 cell on a Mo substrate in tests with illumination of both sides. Back-wall cells with a structure of SLG/ITO/p-Si/i-Si/Cu(In, Ga)(Se,S)2/CdS/i-ZnO/Ag-reflector were also fabricated and improved current collection by greater light trapping was achieved compared to the bi-facial cell with back-side illumination.

Validation and Extension of Local Temperature Evaluation of Conductive Filaments in RRAM Devices

Local temperature plays a key role in resistive switching random access memory devices. We have previously presented a method for measuring the local filament temperature on a nanometric scale using an MIS bipolar transistor structure. Here, a more detailed analysis of the method is presented. A new calibration technique improves the accuracy of the extracted temperature. Alternative device structures allow validation of the method by the extraction of temperature that equals the ambient temperature when no self-heating occurs as well as extension of the obtained temperature range. The accuracy, prospects, and limitations of the method are discussed.

Deposited ALD SiO2 High-k/Metal Gate Interface for High Voltage Analog and I/O Devices on Next Generation Alternative Channels and FINFET Device Structures

A highly reliable SiO2 deposited by atomic layer deposition (ALD) as a gate dielectric interface layer with high-k/metal gate (HKMG) in high voltage I/O field effect transistor (FETs) for advanced technologies has been demonstrated. Improved process control, better gate oxide conformality, superior dielectric reliability (over CVD SiO2), and equivalent uniformity and reliability compared to thermal oxide proves its usefulness for FinFET/ETSOI I/O devices. In addition, use of ALD SiO2 with novel interface layer results in reduced interfacial regrowth on SiGe channel, which when coupled with post deposition nitridation and annealing optimization for optimal performance, is an attractive oxide optimization option for alternate channel architectures.

Deposited ALD SiO2 High-k/Metal Gate Interface for High Voltage Analog and I/O Devices on Next Generation Alternative Channels and FINFET Device Structures

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Building Neuromorphic Circuits with Memristive Devices

The rapid, exponential growth of modern electronics has brought about profound changes to our daily lives. However, maintaining the growth trend now faces significant challenges at both the fundamental and practical levels [1]. Possible solutions include More Moore?developing new, alternative device structures and materials while maintaining the same basic computer architecture, and More Than Moore?enabling alternative computing architectures and hybrid integration to achieve increased system functionality without trying to push the devices beyond limits. In particular, an increasing number of computing tasks today are related to handling large amounts of data, e.g. image processing as an example. Conventional von Neumann digital computers, with separate memory and processer units, become less and less efficient when large amount of data have to be moved around and processed quickly. Alternative approaches such as bio-inspired neuromorphic circuits, with distributed computing and localized storage in networks, become attractive options [2]?[6].

Spray-deposited CuInSe2 nanocrystal photovoltaics

Photovoltaic devices (PVs) were fabricated by spray-coating an ink of copper indium diselenide (CIS) nanocrystals as the light-absorbing layer. Without high-temperature post-deposition annealing, PVs were made on glass and plastic substrates with power conversion efficiencies of up to 1.9% and 1.1%, respectively, under AM1.5 illumination. The mild processing conditions also enabled fabrication of alternative device structures that are not compatible with conventional high-temperature PV processing, including substrate and superstrate designs, and devices with transparent back contacts of conducting indium tin oxide (ITO) and plastic substrates. Device performance is observed to be limited by poor charge extraction from the nanocrystal films, with the highest efficiencies being obtained from PVs with relatively thin absorber layers. To improve light absorption without sacrificing internal quantum efficiency, stacked PVs were fabricated, which exhibited improved short-circuit current and power conversion efficiency compared to stand-alone single junction devices.

Controlling the carrier recombination zone for improved color stability in a two-dopant fluorophore/phosphor white organic light-emitting diode

A white organic light-emitting diode (WOLED) is produced upon systematic introduction of deep-blue fluorescence from 4,4′-bis(9-ethyl-3-carbazovinylene)-1,1′-biphenyl to broad-band yellow phosphorescence from bis[3,5-bis(2-pyridyl)-1,2,4-triazolato]platinum(II) in the common host 4,4′-bis(carbazol-9-yl)biphenyl. The carrier recombination zone is first identified upon investigating alternative device structures, then optimized by varying the thickness of the electron-transport layer. The WOLED exhibits striking stability of color and efficiency, as manifest by parameters at high brightness of 1000 cd/m2 sustaining 94%–122% their values at 50 cd/m2.

Effect of elastic processes and ballistic recovery in silicon nanowire transistors

Scaling of silicon devices is fast approaching the limit where a single gate may fail to retain effective control over the channel region. Of the alternative device structures under focus, silicon nanowire transistors (SNWT) show great promise in terms of scalability, performance, and ease of fabrication. Here we present the results of self-consistent, fully 3D quantum mechanical simulations of SNWTs to show the role of surface roughness (SR) and ionized dopant scattering on the transport of carriers. We find that the addition of SR, in conjunction with impurity scattering, causes additional quantum interference which increases the variation of the operational parameters of the SNWT. However, we also find that quantum interference and elastic processes can be overcome to obtain nearly ballistic behavior in devices with preferential dopant configurations.

Nanomaterials in nanoelectronics: Who’s who and what’s next

This paper provides an overview of the role of nanomaterials in emerging nanoelectronic devices. As semiconductor devices are scaled to smaller and smaller sizes within the nanoregime, a variety of technological and economic problems arise, the rules of classical physics give way to quantum mechanics, and the term molecular-scale ultimately becomes as or more accurate than nanoscale. At this point, the size scaling that has successfully taken device features from the microscale to the nanoscale can no longer be continued, and alternative processing technologies, materials, and device structures are required. In this regime, nanostructured materials, including quantum dots, semiconductor nanowires, and carbon nanotubes, become essential to continued miniaturization and performance enhancement.

Scaling CMOS devices through alternative structures

The conventional wisdom holds that CMOS devices cannot be scaled much further from where they are today because of several device physics limitations such as the large tunneling current in very thin gate dielectrics. It is shown that alternative device structures can allow CMOS transistors to scale by another 20 times. That is as large a factor of scaling as what the semiconductor industry accomplished in the past 25 years. There will be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.

CMOS scaling into the nanometer regime

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

CMOS scaling into the 21st century: 0.1 µm and beyond

This paper describes the design, fabrication, and characterization of 0.1-µm-channel CMOS devices with dual n+/p+ polysilicon gates on 35-A gate oxide. A 2× performance gain over 2.5-V, 0.25-µm CMOS technology is achieved at a power supply voltage of 1.5 V. In addition, a 20× reduction in active power/circuit is obtained at a supply voltage of < 1 V with the same delay as the 0.25-micron CMOS. These results demonstrate the feasibility of high-performance and low-power room-temperature 0.1-µm CMOS technology. Beyond 0.1 µm, a number of fundamental device and technology issues must be examined: oxide and silicon tunneling, random dopant distribution, threshold voltage nonscaling, and interconnect delays. Several alternative device structures (in particular, low-temperature CMOS and double-gate MOSFET) for exploring the outermost limit of silicon scaling are discussed.

Optoelectronic integration: A technology for future telecommunication systems

An overview is given of research on optoelectronic integrated circuits (OEICs) since the late 1970s. The current state of OEICs for telecommunication applications is examined. The quaternary alloy material InGaAsP, which can be grown lattice matched to InP, is the material of choice for fabricating emitters and detectors. Because these materials do not lend themselves to a simple MESFET technology, there has been extensive research into alternative electronic device structures such as MISFETs, JFETs, and heterojunction bipolar transistors for integration with optical devices. Problems that remain to be solved are identified.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Numerical modeling of vertical Hall-effect devices

A two-dimensional numerical simulation of the unconventional Hall device recently proposed by Popovic is presented. Some improved and simplified alternative device structures are proposed and simulated as well.