All-digital Phase-locked Loop Research Articles

A 3.2-to-4.6 GHz fast-settling all-digital PLL with feed forward frequency presetting

A 3.2-to-4.6 GHz fast-settling all-digital PLL with feed forward frequency presetting

An all‐digital phase‐locked‐loop with a robustness enhanced dual‐mode DCO

ABSTRACTAn all‐digital‐phase‐locked‐loop (ADPLL) with a dual‐mode Class‐A/Class‐C Digital‐controlled‐oscillator (DCO) is presented in this letter. During the start‐up phase, the DCO operates in the Class‐A mode with increasing tail current. A low‐power amplitude‐to‐pulse‐converter (APC) is proposed to detect the oscillating amplitude of the DCO. After the start‐up, the DCO switches to the Class‐C mode with reduced tail current, resulting in better phase noise and lower power consumption. The ADPLL with the proposed DCO is implemented in a 65‐nm CMOS technology. The Class‐C mode DCO exhibits a phase noise of −123.3 dBc/Hz at 1‐MHz offset with a 2.7‐GHz carrier frequency. Measured results show about a 2.9‐dB phase noise improvement at 1‐MHz offset among the tuning range of 2.5–2.9 GHz, compared to the Class‐A DCO under the same power consumption. The figure‐of‐merit (FOM) and FOM including the tuning range (FOMT) of the DCO is 188.7 and 192.1, respectively. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:312–315, 2017

A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring

This brief presents a built-in self-calibration (BISC) technique for minimization of the total jitter in bang-bang all-digital phase-locked loops (ADPLLs). It is based on the addition of a monitoring phase-frequency detector (PFD) with tunable delay cells for the reference clock and the divider clock and a counter for this PFD output signal. This allows for on-chip binary comparison of the jitter distribution widths at the ADPLL PFD input, when ADPLL filter parameters are altered. Since only a relative comparison is performed, no accurate delay calibration is required. The statistical properties of this comparison of two random distributions are analyzed theoretically, and guidelines for circuit dimensioning are derived. The proposed method is used for BISC by adaption of the ADPLL filter coefficients. This allows for jitter minimization under process, voltage and temperature variations as well as gain and period jitter of the digitally controlled oscillator. The proposed calibration technique is verified by system simulations and measurements of a silicon prototype implementation in 28-nm CMOS technology.

A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS

This paper presents a low-power hybrid-loop receiver (RX) with high-interference tolerance for Bluetooth low energy (BLE). The hybrid-loop structure based on an all-digital phase-locked loop enables the RX to both enhance the interference tolerance and digitize the frequency-modulated signal without an ADC. A novel single channel receiving method, which enables the conversion of the constellation from frequency shift keying to differential binary phase shift keying signal, is adopted to eliminate the Q-channel signal processing to reduce the power consumption. The prototype RX fabricated in a 65 nm CMOS technology consumes only 5.5 mW and fulfills the BLE requirements of the adjacent channel rejection and out-of-band blocker tolerance without exception. The sensitivity level is −90 dBm.

Quantization Noise Analysis of Time-to-Digital-Converter-Based All-Digital Phase-Locked Loop and Frequency Discriminators

All-digital phase-locked loops (ADPLLs) based on the time-to-digital converter (TDC) and the frequency discriminator (FD) are modeled and analyzed in terms of quantization effects. Using linear models with quantization noise sources, theoretical analysis and simulation are carried out to obtain the output phase noise of each building block of the TDC-based ADPLL. It is newly derived that the TDC noise component caused by the delta-sigma modulator (DSM) and the finite resolution of the digitally controlled oscillator is not white. Namely, the in-band phase noise caused by the DSM-induced TDC is not white, which is due to the integrate-and-dump and subsampling operations of the TDC. This can give some insight into the design of low-noise ADPLLs. Some structures of delta-sigma FDs, which can serve as an alternative to the TDC, are also newly analyzed in terms of quantization noise, using the derived linear noise model.

A fast locked and low phase noise all-digital phase locked loop based on model predictive control

An all-digital phase locked loop (ADPLL) taking new approach for design of the loop filter is presented. A feedback loop in the time domain by modeling the DCO and TDC as an appropriate model in the state-space form is proposed. Then, a model predictive control (MPC) method for designing loop filter in order to generate an optimal control signal is employed. The proposed loop filter can overcome latency issue that inevitably exists in most of digital systems. Furthermore, the proposed MPC loop filter achieves rapid transient response time and enables us to model other noise sources resulted from oscillator pulling and flicker noise which are common problems in many modern transceivers and the effects of which can be dramatically removed without degrading the overall phase noise performance. Simulation results confirm the capability of the proposed design and show it is significantly more robustness against these problems compared to conventional digital PLL.

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode.

ANALYSIS OF FREQUENCY SYNTHESISERS FOR MULTISTANDART WIRELESS TRANSCEIVER / DAŽNIO SINTEZATORIŲ DAUGIASTANDARČIAMS BEVIELIO RYŠIO SIŲSTUVAMS IR IMTUVAMS ANALIZĖ

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

A 2.2 GHz -242 dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture

This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of $- 112\; \text{dBc/Hz}$ and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of $-242 \; \text{dB} $ was achieved with a power consumption of only 4.2 mW.

A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase–Frequency-Error Compensation

The previous fast-locked all-digital phase-locked loop (ADPLL) usually suffers from large timing jitter due to the steep frequency transfer curve of its digitally controlled oscillator (DCO). This paper presents an ADPLL that possesses a coarse frequency selection function. All DCO frequency transfer curves of the ADPLL have gentle slopes. The ADPLL selects one transfer curve before acquisition. To fulfill the fast-acquisition requirement, the proposed ADPLL employs the phase–frequency-error compensation technique. In the acquisition mode, the phase-error compensator resolves the problem of phase-error accumulation. Meanwhile, the frequency-error compensator predicts a proper control code by calculating the cycle time difference between the reference clock and the derived signal fed back from the DCO. Therefore, the proposed ADPLL can compensate for the phase and the frequency errors simultaneously. The experimental results show that the proposed ADPLL possesses a fine-tuning acquisition within 5 reference clock cycles. After acquisition, the code updates in a fractional manner in the tracking mode to enhance the tracking jitter performance. The ADPLL output frequency ranges from 860 MHz to 1 GHz. The measured rms jitter is 1.31 ps at 1-GHz frequency.

An All-Digital PLL Proposal using Gain Control Technique

Time-to-digital converter (TDC) has been the main technique used in all-digital phase-locked loops (ADPLL). However, this approach has several design issues, and the solutions to resolve them always increase the complexity of the system. In this paper, an alternative method for handle the frequency error detection using a type II ADPLL architecture is presented. The proposed technique does not perform direct conversion from time to digital, but employs the discrete-time processing of compared signals from phase error detection. This architecture has the advantage of scalability and integration of all-digital techniques and has less complexity than conventional ADPLLs. The derivation of equations for the proposed architecture and its noise analysis is provided. The results are validated through system level simulations using macro-models of the devices. The result of the transient simulation shows the theoretical predictions about the trajectory of output frequency.

A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques

This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm(2)). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (V-DD = 0.52 V), the ADPLL only dissipates 269.9 mu W at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of 57.3 dBc with the period jitter of 0.217% UI.

Near‐threshold all‐digital PLL with dynamic voltage scaling power management

A near-threshold all-digital phase-locked loop (ADPLL) with a power management unit (PMU) is presented to make the proposed ADPLL work reliably across variations and power consumption as well is reduced. When operated under near-threshold condition from 0.52 to 0.58 V VDD, the gated digitally controlled oscillator frequency range is from 90.8 to 245.7 MHz. When the ADPLL is operated at 0.52 V VDD, a lock-in time of 9.5 μs at 100 MHz output clock frequency is measured with an rms period jitter of 0.17% UI. With the PMU, the ADPLL power reduction at 130 MHz output frequency is 39% and the buck converter power consumption is nearly 30 μW. Consequently, the proposed ADPLL with PMU is suitable to event-driven or low-voltage applications.

A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling

In energy-efficient processing platforms, such as wearable sensors and implantable medical devices, dynamic voltage and frequency scaling allows optimizing the energy efficiency under various modes of operation. The clock generator used in these platforms should be capable of achieving a faster settling time and has a wider operating voltage range. In this brief, a fast lock-in all-digital phase-locked loop (ADPLL) with two operation modes (0.52/1 V) is presented. The proposed ADPLL can quickly compute the desired digitally controlled oscillator control code with high accuracy. Therefore, the proposed ADPLL can achieve a fast setting time with frequency errors $\mu \text{W}$ at (0.52 V, 120 MHz).

A low jitter all - digital phase - locked loop in 180 nm CMOS technology

An all-digital phase locked loop (ADPLL) was implemented in 180 nm CMOS technology. The proposed ADPLL uses a digitally controlled oscillator to achieve 3 ps resolution. The pure digital phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog counterpart. The proposed ADPLL can be easily applied to different process as a soft IP block, making it very suitable for system-on-chip applications.

Prof. R. Bogdan Staszewski Gives Short Course on All-Digital Phase-Locked Loops at SSCS Chengdu Chapter [Chapters

Prof. R. Bogdan Staszewski Gives Short Course on All-Digital Phase-Locked Loops at SSCS Chengdu Chapter [Chapters

A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology

A system-on-a-chip (SoC) requires several phase-locked loops (PLLs) for providing different clock frequencies to different modules. Usually, analog PLLs cannot be stopped due to their long setting time. Hence, these PLLs dominate the system's standby power consumption. In this paper, a fast lock-in all-digital PLL (ADPLL) that can achieve lock-in within 4.5 clock cycles is proposed to ensure that it can be switched off in the low power mode. The output frequency of the proposed ADPLL ranges from 125 MHz to 1.47 GHz, and the power consumption is 0.98 mW (at 0.9 V, 1.47 GHz).

Modeling and Analysis of a Novel All-Digital Phase-Locked Loop Based on FPGA

提出了一种新型的全数字锁相环，其采用自采样比例积分控制，使得锁相输出无静差，输出抖动小，并能根据数字鉴相器输入信号间相位误差的大小，调节数字环路滤波器的计数模数，在保证锁相环稳定性的同时，提高了锁相环锁定速度。本文基于该全数字锁相环各模块工作特性的分析，建立了全数字锁相环的数学模型，利用所得到的锁相环系统传递函数进行了性能参数分析，并给出了锁相环参数设计指导原则。论文最后通过实验测试验证了理论参数分析的正确性。 This paper proposed a novel all-digital phase-locked loop (ADPLL). By using the self-sampling PI control method, it can obtain a phase-locked output signal without steady-state error and with less jitter. The designed ADPLL is able to adjust the mode number of the digital loop filter according to the phase error between the two input signals of the digital phase detector. In this way, the ADPLL can optimize the lock-in speed when the system stability is also guaranteed. The paper establishes the mathematical model of the ADPLL based on the analysis of the operating characteristic of each module. Using the obtained system transfer function, the paper analyzes the performance parameters of the ADPLL, and provides the guiding principle of the parameters design. The validity of theoretical analysis is verified by experimental test in the final of this paper.

Single-Event Characterization of Bang-bang All-digital Phase-locked Loops (ADPLLs)

The single-event vulnerability of a bang-bang ADPLL is investigated through fault injection experiments and circuit simulations. Single-event upsets in the digital loop filter result in the worst-case error response of the ADPLL, often requiring phase reacquisition. Single-event tolerant design guidelines for the digital loop filter are proposed and validated through FPGA-based fault injection experiments.

A Subharmonically Injection-Locked All-Digital PLL Without Main Divider

A subharmonically injection-locked all-digital phaselocked loop (ADPLL) without a main divider is presented. It achieves not only low power but also low phase noise over the process, voltage, and temperature (PVT) variations. This ADPLL uses only a simple bang-bang phase detector without a time-todigital converter when both frequency and phase locking. Moreover, the injection pulse can be self-adjusted to optimal timing over the PVT variations without additional calibration loop. This ADPLL is fabricated in a 40-nm CMOS process; it consumes 3.04 mW under a standard supply of 1.1 V excluding output buffers. The measured phase noise of the proposed ADPLL is -121.4 dBc/Hz at 1-MHz offset. The integrated RMS jitter is 109.6 fs for the offset frequency from 1 kHz to 100 MHz. The calculated figure-of-merit is equal to -254.39 dB.