Duty Cycle Adjustment Research Articles

Design of power saving protocol with duty cycle adjustment for public safety-LTE

Design of power saving protocol with duty cycle adjustment for public safety-LTE

A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs

A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs

A novel linear square/triangular wave generator with tunable duty cycle

A novel circuit of square/triangular wave generator consists of single multiple output dual-X current conveyor transconductance amplifier (MO-DXCCTA), one grounded resistor and one grounded capacitor is proposed. One square wave in current mode and one triangular wave in voltage mode are simultaneously available from the proposed generator. The proposed circuit is fully electronically controllable facilitating the feature of duty cycle adjustment. The duty cycle is electronically tunable via bias current. Moreover, a wide sweep of oscillation frequency is possible via grounded capacitor with very good linearity. The tuning of oscillation frequency does not affect the amplitudes of output waveforms. Furthermore, the oscillation frequency can also be controlled electronically and independently via bias current for a fixed duty cycle of 50%. A prototype of MO-DXCCTA using commercial ICs (AD844 and LM13700) is used to carry out the experimental results. Measured results show very good variation of frequency (up to 245.5 kHz) against capacitor with nonlinearity less than 2%.

Control of entanglement dynamics in a system of three coupled quantum oscillators

Dynamical control of entanglement and its connection with the classical concept of instability is an intriguing matter which deserves accurate investigation for its important role in information processing, cryptography and quantum computing. Here we consider a tripartite quantum system made of three coupled quantum parametric oscillators in equilibrium with a common heat bath. The introduced parametrization consists of a pulse train with adjustable amplitude and duty cycle representing a more general case for the perturbation. From the experimental observation of the instability in the classical system we are able to predict the parameter values for which the entangled states exist. A different amount of entanglement and different onset times emerge when comparing two and three quantum oscillators. The system and the parametrization considered here open new perspectives for manipulating quantum features at high temperatures.

PV Voltage Control in Spite of Disturbances on MCB Boost Output Voltage in Parallel Association

We present a specific control law designed to Magnetically Coupled Boost (MCB) converters used as photovoltaic (PV) optimizers in parallel association. In the case of inappropriate control algorithms, conflicts appear between boosts, preventing energy injection on output power bus for some of them. In this work, we highlight that an important disturbance on output bus induces consequent perturbation of PV module operating point, when controlling in open loop. In a second time we show how to implement a formula designed to compute duty cycle in pulse width modulation control (PWM), in spite of not perfect MCB model and no linear PV module behavior. Indeed, challenge is to adjust duty cycle according to actual power bus voltage when PV module voltage has to be constant, especially when Maximum Power Point is reached. A closed loop with elementary correction law is implemented in sampled control to ensure PV voltage as reference, preventing any variation of PV operating point. In a third time, experiments with different settings in sampled controller are analyzed, and comparisons between responses allow to conclude on robustness of such control, in the case of only one MCB converter disturbed by output voltage. Further studies of converter behavior in parallel association are also mentioned at the end of this paper, with objectives, for example, to characterize impact of possible shading on photovoltaic module and even to allow coupling of storage units to power bus.

Implementation of a programmable electromechanical chopper with adjustable frequency and duty cycle for specific heat measurements

A hard disk mechanism was used as an electromechanical light chopper controlled by software developed in LabVIEW with an accuracy of ±0.01Hz in frequency to realize specific heat measurements. This chopper can be used in applications in experimental techniques in which low-frequency light excitation is required. The software provides an user interface to set the excitation frequency and its duty cycle. The evaluation of the efficiency was measured by installing the device in a fully automated high-resolution AC calorimetry system. The device provides a light cutter signal with a frequency varying from 1mHz to 40Hz. Employing the desired wave function, the excitation mode provided by this design can be used under theoretical models proposed for the specific heat technique, obtaining an increased efficiency in the measurements of the specific heat response for the studied materials. This paper reports the performance characteristics of the technology of an asymmetric CA-chopper, which can optimize efficiency in capturing the measurement of the response of specific heat of any given study material in a high-resolution ac calorimetry system. The chopper consists entirely of the positioning mechanism of a hard disk.

Big program code dissemination scheme for emergency software-define wireless sensor networks

Program codes as one of big data should be disseminated to all sensor nodes in a wireless software-define smart network (WSDSN) quickly. Due to the limited energy of sensor nodes, sensor nodes adopt asynchronous duty-cycle model to save energy. But neighbor nodes with sleep status can’t receive program codes, resulting in longer transmission delay for spreading program codes. In this paper, an adjustable duty cycle based fast disseminate (ADCFD) scheme is proposed for minimum-transmission broadcast (MTB) in a smart wireless software-define network. In an ADCFD scheme, the duty cycle of nodes are adjusted to receive program codes timely. Thus, the transmission times and emergency transmission delay are reduced. The theoretical analysis and experimental results show that compare to previous broadcast scheme, the number of transmission in an ADCFD scheme is reduced by 44.776%–118.519%, the delay from disseminating program codes is reduced by 17.895%- 107.527%, while retaining network lifetime.

Activity-Aware Sensor Cycling for Human Activity Monitoring in Smart Homes

Smart homes are one of the Internet of Things domains intended to support and aid the residents through various smart services. These services require accurate context inferences using daily activity patterns and environmental properties. To satisfy such a need with battery-powered sensors, various duty cycling schemes were introduced. In this letter, we propose an activity-aware sensor cycling approach that makes the best tradeoff for duty cycle adjustments by exploiting the predictable behavior of residents, thereby significantly improving the activity detection accuracy at a marginal increase of the energy consumption. Evaluation results demonstrate that it achieves up to 99% accuracy of activity detection and extends the network lifetime by supporting balanced energy consumption among sensors.

High sensitivity field asymmetric ion mobility spectrometer.

A high sensitivity field asymmetric ion mobility spectrometer (FAIMS) was designed, fabricated, and tested. The main components of the system are a 10.6 eV UV photoionization source, an ion filter driven by a high voltage/high frequency n-MOS inverter circuit, and a low noise ion detector. The ion filter electronics are capable to generate square waveforms with peak-to-peak voltages up to 1000 V at frequencies up to 1 MHz with adjustable duty cycles. The ion detector current amplifier has a gain up to 1012 V/A with an effective equivalent input noise level down to about 1 fA/Hz1/2 during operation with the ion filter at the maximum voltage and frequency. The FAIMS system was characterized by detecting different standard chemical compounds. Additionally, we investigated the use of a synchronous modulation/demodulation technique to improve the signal-to-noise ratio in FAIMS measurements. In particular, we implemented the modulation of the compensation voltage with the synchronous demodulation of the ion current. The analysis of the measurements at low concentration levels led to an extrapolated limit of detection for acetone of 10 ppt with an averaging time of 1 s.

Prescription of rhythmic patterns for legged locomotion

As the engine behind many life phenomena, motor information generated by the central nervous system plays a critical role in the activities of all animals. In this work, a novel, macroscopic and model-independent approach is presented for creating different patterns of coupled neural oscillations observed in biological central pattern generators (CPG) during the control of legged locomotion. Based on a simple distributed state machine, which consists of two nodes sharing pre-defined number of resources, the concept of oscillatory building blocks (OBBs) is summarised for the production of elaborated rhythmic patterns. Various types of OBBs can be designed to construct a motion joint of one degree of freedom with adjustable oscillatory frequencies and duty cycles. An OBB network can thus be potentially built to generate a full range of locomotion patterns of a legged animal with controlled transitions between different rhythmic patterns. It is shown that gait pattern transition can be achieved by simply changing a single parameter of an OBB module. Essentially, this simple mechanism allows for the consolidation of a methodology for the construction of artificial CPG architectures behaving as an asymmetric Hopfield neural network. Moreover, the proposed CPG model introduced here is amenable to analogue and/or digital circuit integration.

A Simplified Space Vector Modulation Scheme for Multilevel Converters

This paper proposes a simplified space vector modulation (SVM) scheme for multilevel converters. Compared with earlier SVM methods, the proposed scheme simplifies the detection of the nearest three vectors and the generation of switching sequences, and therefore is computationally more efficient. Particularly, for the first time, the proposed scheme achieves the same easy implementation as phase-voltage modulation techniques. Another superior characteristic of the proposed scheme over earlier methods is its potential for multiphase multilevel applications. The proposed scheme also offers the following significant advantages: 1) independence of the level number of the converter; 2) more degrees of freedom, i.e., redundant switching sequences and adjustable duty cycles, to optimize the switching patterns; and 3) no need for lookup tables or coordinate transformations. These advantages make the proposed scheme well suited to large level-number applications, such as modular multilevel converters and high voltage direct current systems. Simulation and experimental results verify this new concept.

플랜트 시설에서 지연시간 감소를 위한 동적 듀티사이클 조절 기법

For environmental monitoring and risk identification of industrial plants, several monitoring systems using Wireless Sensor Networks (WSNs) have been developed. In this paper, we propose a dynamic duty cycle adjustment mechanism for reduced latency in industrial plants. The proposed method adjusts the duty cycle among predefined risk groups depending on the urgency of sensed data values. To demonstrate its efficacy, we analyze the expected transmission latency model and then discuss the characteristics in detail. We show that the proposed dynamic duty cycle mechanism is a more effective than a periodic mechanism by analyzing the expected latency of them in industrial plants where there are various types of sensory data with different levels of reliability.

Femtosecond-laser-inscribed sampled fiber Bragg grating with ultrahigh thermal stability.

We have successfully fabricated a series of sampled fiber Bragg gratings with easily adjustable sampling periods and duty cycles using an 800 nm femtosecond laser point-by-point inscription. The thermal stability of the fabricated fiber gratings was investigated using isochronal annealing tests, which indicated that the fiber gratings are capable of maintaining high reflectivity at temperatures of up to 1000°C for 8 h. This demonstrates the potential of the developed sampled fiber Bragg gratings for use in multi-wavelength fiber lasers and a variety of high temperature applications.

An energy-efficient mobile target detection scheme with adjustable duty cycles in wireless sensor networks

In this paper, an energy-efficient mobile target detection scheme with adjustable duty cycles (TDADCs) is proposed. TDADC has three advantages. First, it takes full advantage of the residual energy and improves the effective energy utilisation by increasing the sensing duty cycle of non-hotspot nodes. Secondly, the new scheme can significantly improve the overall probability of target detection. Thirdly, the notification transmission latency can be reduced by increasing the communication duty cycles of non-hotspot area. The problem of target detection can be addressed as an optimal problem trade-off between the target detection quality and network lifetime. A novel measurement framework called Weighted Quality of Target Detection (WQTD) is also proposed to measure the quality of target detection. Both theoretical and simulation results show that the proposed scheme significantly improved the probability of target detection, decreased the notification transmission latency and detection delay without reducing the network lifetime.

An energy-efficient mobile target detection scheme with adjustable duty cycles in wireless sensor networks

In this paper, an energy-efficient mobile target detection scheme with adjustable duty cycles (TDADCs) is proposed. TDADC has three advantages. First, it takes full advantage of the residual energy and improves the effective energy utilisation by increasing the sensing duty cycle of non-hotspot nodes. Secondly, the new scheme can significantly improve the overall probability of target detection. Thirdly, the notification transmission latency can be reduced by increasing the communication duty cycles of non-hotspot area. The problem of target detection can be addressed as an optimal problem trade-off between the target detection quality and network lifetime. A novel measurement framework called Weighted Quality of Target Detection (WQTD) is also proposed to measure the quality of target detection. Both theoretical and simulation results show that the proposed scheme significantly improved the probability of target detection, decreased the notification transmission latency and detection delay without reducing the network lifetime.

Traffic-based energy efficient MAC protocol for wireless sensor networks

The sensor node's battery power shows a key part in the sensor network's lifespan. The various existing medium access control protocols do not consider various factors like the sensor's traffic load and battery life, which lead to more energy consumption. In order to solve this problem, a new protocol called the traffic-based energy efficient MAC TBEMAC protocol is proposed for wireless sensor networks. It includes two stages, namely, the duty cycle adjustment phase and the wakeup schedule phase. In the duty cycle adjustment phase the sensor node's duty cycle is adjusted based on the sensor's traffic load, buffer status and battery life. In the wakeup schedule phase, TBEMAC groups organises the nodes in each corona based on their battery life and traffic load. The active time AT period, is also identified from the wakeup time slots of each node, which greatly reduces idle listening and energy consumption. The simulation results prove that the extension and dynamic adjustment of the duty cycle of the sensor nodes greatly improves data effectiveness, and reduces end-to-end delay.

Clock and Synchronization Networks for a 3 GHz 64 Bit ARMv8 8-Core SoC

This paper describes the clock distribution and synchronization network for a 64 bit ARMv8 8-core microprocessor. Embedded in a SoC for cloud computing platforms, the processor is fabricated in a 40 nm CMOS technology and operates at 3.0 GHz. The system PLL has a measured rms jitter <;1 ps and features dynamic frequency hopping for DVFS applications. In conjunction with a Star/H/Mesh topology, the clock distribution uses both CML and CMOS circuits to minimize period jitter and nominally achieves <;0.8 ps/mV | rms and <;9 ps of period jitter and skew, respectively. By using local Duty Cycle Adjustment circuits in each core to properly offset the clock duty cycle and ease timing critical paths, the processor performance improves by more than 5%. A simple probing circuit for high speed clock measurements can be used to monitor the high frequency excursions of the internal supply to counteract any timing violation that could occur. Finally an enhanced latch, which improves MTBF by up to 5 orders of magnitude and thus is suited for high speed synchronization operations, is proposed.

A Review: Implementation of Maximum Power Point Tracking Algorithm for PV System on FPGA

Photovoltaic power generation has two major problems: the conversion efficiency of existing PV modules is less and amount of power generated by PV system changes with weather conditions. Also, the PV cell I-V characteristics are non-linear due to complex relationship of voltage & current and varies with change in temperature or insolation. There is only one point on P-V or I-V curve called Maximum Power Point at which PV system operates at maximum efficiency and produces maximum output power. Failure to track MPP causes significant power loss. So, Maximum Power Point Tracking (MPPT) is required to operate PV system at MPP. The P&O algorithm and INC algorithm are commonly used methods to track MPP by adjusting duty cycle of DC-DC converter. The existing methods use microcontroller or DSP controller to implement MPPT algorithm. FPGA provides number of advantages over sequential machine microcontroller, as FPGA does concurrent operation i.e. instructions executed continuously and simultaneously. However DSP does signal processing related calculation only. Using FPGA number of components required is less and FPGA is faster than DSP. Thus, the size of components required for power converter decreases. The MPPT algorithm is implemented on FPGA which continuously track the maximum point under rapid environmental changes.

Cooperative Scheduling for Adaptive Duty Cycling in Asynchronous Sensor Networks

To support the sustainable operation of wireless sensor networks using limited energy, duty cycling is a promising solution. However, it is a challenge to guarantee each node communicating with its neighbors under duty cycle when the network is asynchronous. The challenge becomes bigger when nodes’ duty cycles are required to be adjusted separately according to their demands to save energy and achieve high channel utilization. Existing low power listening- and contention-based protocols are not energy-efficient and cannot ensure high channel utility. Additionally, synchronizationbased media access control (MAC) protocols suffer from extra energy consumption and low synchronization precision. This paper proposes a localized and on-demand (LOD) duty cycling scheme based on a specifically designed semi-quorum system. LOD can adjust duty cycle of each node adaptively according to its demand so as to avoid channel contention, consequently achieving high channel utilization. This allows the fairness for channel access within asynchronous sensor networks. Extensive experiments are conducted on a real test-bed of 100 TelosB nodes to evaluate the performance of LOD. As compared with B-MAC, LOD substantially reduces contention for channel access and the energy consumption, thus improving the network throughput significantly.

A Fast and Generalized Space Vector Modulation Scheme for Multilevel Inverters

This paper presents a fast and generalized space vector pulse width modulation (SVPWM) scheme for any multilevel inverter. The SVPWM scheme generates all the available switching states and switching sequences based on two simple and general mappings, and calculates the duty cycles simply as if for a two-level SVPWM, thus independent of the level number of the inverter. Because the switching states, duty cycles, and switching sequences are all obtained by simple calculation in the proposed SVPWM scheme, no lookup table is needed and the scheme is computationally fast. The generalized method of generating the switching states (first mapping), calculating the duty cycles, and determining the switching sequence (second mapping) is described in this paper. The scheme is suitable for any reference vector with any modulation index, and can be conveniently extended to meet specific requirements, such as symmetric switching sequences. Compared with prior methods, the SVPWM scheme proposed in this paper provides two more degrees of freedom, i.e., the adjustable switching sequences and duty cycles, thus offering significant flexibility for optimizing the performance of multilevel inverters. The influence of redundant switching sequences in the output phase voltage of inverters is demonstrated for a nine-level inverter. This paper also thoroughly compares the proposed SVPWM scheme with prior methods. Both simulation and experimental results are given.