Duty Cycle Adjustment Research Articles

A Modified Y-Source DC–DC Converter With High Voltage-Gains and Low Switch Stresses

This letter proposes a modified Y-source dc–dc converter, which features higher voltage-gains but lower voltage stresses on the components. Moreover, the proposed converter draws a continuous current from the dc input with much control flexibility (i.e., a wide range of adjustable duty cycles). Additionally, the coupled inductors have a low turns ratio, and the core saturation issue is avoided due to the dc-current-blocking capacitor. A detailed analysis of the proposed converter is provided, and the performance is benchmarked with selected coupled-inductors-based converters on various aspects. Experimental tests confirm the theoretical analysis.

An Adjust Duty Cycle Method for Optimized Congestion Avoidance and Reducing Delay for WSNs

With the expansion of the application range and network scale of wireless sensor networks in recent years, WSNs often generate data surges and delay queues during the transmission process, causing network paralysis, even resulting in local or global congestion. In this paper, a dynamically Adjusted Duty Cycle for Optimized Congestion based on a real-time Queue Length (ADCOC) scheme is proposed. In order to improve the resource utilization rate of network nodes, we carried out optimization analysis based on the theory and applied it to the adjustment of the node’s duty cycle strategy. Using this strategy to ensure that the network lifetime remains the same, can minimize system delay and maximize energy efficiency. Firstly, the problems of the existing RED algorithm are analyzed. We introduce the improved SIG-RED algorithm into the ADCOC mechanism. As the data traffic changes, the RED protocol cannot automatically adjust the duty cycle. A scheduler is added to the buffer area manager, referring to a weighted index of network congestion, which can quickly determine the status of network congestion. The value of the weighting coefficient W is adjusted by the Bayesian method. The scheduler preferably transmits severely urgent data, alleviating the memory load. Then we combined improved data fusion technology and information gain methods to adjust the duty cycle dynamically. By simulating the algorithm, it shows that it has faster convergence speed and smaller queue jitter. Finally, we combine the adjusted congestion weight and the duty cycle growth value to adjust the data processing rate capability in the real-time network by dynamically adjusting it to adapt to bursts of data streams. Thus, the frequency of congestion is reduced to ensure that the system has higher processing efficiency and good adaptability.

METHOD FOR PRECISE TIMING AND DUTY CYCLE ADJUSTMENT IN I/O PADS

METHOD FOR PRECISE TIMING AND DUTY CYCLE ADJUSTMENT IN I/O PADS

A Reinforcement Learning-Based Duty Cycle Adjustment Technique in Wireless Multimedia Sensor Networks

Multimedia delivery support has recently been added to Wireless Sensor Networks (WSN) and has led to increased interest in Wireless Multimedia Sensor Networks (WMSN). WMSNs are expected to be crucial to the success of applications related to the Internet of Things (IoT), such as smart health, smart surveillance, smart homes, etc. Alongside their improved multimedia capabilities, WMSNs inherit WSN limitations such as energy and processing constraints. Additionally, WMSNs have significant Quality of Service (QoS) requirements, since multimedia delivery requires increased network performance in terms of bandwidth, latency, etc. Balancing energy efficiency and QoS is a fundamental challenge for WMSN users and operators alike. This paper proposes Reinforcement Learning based Duty Cycle (rlDC), an innovative learning-based scheme to adjust the duty cycle and contention window of WMSN nodes in order to meet energy efficiency and QoS targets. By employing rlDC, WMSN sensor nodes intelligently adapt their operation according to network delivery performance and application requirements. The proposed rlDC scheme was evaluated under different use cases in a simulation environment, and testing results show it outperforms other state-of-the-art duty-cycle-based protocols for WMSNs.

Current‐source mode switched‐capacitor power converters with improved current gain capability

A new family of current-source (CS) mode switched-capacitor (SC) power converters has been proposed in this study, which imposes an alternative solution for power converters especially for CS systems. The conversion ratio of this type converter is analysed and verified here to have one increased degree of freedom using the switching mode and the capacitor-tapping mode, which is a good solution to deal with the limitation of duty cycle adjustment. This research improves the CS mode system that is relatively unexplored in previous works and the proposed work fills the research gap by the sides of the well-established voltage-source (VS) system. An interesting power conversion ratio formulation is obtained, which can produce the wide range of conversion ratio of VS mode switched-inductor power converters and CS mode SC power converters in buck, boost and buck-boost versions. In addition, this proposed CS mode SC power converters have high efficiency of power conversion through simulation and prototype experiments verification. These CS mode converters can flexibly supply power directly to the load powered by the CS and successfully replace the VS mode converters operated under the current environment system.

Hierarchical MAC protocol with adaptive duty-cycle adjustment algorithm for wireless sensor network

In wireless sensor networks (WSNs), the existing routing algorithms causes increased energy utilisation and minimises the lifetime of the network. In order to conquer this problem, in this paper, an adaptive duty-cycle adjustment algorithm based on the traffic and channel condition is put forwarded. Initially, the node with higher weight value is chosen as cluster head, the value is calculated from residual energy and delay between the successive transmissions. After the cluster formation, the relay nodes are selected by their remaining battery energy and the channel state in the network for the data transmission. Based on the relay nodes found, the network traffic is controlled by the traffic adaptive duty-cycle. In this approach, the heads of each cluster collects traffic information from member nodes and computes appropriate duty cycle according to current traffic, and then the resulting duty cycle information conveyed to normal nodes. The node then executes the data transmission based on the duty cycle. Our results revealed that the proposed approach minimises the energy utilisation and enhances the network lifetime too.

Hierarchical MAC protocol with adaptive duty-cycle adjustment algorithm for wireless sensor network

Hierarchical MAC protocol with adaptive duty-cycle adjustment algorithm for wireless sensor network

A Power-Efficient Configurable FSK–OOK Transmitter with Scalable Data Rate for Wireless Medical Applications

This paper presents a 922 MHz power-efficient configurable frequency-shift keying–on–off keying (FSK–OOK) phase-locked loop (PLL)-based transmitter. The proposed transmitter works as a multimode structure with configurable data rate and output power. In OOK modulation, by duty cycle adjustment of input data and producing return-to-zero data (RZ-data) by a simple circuit, the data rate can be scaled with power consumption. This implies that any desired level of output power can be transmitted with different power consumption according to the power budget. The transmitter benefits from a new phase frequency detector, an improved charge pump and a low-power voltage-controlled oscillator. The proposed structure represents data rate of 0.24–2.4 Mb/s in OOK mode and 1.8 Mb/s in FSK mode, and it can deliver output power level from − 19.71 to 0.53 dBm. The efficiency of the transmitter at RZ–OOK modulation with data rate of 2.4 Mb/s and output power of 0.53 dBm is 57.25%. Also, the efficiency of transmitter in FSK modulation is 22.1%. The post-layout simulation results in 0.18 µm RF CMOS process are obtained and verify the effectiveness of the proposed circuit.

A Simplified 3-D NLM-Based SVPWM Technique With Voltage-Balancing Capability for 3LNPC Cascaded Multilevel Converter

The nearest level modulation (NLM)-based space vector pulsewidth modulation (SVPWM) algorithms have attracted a great deal of interest since they can provide various degrees of freedom, i.e., optimized switching sequences and adjustable duty cycles. This article proposes a simplified three-dimensional (3-D) NLM-based SVPWM algorithm in a 3-D coordinate system. Compared with the generalized two-dimensional (2-D) NLM-based SVPWM schemes, the proposed method not only provides identical degrees of freedom to optimize switching patterns and obtain adjustable duty cycles, but also presents better digital implementation and lower hardware occupancy to achieve the real-time PWM generation. In addition, based on the NLM-based principle, a method of addressing the issue of unbalanced voltages in a three-phase 3-level neutral point clamped cascaded multilevel converter (3LNPC-CMC) is introduced. The presented method possesses the optimized voltage-balancing capacity and equalizes the unbalanced inner cell and mutual cell voltages in the 3LNPC-CMC with minimum number switching transition. Finally, the whole proposed process is verified by simulation and experimental results.

A Test Circuit for GaN HEMTs Dynamic $R_{\text{ON}}$ Characterization in Power Electronics Applications

Wide bandgap devices such as gallium nitride (GaN) high electron mobility transistors (HEMTs) are a promising technology in the field of power electronics. Due to the physical properties of the GaN and the device design, they can outperform their silicon counterparts for the design of highly efficient power switching converters. However, its design should face certain effects that can diminish its performance. One such effect is the degradation mechanism known as dynamic ON-resistance (dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ ), being its mitigation one of the main objectives in the design of the device. In this paper, a circuit is proposed for assessing if this effect is present in GaN transistors in power electronics applications. The circuit allows testing the GaN HEMTs with different stress voltages and times maintaining the desired current level, and allows for repeating the test in successive switching pulses, with adjustable switching frequency and duty cycle, always with the same current, mimicking a real power electronics application.

Optimized Parameters Design and Adaptive Duty-Cycle Adjustment for Class E DC–DC Converter With on‐off Control

The Class E dc–dc converter, with a simple topology and zero-voltage-switching (ZVS) for the power switch, can operate at a switching frequency of up to megahertz. In this paper, an optimized ZVS operation condition for minimizing the switch voltage stress, switch rms current, and switch voltage harmonic components is derived for the on ‐ off controlled Class E dc–dc converter by optimizing the time instant at which the switch voltage resonates back to zero. Based on this result, a step-by-step parameter design approach is proposed for a Class E dc–dc converter with a large input inductor, which avoids time-consuming simulations or complex numerical calculations. Then, a capacitance compensation approach is further proposed to extend the design results to a Class E dc–dc converter with a resonant input inductor. Furthermore, an adaptive duty-cycle adjustment scheme is proposed for reducing the reverse conduction loss of the power switch, thereby improving the conversion efficiency over the entire input voltage range. Finally, a prototype of a 20-MHz 10-W Class E dc–dc converter is built and tested in the laboratory, and experimental results are presented to verify the effectiveness of the proposed optimized parameter design approach and the adaptive duty-cycle adjustment scheme.

A low-power reference-less clock/data recovery for visible light communication devices requiring low data throughput

In this study a reference-less clock and data recovery (CDR) is designed and developed for the low speed visible light communication system based Internet of Things (IoT) tags. Design system incorporates an off-chip photodiode and an integrated-on chip front-end receiver with the reference-less CDR. For an IoT tags low power consumption, low supply voltage, and small area are the major design constraint. Considering these constraints, the circuit of the front-end receiver incorporate the near-threshold cascode current mirror based transimpedance amplifier, low pass filter and a comparator. On the other-hand, low power all-digital phase locked loop-based reference-less CDR is design herein with a modified loop filter, auto tune digital control oscillator and auto duty cycle adjustment circuit. The circuit is implemented in an integrated chip with area of 0.728 mm2 via TSMC 180 nm process. Experimental measurement results of the tapeout chip shows that the phase noises are − 39.54 dBc/Hz @ 1 kHz, − 80.35 dBc/Hz @ 10 kHz and − 92.26 dBc/Hz @ 100 kHz. The measured jitter in the recovered clock is 3.312 ns (0.0033 UI). At 1 Mbps, the measured total power consumption is 5.58 μW. The achieve results shows that the implemented circuit in this study highly support the commercial low data rate based optical wireless sensing nodes for IoT tags.

Fully Electronically Tunable and Easily Cascadable Square/Triangular Wave Generator with Duty Cycle Adjustment

A novel multiple-output dual-X current conveyor transconductance amplifier with buffer-based square/triangular wave generator is introduced in the paper. The proposed generator provides square wave in current mode and triangular wave in voltage mode. Outputs as square and triangular waves are available from terminals with appropriate impedance levels thereby making the proposed generator circuit easily cascadable in both current and voltage modes. The oscillation frequency and amplitude of output square wave are electronically and independently controllable. One more interesting feature of the proposed generator circuit is the adjustable duty cycle. The proposed circuit of square/triangular wave generator is verified through the HSPICE simulation results carried using 0.18[Formula: see text][Formula: see text]m CMOS technology. The simulation results show linear variation of duty cycle against external DC current over a range of 6.5–96%. The variation of square wave’s amplitude via bias current is found to be linear from 10[Formula: see text][Formula: see text]A to 80[Formula: see text][Formula: see text]A. Moreover, the proposed generator can operate very well up to 23.8[Formula: see text]MHz with nonlinearity less than 5%. The proposed generator circuit is also experimentally verified.

An energy efficient data transmission approach for low-duty-cycle wireless sensor networks

In low-duty-cycle wireless sensor networks, the lifetime of energy-limited nodes is improved, but the network’s transmission delay is also increased. However, many systems with real-time capabilities require data to be sent to the data center within a specified time. In this paper, we first analyze the relationship between the duty cycle of the node and the network lifetime and transmission delay, and then propose a novel scheme named transmission delay minimization based on adjustable duty cycle (DMADC). In the DMADC scheme, a higher duty cycle is employed in the non-hotspot region to achieve a lower latency, and a lower duty cycle is used in the hot spot area to achieve higher network life. This method can make full use of the residual energy of the nodes at the edge of the network to dynamically adjust its duty cycle, reduce the waiting delay in the data transmission process, and select a path close to the global optimum for each node in the network, so that our scheme is able to achieve a minimum average end-to-end delay. The theoretical analysis and experimental results demonstrate that the performance of DMADC is better than that proposed in previous studies. Compared with previous research schemes, the DMADC scheme can reduce the end-to-end data transmission delay by 10.25%–26.37% while maintaining the network lifetime, and increase the energy utilization rate by more than 25%. The DMADC scheme improves network lifetime by about 30% while maintaining end-to-end latency.

A Microcontroller-Based Modular Pulsed H.V. Power Supply: Design, Implementation, and Tests on DBD-Based Plasmas

This paper is devoted to the design, implementation, and test of a low cost, modular, and reliable pulsed high-voltage (HV) converter (dc chopper). The distinct characteristics of the present prototype refer to: adjustable voltage amplitude up to 7 kV, amplitude drop less than 4‰ for $2 \times 10$ A output peak current at 5 kHz, adjustable pulse frequency up to 5 kHz, adjustable duty cycle between 1% and 10%, rising/falling time around 100 ns, and jitter about 10 ns. In principle, 1-kV modules based on a fast MOSFET each are combined in series to form a completely modular push–pull switch configuration. Contrary to sophisticated optical fiber-based insulation techniques, the driving low-voltage stage of the power supply is magnetically coupled to the HV stage. The low-voltage stage defines and schedules the HV pulses by means of a microcontroller. The 7 kV is equally distributed along MOSFETs due to balancing networks of passive components. Zener diodes in parallel with MOSFETs provide sufficient protection against overvoltages. The power supply has been successfully tested on dielectric-barrier discharge-based plasmas which have nowadays continuous technological interest.

A Systematic Approach to Determining the Duty Cycle for Regenerative Comparator Used in WSN

A low power regenerative comparator is very useful in Successive Approximation Register (SAR) type Analog to Digital Converter (ADC) for a Wireless Sensor Node (WSN). A regenerative type comparator generates output pulses by comparing input with a reference input. This paper deals with control of a power with an adjustable duty cycle. The regenerative comparator with an adjustable duty cycle and a positive feedback of a latch will help in improving accuracy, speed and also in achieving the less power consumption. The optimum value of a duty cycle is determined with taking into consideration of metastability timing constraints. The proposed low power regenerative comparator circuit is designed and simulated by using TSMC 180 nm CMOS technology. The comparator consumes power as low as 298.54 nW with a regenerative time 264 ps at 1 V power supply.

Novel CMOS MO‐CFDITA based fully electronically controlled square/triangular wave generator with adjustable duty cycle

This study presents a novel square/triangular wave generator based on multiple-output current follower differential input transconductance amplifier (MO-CFDITA) with reduced complexity in terms of transistors. The proposed generator comprises of single MO-CFDITA and one grounded capacitor only which makes the proposed generator circuit suitable to integrated circuit implementation. The proposed generator provides output square wave in current mode and output triangular wave in voltage mode. The amplitude of current-mode square wave is electronically and independently tunable via bias current. The DC level of the triangular wave is also electronically adjustable. The proposed generator has dual-slope operation and its duty cycle is adjustable with the help of DC current source over a range of 5–95%. The proposed generator consumes a power of 1.45 mW only and it is usable up to 50 MHz which is quite good operating frequency range. To examine the performance of the proposed generator, the cadence VIRTUOSO simulation results have been depicted. Additionally, the simulation results and performance parameters of complementary metal–oxide–semiconductor (CMOS) MO-CFDITA are included. The practicality of the proposed generator is verified through the experimental results.

Analysis of Measurement and Application of Digital to Analog Converters for Software Defined Radio Hybrid System

Software defined radio (SDR) and cognitive radio have become the development trend for military or civilian radio stations. This paper analyzes the digital to analog (DAC) system based on software defined radio applications. The measurement procedure and calibration technique for hybrid signal system are described in detail. In order to maximize the utilization of the image spectrum and achieve better performance for communication, the sub-Nyquist rate DAC system with different construction modes is introduced. The two-phase holding reconstruction mode utilizes higher order image spectrum by adjusting duty cycle of the two phases. This technique based on SRD has the merit of lower power consumption and higher efficiency for communication system.

Design of power saving protocol with duty cycle adjustment for public safety-LTE

In this paper, a power saving protocol for public safety-long-term evolution (PS-LTE) with duty cycle adjustment is proposed according to the emergency of PS-LTE-based mobile stations. Because the PS-LTE transceiver consumes power whenever it is active, it is the most efficient to leave the receiver off, and wake it up asynchronously only when needed. As an alternative to protocol-based duty-cycle control, an asynchronous wake-up scheme is designed for battery saving of PS-LTE devices. This type of PS-LTE phones with power saving protocol has an adaptive cycle control during 'EMERGENCY-CALL'. This dedicated wake-up 'EMERGENCY PS-LTE Phone' can continuously monitor the channel, listening for a wake-up signal from other nodes and activating the main receiver upon the detection of asynchronous wake-up protocol. As a result, PS-LTE-based mobile station reduces power consumption by maximising the node sleeping-time without compromising network latency, and the wake-up PS-LTE phone with power saving protocol (without PS-LTE's function activities: group communication systems enabler, proximity-based service, mission critical push-to-talk, isolated E-UTRAN operation for public safety, relay, etc.) also enables the improvement of overall network performance.

一种改进变步长自适应扰动观察法的研究

光伏板是对太阳能的有效利用手段，而最大功率跟踪则是优化此手段的重要途径。就目前来看，扰动观测法是MPPT应用较为广泛的一种方法，但传统扰动观察法存在跟踪速度与能量波动损失问题，针对于此，设计一种变步长自适应MPPT跟踪方法。该方法利用前后时刻功率差值作为占空比调节因子，并且设定阈值，留取一定的功率波动裕量，有效解决了上述存在问题，在此之外还能够进行自适应控制。通过Simulink建模仿真分析，与传统方法进行比较，得出该方法在跟踪的稳定性、快速性、与能量损耗减少方面具有明显优势。 Photovoltaic panels are effective means of solar energy utilization, and maximum power tracking is an important way to optimize this method. At present, the disturbance observing method is a widely used method of MPPT. However, the traditional disturbance observing method has the problems of tracking speed and energy fluctuation loss. In view of this, a variable step adaptive MPPT tracking method is designed. The method uses the power difference between the front and the rear moment as the duty cycle adjustment factor, and sets the threshold value, leaving a certain power fluctuation margin, which effectively solves the above existing problems; besides, it can also carry out adaptive control. By Simulink modeling and simulation analysis, compared with the traditional methods, the conclusion is drawn that the method has obvious advantages in terms of tracking stability, rapidity and energy loss reduction.