Adjacent Errors Research Articles

Construction and analysis of check matrices correcting single and double adjacent errors codes

Construction and analysis of check matrices correcting single and double adjacent errors codes

Integer codes correcting single errors and double adjacent errors

AbstractThe user datagram protocol is the most widely used protocol for streaming multimedia data over the Internet. Like other protocols at the network and transport layers, it uses the Internet Checksum (IC) to detect channel errors. The consequence of this is that each corrupted packet is dropped, which can degrade the quality of service perceived by a user. In this paper, the authors present a solution to this problem based on integer codes capable of correcting single and double adjacent errors. The presented codes are a generalization of the IC, which makes them easy to implement in software.

Modified Proficient Adjacent Error Correcting Codes

As the technology scales down, the soft errors manifested from faults appear in memories due to radiation effects. This paper suggests two decoding mechanisms using hamming bits, extended hamming bits and vertical parity bits applied on matrix codes. Among the proposed two ways of decoding, the method-2 induces less number of errors if the number of adjacent bits exceeds N/2 for N-bit data. Both decoding mechanisms are capable of correcting a maximum of N/2 adjacent errors in N data bits. The codes are modelled in Verilog HDL and are verified in Xilinx Vivado 2021.2 Tool for Zynq 7000 series FPGA. The results prove that the minimum bit overhead of 31.25% and maximum code rate of 76.19% can be achieved if 64-bits of data are processed at a time using proposed AEDAC codes but with a trade-off in terms of area.

New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application

Multiple cell upset (MCU) caused by cosmic radiation is a serious issue related to the reliability of static random access memories (SRAMs) in space application. Due to radiation, single cell or multiple cells of a memory are corrupted. The chances of errors in more than one memory cells are also increasing due to continuous down scaling of technology. Single error, double or triple adjacent errors are most common in this case. Several error correction codes are already introduced for protecting the memories. But many existing error correcting codes have either higher delay and/or power consumption and/or decoder error rate. In this paper, we have introduced 16-bit, 32-bit and 64-bit information length, uniquely decodable single error correction-double adjacent error correction (SEC-DAEC) and single error correction-double adjacent error correction-triple adjacent error correction (SEC-DAEC-TAEC) codes with lower power consumption and delay. In our design, same H-matrix is used for implementing both SEC-DAEC and SEC-DAEC-TAEC codes. Both FPGA and ASIC based synthesis results show that proposed SEC-DAEC and SEC-DAEC-TAEC codes with dimensions (24, 16), (41, 32) and (75, 64) are better compared to existing same dimension codes with respect to area, power and delay. Since, the proposed SEC-DAEC and SEC-DAEC-TAEC codes have low encoder and decoder delay which corresponds to low writing and reading time, consume significantly low power and have zero decoder error rate, so proposed codec can be used for memories in space application.

Error Detection and Correction for Golay Code & Extended Golay Code using Cyclic Redundancy Check

In this paper certain optimization techniques are proposed to reduce the encoder and decoder computation time of cache memory that is affected by soft error and by implementing ECC such as cyclic and block codes. Error that is adjacent by a width of three and two bits are the prime concern of this thesis. Optimised Golay code (23, 12) and new block code size (32, 19) which is also optimised are presented. Nevertheless, cyclic code is efficient compared with block code however, the prime concern of the thesis is to address the triple and double adjacent errors which also includes single bit error, in this regard built-in capability of Golay code is optimised and used for comparison. The extended Golay code is implemented in term of number of slice, number of LUT and maximum combinational path delay compared with existing Golay code.

Low overhead optimal parity codes

The error detecting and correcting codes are used in critical applications like in intensive care units, defense applications, and require highly reliable data. This brief focuses on codes to detect and correct adjacent errors within a single clock cycle by using modulo-2 addition of data bits for parity generation, syndrome calculation, error location identification and correction by improving code rate and minimizing bit overhead. The optimal parity codes devised can correct odd number of adjacent errors upto (N/2)-1 data bits when compared with the existing codes with less delay. Four optimal codes are proposed using existing decimal matrix codes properties. The proposed codes prove better in terms of area, delay, power, bit overhead, code rate, code efficiency, and with good reliability. The components are developed in veriloghardware description language and verified for zynq 7000 series field programmable gate array in xilinx integrated synthesis environment 14.5 Tool. Among the codes devised, optimal code-4 proves to be a better code with 65.3% code rate and 53.12% bit overhead. Also when compared with other codes, it uses 33.3% less area and 1.89% less power delay product for encoder and 32.2% less area and 0.36% power delay product for decoder respectively.

Splitting Sequences for Coding and Hybrid Incremental ARQ with Fragment Retransmission

This paper proposes a code defined on a finite ring ℤpM, where pM = 2m−1 is a Mersenne prime, and m is a binary size of ring elements. The code is based on a splitting sequence (splitting set) S, defined for the given multiplier set E=±20, ±21,…, ±2m−1. The elements of E correspond to the weights of binary error patterns that can be corrected, with the bidirectional single-bit error being the representative that occurs the most. The splitting set splits the code-word into sub-words, which inspired the name splitting code. Each sub-word, provided with auxiliary control symbols that are a byproduct of the coding procedure, corrects a single symbol error. The code can be defined, with some constraints, for general Mersenne numbers as well, while the multiplier set can be adjusted for adjacent binary errors correction. The application proposed for this code is a hybrid three-stage incremental ARQ procedure that transmits the code-word in the first stage, auxiliary control symbols in the second stage, and retransmits the sub-words detected as incorrect in the third stage. At each stage, error correction can be turned on or off, keeping both the retransmission rate and residual error rate at a low level.

Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.

Integer Codes Correcting Single Errors and Detecting Burst Errors Within a Byte

Correcting single and detecting adjacent errors has become important in memory systems using high density DRAM chips. The reason is that, in these systems, the strike of a single energetic particle can upset one or more adjacent bits. In this article, we present a simple solution for this problem based on integer codes capable of correcting single errors and detecting ${l}$ -bit burst errors confined to a ${b}$ -bit byte ( $1 {\, ). Unlike the classical approach, the proposed one does not rely on the use of dedicated encoding/decoding hardware. Instead, it uses the processor as both encoder and decoder. The effectiveness of such solution is demonstrated on a theoretical model of an eight-core processor. The obtained results show that it has the potential to be used in future DDR5 systems.

Protecting Memories against Soft Errors: The Case for Customizable Error Correction Codes

As technology scales, radiation induced soft errors create more complex error patterns in memories with a single particle corrupting several bits. This poses a challenge to the Error Correction Codes (ECCs) traditionally used to protect memories that can correct only single bit errors. During the last decade, a number of codes have been developed to correct the emerging error patterns, focusing initially on double adjacent errors and later on three bit burst errors. However, as the memory cells get smaller and smaller, the error patterns created by radiation will continue to change and thus new codes will be needed. In addition, the memory layout and the technology used may also make some patterns more likely than others. For example, in some memories, there maybe elements that separate blocks of bits in a word, making errors that affect two blocks less likely. Finally, for a given memory, depending on the data stored, some error patterns may be more critical than others. For example, if numbers are stored in the memory, in most cases, errors on the more significant bits have a larger impact. Therefore, for a given memory and application, to achieve optimal protection, we would like to have a code that corrects a given set of patterns. This is not possible today as there is a limited number of code choices available in terms of correctable error patterns and word lengths. However, most of the codes used to protect memories are linear block codes that have a regular structure and which design can be automated. In this paper, we propose the automation of error correction code design for memory protection. To that end, we introduce a software tool that given a word length and the error patterns that need to be corrected, produces a linear block code described by its parity check matrix and also the bit placement. The benefits of this automated design approach are illustrated with several case studies. Finally, the tool is made available so that designers can easily produce custom error correction codes for their specific needs.

Reducing false positives due to double adjacent errors in instruction TLBs

Translation lookaside buffers (TLBs) are cache structures used to make the translation process between virtual pages and physical pages faster. Instruction TLBs store the virtual page number of the last accessed instruction memory pages and the corresponding physical page numbers. Single and double adjacent errors, which are common in harsh environments, may affect TLBs. This paper presents a technique to provide instruction TLB resilience to these single and double adjacent errors without additional storage requirements, by taking advantage of the spatial locality principle that is present in program execution.

Low Delay 3-Bit Burst Error Correction Codes

The increasing importance of Multiple Cell Upsets (MCUs) in modern memories has spurred research on error correction codes that can correct adjacent bit errors. For example, Double Adjacent Error Correction (DAEC), 3-bit burst and 4-bit burst codes have been proposed in the last years. However, as the error correction capabilities are increased so is the complexity of the encoder and decoder circuits. This directly impacts the encoding and decoding delay and thus limits the use of the codes in high speed memories. To reduce the complexity, some techniques have been proposed recently. Those include more advanced optimization programs to find codes with a lower number of ones in the parity check matrix or the interleaving of data and parity check bits to simplify the decoding. In this paper, those techniques are combined to design more efficient 3-bit burst error correction codes. The encoders and decoders for the proposed codes have been implemented and compared with the state of the art 3-bit burst error correction codes. The results show that the new codes reduce the encoder and decoder delay significantly. Therefore, the proposed codes provide memory designers with a more efficient option to implement protection against 3-bit burst errors for high speed memories.

Efficient Implementations of 4-Bit Burst Error Correction for Memories

In recent years, there has been a growing interest in error correction codes (ECCs) that can correct localized errors in memories. This is due to the larger fraction of radiation induced error events that affect several nearby memory cells as technology scales. Initially, codes that can correct single and double adjacent errors were proposed. More recently, 3-bit burst ECCs have also been presented. The next step is to provide efficient 4-bit burst error correction for memories. The issue is that as the error correction capability increases so does the overheads required to implement the codes in terms of parity check bits and encoding and decoding complexity. In this brief, efficient solutions to protect memories against 4-bit bursts are presented. The first one is the use of two interleaved single and double adjacent ECC while in the second, efficient 4-bit burst ECCs are presented. The first solution reduces the decoding complexity and delay at the cost of having more parity check bits while the second tries to reduce the decoding complexity when using the minimum number of parity check bits. Both solutions have been evaluated and compared to an interleaved single error correction code and with existing burst ECCs to better understand the overheads needed to achieve the protection against 4-bit burst errors.

Hamming Error Detection using triple Adjacentcode Algorithm

Error detection and correction codes provide reliable delivery of information signals. In general, these types of errors are generated in RAM chips [Error detection]. These errors can be detected and corrected by employing the error-detecting and error-correcting codes in RAMs. The most generalized scheme for detecting the error in error detecting technique is parity bit. In Single Error Correction-Triple Adjacent Error Detection (SEC-TAED) method, the parity bit can be extended to detect a single error as well as triple adjacent errors. Hence, SEC-TAED based hamming code is referred to as “Extended Hamming SEC-TAED codes.” Hence, 82% of detection efficiency can be achieved in modified bit-reordered based SEC-TAED process.

Soft Error Tolerance in Memory Applications

This paper proposes a new method to detect and correct multi bit errors in memory applications using a combination of a clustering approach, Bit-Per-Byte error detection technique, and Majority Logic Decodable (MLD) codes. The likelihood of soft errors accelerates with system complexity, reduction in operational voltages, exponential growth in transistor per chip, increases in clock frequencies, breakdown of memory reliability and device shrinking. Memories are the sensitive part of a computer system. Soft errors in memories may cause an instruction to malfunction. Several techniques are already in practice to mitigate the soft errors. Majority logic decodable codes are proved as effective for memory applications because of their ability to correct a massive number of errors. Since memories are used to hold large number of bits that’s the restraint of Majority logic decodable codes method, so we emphasize on the size of data word in this method. The proposed method aims to detect and correct up to seven bit errors with lesser computational time. It works in an efficient manner in case of adjacent errors which is not possible in Majority logic decodable codes (MLD). It is delineated by Experimental reviews that the proposed approach outperforms existing dominant approach with respect to number of erroneous bit detection and correction, and computational time overhead.

Spelling With a Small Mobile Brain-Computer Interface in a Moving Wheelchair.

Research into brain-computer interfaces (BCIs), which spell words using brain signals, has revealed that a desktop version of such a speller, the edges paradigm, offers several advantages: This edges paradigm outperforms the benchmark row-column paradigm in terms of accuracy, bitrate, and user experience. It has remained unknown whether these advantages prevailed with a new version of the edges paradigm designed for a mobile device. This paper investigated and evaluated in a rolling wheelchair a mobile BCI, which implemented the edges paradigm on small displays with which visual crowding tends to occur. How the mobile edge paradigm outperforms the mobile row-column paradigm has implications for understanding how principles of visual neurocognition affect BCI speller use in a mobile context. This investigation revealed that all the advantages of the edges paradigm over the row-column paradigm prevailed in this setting. However, the reduction in adjacent errors for the edges paradigm was unprecedentedly limited to horizontal adjacent errors. The interpretation offered is that dimensional constraints of visual interface design on a smartphone thus affected the neurocognitive processes of crowding.

Joint Crosstalk Aware Burst Error Fault Tolerance Mechanism for Reliable on-Chip Communication

In a Nano-scale technology, reliability is one of the main issues for on-chip communication systems. To make communication system more reliable, Joint Crosstalk Aware Multiple Error Correction with interleaving scheme is proposed for crosstalk errors. This technique is very useful while dealing with burst error. The number of burst errors which can be tolerated by this technique can be adjusted by changing the interleaving distance between adjacent bits of the same module. The burst of 9 adjacent errors can be corrected if 4 modules of encoder and decoder are used. The design is implemented on FPGA to calculate area overhead and delay. The proposed JMEC/JMEC-Inter encoder and decoder are both fast, with maximum operating frequencies of 163.308 MHz and 307.977 MHz respectively by trading off by I/O's pins (48.53 and 19.85 percent more I/O's than Hamming and JTEC respectively). The area consumed by the proposed technique is less than the 3 percent of the FPGA resources, making the technique good candidate on chip fault tolerance mechanism.

Optimizing the Implementation of SEC–DAEC Codes in FPGAs

Single error correction and double-adjacent error correction (SEC–DAEC) codes are a type of error correction codes (ECCs) capable of correcting single and double-adjacent errors. They are useful in applications where multiple adjacent errors may occur, such as space or avionics. ECC encoders and decoders have a regular structure that makes it easier to accommodate them into field-programmable gate arrays (FPGAs). This brief proposes methods to optimize the decoder of SEC–DAEC codes when implemented in an FPGA, reducing the resource utilization when compared with the conventional implementations.

High performance adjacent error detection for nanometer devices

Static random-access memory (SRAM) based memories are widely used in electronic systems and if their contents change due to external reasons, the electronic system can functionally fail. One of the external reasons is the radiation induced soft errors as the SRAM memories are susceptible to radiation effects. Majority of the recently proposed methods use error correction codes (ECC) to mitigate soft errors. Error correction/detection capabilities of such methods are at most 3 bits in a codeword which will be insufficient while number of memory bits affected by a radiation particle is increased, as CMOS process technology shrinks towards around 5 nm. Since memory bits affected by a radiation particle are physically close, adjacent error detection/correction becomes a hot research topic. In this Letter, Euclidean geometry-low density parity check code, more capable ECC than Hamming code used in recent works, is explored in context of adjacent error detection performance. The results show that proposed method successfully detects up to 14-bit adjacent errors in a 15-bit codeword. As such, this method is suitable where high detection performance is needed. The proposed method is also simplified for efficient hardware implementation while detection performance is not sacrificed. Both methods are compared in terms of resource usage.

Extended Hamming SEC-DAED-TAED based Fault Detection Technique for AES Encryption and Decryption

Objectives: This paper proposes efficient extended hamming codes to find & rectify a single error (SEC) as well as find large number of double & triple adjacent errors (DAED) or (TAED). Methods: (n, k) hamming codes are utilized to implement the proposed system. The codeword of (n, k) hamming codes have ‘n’ bit. From these ‘n’ bit error combinations are found by using MATLAB design tool. From detected error combinations, the order of code bits is changed according to bit replacement algorithm. Calculated codewords are shuffled in order to obtain high probability of detection in double & triple errors. Findings: Calculated Hamming SEC-DAED-TAED codes (Bit-reordered codeword) gives 45% of probability of detection improvements in double adjacent error detection and 33% of probability of detection improvements in triple adjacent error detections when compared to normal order based hamming SEC-DAED-TAED codes. 128-bit Advanced Encryption Standard (AES) encryption standard is considered as one of the applications of developed hamming code. Applications: Mobile banking, Internet banking, space and terrestrial communications are considered as the important applications of proposed hamming codes based AES encryption.