Adjacent Channel Power Ratio Research Articles

A Comprehensive Study of Adaptive LNA Nonlinearity Compensation Methods in Direct RF Sampling Receivers

This paper studies the effects of nonlinear distortion of Low Noise Amplifier (LNA) for the multichannel direct-RF sampling receiver (DRF). The main focus of our work is to study and compare the effectiveness of the different adaptive compensation algorithms, including the inverse-based and subtract-based Least Mean Square (LMS) algorithm with a fixed and variable step size. The models for the compensation circuits have been analytically derived. As the major improvements, the effectiveness of the compensation circuits under the ADC quantization noise effect is evaluated. The bit-error-rates (BER) in dynamic signal-to-noise ratio (SNR) scenarios are calculated. We have proposed the use of variable step-size LMS (VLMS) to shorten the convergence time and to improve the compensation effect in general.
 To evaluate and compare different compensation methods, a complex Matlab model of the Ultra high frequency (UHF) DRF with 4-QPSK channels was implemented. The simulation results show that all compensation methods significantly improve the receiver performance, with the convergence time of the VLMS algorithm does not exceed 5.104 samples, the adjacent channel power ratios (ACPR) are reduced more than 30 dBc, and the BERs decrease by 2­–3 orders of magnitude, compared with the non-compensated results. The simulation results also indicate that the subtraction method in general has better performance than the inversion method.

1.2–2.8-GHz 32.4-dBm Digital Power Amplifier With Balance-Compensated Matching Network

In this letter, a wideband watt-level digital power amplifier (DPA) with a balance-compensated matching network is proposed for polar transmitters. The balance response of the differential to the single-ended transformer is enhanced by a series-loaded compensation capacitor, which leads to the improvement of the DPA efficiency. To verify the mechanisms, a prototype DPA is fabricated in conventional 40-nm CMOS technology. The proposed DPA operates over 1.2–2.8 GHz and exhibits a peak output power of 32.4 dBm at 2 GHz and a peak drain efficiency of 53.8% at 1.8 GHz. It supports 50-MHz 64-quadratic-amplitude modulation (QAM) with average output power ( $P_{\text {avg}}$ ) of 25.37 dBm, error vector magnitude (EVM) of −26.97 dB, adjacent channel power ratio (ACPR) of −29.61 dBc, and 10-MHz 1024-QAM with $P_{\text {avg}}$ of 22.14 dBm, EVM of −35.75 dB, and ACPR of −35.37 dBc, respectively.

Hybrid Harmonic Cancellation Digital Predistortion With a Feedback Loop Compensation

High frequency (HF) transmitter whose operating frequency range is about four octaves is always faced with the problems of harmonics because of the nonlinearity of the power amplifier (PA). The conventional analog harmonic cancellation scheme uses lossy and bulky filter banks. The digital harmonic cancellation scheme requires a high sampling rate. In this brief, a hybrid harmonic cancellation digital predistortion (HHC-DPD) technique is proposed to suppress the interfering harmonics by adding a low-pass filter between the PA and the directional coupler. The proposed HHC-DPD scheme can greatly lower the sampling rate, in turn, decrease the digital power consumption and resource occupation. Further, a feedback loop compensation (FLC) method is proposed to cancel the time misalignment between the harmonics and the fundamental caused by the chromatic dispersion in the feedback loop. With the FLC method, the non-convergence issue in iterations can be avoided. Experimental results on an HF PA with carrier frequency located at 8 MHz validate that the proposed HHC-DPD scheme with the FLC outperforms current harmonic cancellation approaches. The sampling rate was reduced from 300 MHz to 100 MHz. Both the harmonics and the adjacent channel power ratio (ACPR) were cancelled for being below −50 dBc after the HHC-DPD.

Broadband RF‐predistortion supporting carrier aggregation

In this work, a frequency reconfigurable broadband radio frequency-predistorter (BB RF-PD) is proposed that can effectively suppress the power amplifier (PA) intermodulation distortion from 200 MHz to 2.5 GHz. It is an attractive lineariser solution for radio repeaters in long distance communication, where baseband information is not readily available. For broadband signals, existing linearisation techniques become intractable due to high cost and power consumption. The proposed BB RF-PD eliminates the use of data converters, field programmable gate arrays, but still provides the well-intentioned linearisation using the passive components. Three application scenarios have been investigated – (i) and (ii) intra-band: 160 MHz long-term evolution (LTE) signal and 100 MHz two-tone signal, and (iii) inter-/multi-band: two-component carrier LTE signal with frequency spacing of 1 GHz. For verification, the proposed BB RF-PD is implemented with a 10 W HMC8500 PA and tested using 160 MHz signal at 1.8 GHz. It delivers an adjacent channel power ratio (ACPR) of −45.65 dBc with an improvement of 16.87 dB, while for inter-band scenario a new technique has been devised for multiband communication, which is known as BB multipath RF-predistorter. It delivers an ACPR of −50 and −47 dBc for lower and upper CC, respectively.

Configurable Independently Tunable Linearizer for Doherty Power Amplifiers

In this letter, a linearization solution for Doherty power amplifiers (DPAs) based on independently tunable linearizer (ITL) is proposed. The ITL for DPA (DITL) is obtained by vector synthesis of two parallel ITLs; the back-off and gain characteristic is configurable to match the DPAs. To verify the method, a prototype is designed at 3.5 GHz. A DPA with 8.5 dB back-off and 20-MHz wideband signal stimulated is measured, the results show that the adjacent channel power ratio (ACPR) is improved from −32.3 to −44.9 dBc, and the power consumption and cost with performance improvement is comparable to conventional linearizers. The DITL can achieve good performance without codesign with DPA, which is suitable in 5G communication system.

A Circuit-Inspired Digital Predistortion of Supply Network Effects for Capacitive RF-DACs

This article presents a novel digital predistortion (DPD) approach to compensate for nonlinear dynamic distortions caused by the supply network of capacitive radio frequency digital-to-analog converters (RF-DACs). The developed DPD concept recreates the voltage distortion on the RF-DAC’s supply network and modulates the input signal such that the effects on the output signal of the RF-DAC are canceled. In contrast to conventional DPD approaches such as pruned Volterra series or memory polynomials, the complexity of the proposed concept is reduced to a feasible level, allowing for implementation in integrated circuits. Furthermore, the derived DPD model allows to use linear estimation algorithms for coefficient training. The presented DPD is demonstrated by measurements of two different capacitive RF-DAC designs and compared with conventional DPD approaches. EVM and adjacent channel power ratio (ACPR) can be improved by up to 6 and 7 dB, respectively, outperforming conventional approaches.

Novel Baseband Equivalent Model for Digital Predistortion of Wideband Frequency-Multiplier-Based Millimeter Wave Sources

This article proposes a novel digital predistortion (DPD) scheme for mitigating the effects of nonlinear distortion caused by frequency multipliers when driven with wideband vector modulated signals. An effective pruning strategy is applied to limit the number of coefficients that consequently reduces the complexity of the DPD scheme while maintaining excellent linearization capacity. Extensive tests are conducted using different millimeter-wave frequency multipliers for proof-of-concept validation. These multipliers include two frequency doublers (25 and 28 GHz), a tripler (63 GHz), and a quadrupler (25 GHz), each driven by vector-modulated signals with an instantaneous bandwidth of up to 400 MHz. Using 44 coefficients or less, the proposed DPD approach allows for excellent frequency-doubler distortion cancellation and improves the error vector magnitude (EVM) and adjacent channel power ratio (ACPR) from about 21% and 21 dB to 1.8%-0.8% and 47-54 dB for the different test signals. Similarly, in the case of the frequency tripler, the EVM and ACPR improve from 8% and 30 dB to less than 1.7% and 45-51 dB after applying the proposed DPD scheme with 57 coefficients under different test signals. Finally, in the case of the frequency quadrupler (composed of two cascaded frequency doublers), the proposed DPD scheme achieves the EVM and ACPR of 0.9%-1.6% and 53-45 dB, respectively, with a higher number of coefficients.

A Reconfigurable Class-AB/F Power Amplifier for 0.1–4.2 GHz Multistandard Applications

In this paper, a reconfigurable multi-mode Class-AB/F power amplifier (PA) is proposed for 0.1–4.2 GHz multistandard applications. The PA operates in linear mode (class-AB) for variable-envelope modulated signals and switching mode (class-F) for constant-envelope modulated signals. The proposed linear mode PA design is suitable for multi-band LTE, IOT, WSN and multi-standard RF transmitter, while switching mode PA design can be used in multi-band IOT-LPWA and BLE (Bluetooth Low Energy) RF transmitter. The proposed PA has a reconfigurable off-chip inter-stage and output matching networks over the specified frequency band, while the input stage is Complementary Current-Reuse common-gate with active shunt feedback configuration to achieve Ultra-Wideband (UWB) input matching. The proposed multi-mode PA is designed using a 130 nm CMOS process. Class-AB PA has a saturated output power of 23.5 dBm ± 1 dB over 0.1–4.2 GHz, a power-added efficiency (PAE) of 41%, a third-order intercept point (OIP3) of 17 dBm, and adjacent channel power ratio (ACPR) of − 29.3 dBc for LTE 15 MHz channel bandwidth. The maximum PAE of 62.1% under the class-F operation is achieved at output power of 24.5 dBm. The PA occupies 0.64 mm2 of chip area, while the estimated off-chip area is 13.3 mm2. The proposed PA consumes 164 mW, and 16 mW in class-AB and class-F, respectively.

Spectral analysis of GFDM modulated signal under nonlinear behavior of power amplifier

Generalized frequency division multiplexing (GFDM) is a flexible non-orthogonal waveform candidate for 5G which can offer some advantages such as low out-of-band emission and high spectral efficiency. This paper investigates the effects of nonlinear behavior of practical power amplifier (PA) on the GFDM spectrum. A closed form expression for power spectral density (PSD) of GFDM signal is extracted. Then, PSD at the output of PA as a function of input power and the coefficients of nonlinear polynomial PA model is derived. In addition, the adjacent channel power (ACP) and ACP ratio, as two important performance metrics, are evaluated. The simulation results confirm the accuracy of derived analytical expressions. Moreover, to validate the performance of GFDM modulation after nonlinear PA, it is compared with orthogonal frequency division multiplexing modulation.

I/Q Imbalance Compensation in Wideband Millimeter-Wave Transmitters Using a Single Undersampling ADC

In this paper, a new method to identify and compensate for the I/Q imbalance in wideband millimeter-wave transmitters using a single undersampling analog-to-digital converter (ADC) is proposed. The proposed method alleviates the need for an I/Q demodulator; hence, simplifying the structure and calibration procedure of the required transmitter-observation receiver (TOR). In addition, an algorithm for estimating the delay and phase offsets between the transmitter and the single-ADC TOR is devised. The presented algorithm improves upon the exhaustive search methods employed in the literature. Measurement results using an off-the-shelf I/Q modulator, driven by an 800 MHz test signal, show about a 5% reduction in the root normalized mean-square error (RNMSE) of its output signal when the proposed method is utilized. Further measurements were conducted to assess the performance of this method, in conjunction with digital predistortion (DPD), when a power amplifier (PA) is added to the transmitter chain. When compared with the application of DPD only, the I/Q imbalance correction allowed additional reductions of about 4% in the RNMSE and 1.5 dB in the adjacent-channel power ratio of the PA output signal. These improvements were obtained with ADC sampling rates as low as 20 times below the Nyquist rate.

Suppression of third-order intermodulation distortion in analog photonic link based on an integrated polarization division multiplexing Mach–Zehnder modulator

A simple and linear analog photonic link (APL) based on a single integrated polarization division multiplexing Mach–Zehnder modulator (PDM-MZM) is proposed with suppressed third-order intermodulation distortion (IMD3). By properly selecting the modulation indexes of radio frequency (RF) signals and bias angles in the two sub-modulators, the electric/optical power ratio is changed and thus two nonlinear distortion signals with opposite phases are constructed to cancel out IMD3 of the link. Therefore, the IMD3 can be suppressed and the spurious-free dynamic range (SFDR) of the system can be improved. Only one electrode in each sub-modulator is used in the experiment. Experimental results show that compared with the conventional link based on a single MZM, 33.7-dB reduction of IMD3 is achieved and an enhancement of 17.6 dB in SFDR can be obtained. Besides, the proposed APL is test by a 16 quadrature amplitude modulation (QAM) RF signal and the error vector magnitude (EVM) and adjacent channel power ratio (ACPR) of the link are measured.

Efficiency and linearity enhancement of a two‐stage X‐band PA through simultaneous gate and drain supply modulation

This study addresses an analogue method for mitigating the non-linearities introduced by discrete supply modulation of a high-efficiency power amplifier (PA). A 10 W two-stage X-band gallium–nitride monolithic microwave integrated circuit ( PA with a peak power-added efficiency of 55%, is tested with drain supply modulation from 10 to 20 V with an increase in efficiency and substantial degradation in linearity. In this work, the authors characterise the two-stage PA dynamically to develop shaping functions for both gate bias voltages. They demonstrate that gate modulation can improve back-off gain and linearity, specifically when gate biases of the two stages of a PA are independently modulated. Simultaneous gate and drain modulation results in 15 percentage point improvement in efficiency over a static supply, and a consistent improvement in noise power ratio over a static supply, for a 20 MHz noise-like signal. Results with a 20 MHz long-term evolution signal show comparable improvement in efficiency while maintaining adjacent channel power ratio near the level of the PA with a static supply.

A Methodology and a Metric for the Assessment of the Linearizability of Broadband Nonlinear Doherty Power Amplifiers

This letter proposes a novel methodology and a metric for the assessment of the linearizability of broadband nonlinear power amplifiers (PAs). Validation of the proposed methodology and the proposed metric on two linearized Doherty PAs (DPAs) using digital predistortion (DPD) technique was carried out and it demonstrated the suitability and appropriateness of the new metric. Different from the iterative optimization procedure between the PA circuit design and the DPD algorithm compensation, the proposed method aims to provide a quantitative criterion on the PA linearizability based on its frequency-dependent amplitude modulation (AM)/AM and AM/phase modulation (PM) characteristics. To verify the effectiveness of the metric, two DPAs were characterized before and after a DPD-based linearization. The average correlation coefficients between the values of the metric and the adjacent channel power ratio after DPD were 0.8763 and 0.9156, and that between the values of the metric and the error vector magnitude after DPD were 0.8618 and 0.7200 for PA1 and PA2, respectively, indicating that the evaluation method and the linearizability metric can be used as a good measure to assess the linearizability of broadband PAs.

Input-Harmonic-Controlled Broadband Continuous Class-F Power Amplifiers for Sub-6-GHz 5G Applications

A comprehensive analysis is presented for investigating the effects of input nonlinearity on performance and broadband design of continuous-mode class-F power amplifiers (PAs). New time-domain waveforms are derived considering input and output harmonic terminations for continuous-mode class-F operation. The derived design equations show that the typical fundamental load design space of a continuous class-F PA must be reengineered in the presence of second-harmonic input nonlinearity to new design space in order to achieve optimum class-F PA performance versus varying second-harmonic load impedance. For the practical validation, the impacts of input nonlinearity on the performance of continuous-mode class-F PAs are first confirmed with pulsed vector load–pull (VLP) measurements on a low-power GaN 2-mm device. Second, a broadband high-power GaN 24-mm part is designed following the proposed theory with in-package input second-harmonic terminations targeting 1.75–2.3-GHz frequency band for the sub-6 GHz 5G high-power applications. Efficiency higher than 65% with peak power more than 53.2 dBm was maintained over the target frequency band, with excellent flatness. Third, a Doherty PA is implemented based on the designed GaN 24-mm part to evaluate the broadband performance with modulated stimuli. Using a multicarrier signal having an instantaneous bandwidth of 395 MHz, the average drain efficiency of the Doherty PA at 8-dB output back-off is higher than 44%, and the linearized adjacent channel power ratio (ACPR) is better than −52 dBc.

Investigation on harmonic spur characteristics of hybrid integrated LDMOS and AlGaN / GaN power amplifiers at different temperatures

The harmonic spur characteristics of a hybrid integrated S-band power amplifier (PA), consisting of both stages of LDMOSFET and AlGaN/GaN HEMT, are studied at different temperatures. The PA offers a peak output power of 50 dBm (100 W) with power added efficiency higher than 50%, and adjacent channel power ratio performance is less than −30 dBc. A temperature test chamber is employed for measuring the harmonic spur of PA from 233 to 393 K, and its linear response to temperature is captured at high output power level.

Load‐modulation technique without using quarter‐wavelength transmission line

A proposed method for achieving active load-modulation technique without using a quarter-wavelength transmission line is discussed and evaluated. The theoretical analysis shows that the active load-modulation can be achieved without using a quarter-wavelength line, where the main amplifier sees a low impedance when the input signal level is low, and this impedance increases in proportion to the amount of current contributed from the peaking amplifier. The peaking amplifier sees an impedance decreasing from infinity to the normalized impedance. To validate the method, a circuit was designed, simulated and fabricated using two symmetrical gallium nitride (GaN) transistors (6 W) to achieve a peak power of 12 W and 6 dB output back-off efficiency. The design operates with 400 MHz bandwidth at 3.6 GHz and showed an average efficiency of 50% at 6 dB back-off and an efficiency of 75% at peak power. The designed circuit was tested with CW and modulated signals, the amplifier showed an Adjacent Channel Power Ratio (ACPR) of 31–35.5 dB when tested with a wideband code division multiple access signal of 6 dB peak-average-power ratio (PAPR) at 35.5 dBm average power. Additional 20 dB of linearity improvement was achieved after adding a lineariser.

Multiband Dual-Mode Doherty Power Amplifier Employing Phase Periodic Matching Network and Reciprocal Gate Bias for 5G Applications

This article presents a novel method to design the multiband Doherty power amplifier (DPA). It is illustrated that phase periodic matching networks (PPMNs) can be used as multiband impedance inverters, off-set elements, and phase compensators to realize multiband DPAs. Moreover, the number of Doherty operation bands can be further increased by employing the reciprocal gate biases. A six-band dual-mode DPA with 1.8-2.2-/3.9-4.3-GHz operation bands in Mode I and 1.52-1.72-/2.38-2.53-/3.67-3.82-/4.53-4.68-GHz operation bands in Mode II using commercial GaN transistors is designed and implemented to validate the proposed method. The fabricated DPA achieves 8.7-13.5-dB gain and 39.6-41.5-dBm peak output power at all the designed bands. Drain efficiency of 49.2%-54.5% and 42.2%-56.7% is measured at a 6-dB output back-off in Mode I and Mode II, respectively. When stimulated by a five-carrier 100-MHz OFDM signal with a 7.7-dB peak-to-average power ratio (PAPR), adjacent channel power ratio (ACPR) of better than -48.9 dBc can be obtained by the proposed DPA after digital predistortion with 35.5%-50.1% average drain efficiency at 1.65/1.95/2.45/3.75/4.1/4.6 GHz, respectively.

Efficient linearisation technique for crosstalk and power amplifier non‐linearity suitable for massive MIMO transmitters

Massive multi-input–multi-output (MIMO) is expected to be an eminent technique to meet the demands of high system capacity and data rates of wireless networks in 5G wireless communication. However due to inherent imperfections of the transmitter such as power-amplifier (PA) non-linearity and crosstalk, practically, the signal quality suffers and does not reap sufficient benefits from the various MIMO techniques. Digital predistortion (DPD) is a popular technique for single-input–single-output transmission to enhance signal quality. This study examines the issue of high DPD's complexity in mitigating imperfections in MIMO transmitters. This work proposes a less complex, novel DPD model for linearising large-scale MIMO transmitters along with its characterisation procedure. The proof-of-concept is provided with the measurement setup containing 4 × 1 MIMO transmitters in the presence of non-linear crosstalk, linear crosstalk, and strong PA non-linearity. The proposed model performs comparably to the state-of-art DPD models like parallel Hammerstein and dual-input crosstalk mismatch with lower number of floating-point operations (flops). The proposed model improves adjacent channel power ratio up to − 54.13 dBc and error vector magnitude up to 1.08% for LTE signal of 40 MHz bandwidth.

Frequency Multiplier-Based Millimeter-Wave Vector Signal Transmitter Using Digital Predistortion With Constrained Feedback Bandwidth

We have demonstrated a frequency multiplier-based multiplying transmitter (MT) architecture, which shows the transmission of wideband modulated signals from the lower frequency band to the millimeter-wave (mm-wave) through the frequency multiplier directly is a viable option. To compensate for the severe nonlinear distortions exhibited by the frequency multiplier in a more efficient way, a two-stage cascaded digital predistortion (DPD) scheme with constrained feedback bandwidth is proposed. The complexity-reduced generalized memory polynomial (GMP) and $N$ th-order power/root module are used for nonlinear behavioral modeling. Furthermore, the spectral extrapolation and band-divided (BD) modeling methods are employed to achieve more accurate linearization performance of the frequency multiplier over the limited feedback bandwidth. The MT experimental system with an active frequency quadrupler at the Q-band was set up to evaluate the linearization capacity of the proposed BD $N$ th-order cascaded complexity-reduced GMP (BD-N-CGMP) DPD scheme. In the test for 24-MHz bandwidth 16 quadrature amplitude modulation (QAM) signal, the frequency quadrupler’s linearized output at 48.6 GHz with error vector magnitude (EVM) of 1.94% and adjacent channel power ratio (ACPR) of −47.2 dBc could be achieved, even when the feedback bandwidth was limited from 480 to 78 MHz. This demonstrated system significantly decreased the requirement of the digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) sampling rate, and showed promising performances for future MT architecture at mm-wave and sub-terahertz (sub-THz) frequencies with large signal bandwidth.

A 20–32-GHz Quadrature Digital Transmitter Using Synthesized Impedance Variation Compensation

This article presents a broadband quadrature digital transmitter (TX) architecture for part of the fifth-generation new radio (5GNR) frequency range 2 (FR2) and backhaul communication. Synthesized impedance variation compensation (IVC) is introduced to improve the efficiency by manipulating the load impedance variation of sub-arrays in the power digital-to-analog converter (power-DAC) at mm-wave. The operation bandwidth is extended by 5 GHz with reconfigurable circuits of output matching in power-DAC, interstage matching, and quadrature signal generator. A mixed-signal sign map is adopted to provide LO gain as well as constellation quadrant selection. As a proof of concept, a 2×10 -bit 20-32-GHz quadrature digital TX is designed and fabricated in 28-nm CMOS technology. With a 1-V supply, the proposed quadrature digital TX achieves the peak output power of 19.02 dBm at 22.5 GHz, the peak drain efficiency of 34.4% at 22 GHz, and the peak system efficiency of 22.1% at 22 GHz. At 23/28 GHz, it demonstrates the EVM of -28.9/-28.4 dB, the average power of 9.96/9.17 dBm, and adjacent channel power ratio (ACPR) of -33.6/-33.3 dBc for 3-Gb/s 64-QAM modulation, respectively. It also supports 1-Gb/s 256-QAM modulation signal.