Adaptive Frequency Calibration Technique Research Articles

A fast AFC technique with self-calibration for fast-locking PLLs

A fast adaptive frequency calibration (AFC) technique with self-calibration for fast-locking phase-locked loops is presented with frequency-selecting switches. The proposed AFC directly calculates the proper switch states of the voltage-controlled oscillator (VCO). It requires only six clock cycles of the reference oscillator regardless of the number of VCO switches to reach the final switch state in the ideal case. The proposed method counts the number of VCO cycles per reference clock period for the minimum VCO frequency (MIN) and the maximum VCO frequency (MAX) during the first four-clock periods. For the following two-clock periods, the proper states of the VCO switches are set to the calculated value from MIN, MAX and the desired division ratio for a target frequency (EST). A frequency synthesiser with the proposed AFC was implemented on a 0.18 µm CMOS process. The AFC time decreased from 40 to 0.4 µs employing the proposed scheme such that the total lock time is 40 µs with the loop bandwidth of 40 kHz.

A wide range sigma—delta fractional-N frequency synthesizer with adaptive frequency calibration

A wide range fractional-N frequency synthesizer in 0.18 μm RF CMOS technology is implemented. A switched-capacitors bank LC-tank VCO and an adaptive frequency calibration technique are used to expand the frequency range. A 16-bit third-order sigma—delta modulator with dither is used to randomize the fractional spur. The active area is 0.6 mm2. The experimental results show the proposed frequency synthesizer consumes 4.3 mA from a single 1.8 V supply voltage except for buffers. The frequency range is 1.44–2.11 GHz and the frequency resolution is less than 0.4 kHz. The phase noise is −94 dBc/Hz @ 100 kHz and −121 dBc/Hz @ 1 MHz at the output of the prescaler with a loop bandwidth of approximately 120 kHz. The performance meets the requirements for the multi-band and multi-mode transceiver applications.

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate in a wide-band frequency range, a switched-capacitors bank LC tank voltage-controlled oscillator (VCO) and an adaptive frequency calibration (AFC) technique are used. The measured VCO tuning range is as wide as 600 MHz (40%) from 1.15 to 1.75 GHz with a tuning sensitivity from 5.2 to 17.5 MHz/V. A 3-bit fourth-order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz as well as agile switching time. The experimental results show -80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129 dBc/Hz out-of-band phase noise at 400-kHz offset frequency. The fractional spurious is less than -70 dBc/Hz at 300-kHz offset frequency and the reference spur is -75 dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.