Active Zero State PWM Research Articles

An energy efficient control method of a photovoltaic system using a new three-phase inverter with a reduced common mode voltage

This paper presents a new energy-efficient space vector pulse width modulation (SVPWM) for controlling the switches of a New three-phase inverter (NTPI) for photovoltaic (PV) applications to reduce switching losses, the peak value, and the dv/dt of the common mode voltage (CMV) with fewer number of switches. The proposed system offers a reliable operation in PV energy system with less leakage current and increased efficiency because of the reduction of the CMV, the source of leakage current in PV inverter-based application. Moreover, this also optimizes the operation of electric vehicle application with lower bearing failure. The performance of the proposed system with the new SVPWM is evaluated to the existing PWM in the literature, as well as the active zero state pulse width modulation (AZSPWM) of the two-level inverter introduced under identical conditions. Experiments and MATLAB simulations have both been used in this study.

A Model Predictive Control Scheme with Minimum Common-Mode Voltage for PMSM Drive System Fed by VSI

Common-mode voltage (CMV) brings shaft voltage and shaft current, and corrodes the bearings of the permanent-magnet synchronous machine (PMSM), which affects the reliability of the whole PMSM drive system. Since the CMV applied by the zero voltage vectors (ZVVs) is three times that applied by the active voltage vectors (AVVs), a modulation scheme achieving minimum CMV without ZVV is proposed and introduced into the model predictive control structure for the PMSM drive system. Firstly, the whole modulation range is divided into three regions, including the low voltage modulation region (LVMR), high voltage modulation region (HVMR), and over-voltage modulation region (OVMR). Meanwhile, the regional boundary expression is derived. Then, the active zero-state pulse width modulation (AZSPWM) is adopted in LVMR. To improve the steady-state performance, near-state pulse width modulation (NSPWM) without opposite ZVVs is applied to the HVMR. Furthermore, when the reference voltage vector (VV) is located in OVMR, an optimal scheme is proposed to improve the dynamic response. Under the premise of no ZVV existing in the whole modulation region, simulation and experimental results show that the proposed hybrid modulation method can improve the steady-state and dynamic performance of the PMSM drive system.

Research on Analysis and Suppression Methods of the Bearing Current for Electric Vehicle Motor Driven by SiC Inverter

The silicon carbide (SiC) inverter brings great advantages to the motor drive systems of new energy vehicles; however, severe challenges to the bearings also happen. The high dc bus voltage and switching frequency of SiC inverter can increase the discharge frequency and energy when the bearing grease film collapses. As a result, the bearing suffers severe electric corrosion, and the service life of the motor drive system can be shortened. In this paper, the characteristics of common-mode voltage and bearing voltage are analyzed, firstly under space vector pulse width modulation (SVPWM). After that, the common-mode equivalent circuit model of the motor drive system is established. The frequency characteristics of bearing voltage are revealed, and the safe working area is determined. Then, the frequency characteristics of bearing voltage and current are verified based on IGBT and SiC inverters in experiments. After that, by designing a common-mode filter, the bearing voltage and current are significantly attenuated. Furthermore, the active zero state PWM (AZSPWM) is adopted to reduce the common-mode voltage from the inverter. At the same time, combined with the common-mode filter, the bearing voltage and current are further reduced. The experimental results show that the switching frequency has a decisive effect on the amplitude of bearing voltage and current. The bearing voltage can be attenuated to around half of the reference bearing voltage by using the common-mode filter and AZSPWM strategy, respectively. The combination of the common-mode filter and AZSPWM strategy can reduce the bearing voltage to around one-fourth of the reference bearing voltage, which can effectively reduce the breakdown time and discharge energy of the grease oil film.

ANFIS based AZSPWM methods for reduction common mode voltage in asynchronous motor drive

<div class="keywords">Space vector pulse width modulation (SVPWM) is a popular technique in the field of variable frequency induction motor drives. It gives better working and good direct current bus utilization in comparison to the sinusoidal PWM (SPWM) method. However, it decreases harmonic fluctuations and generates high common mode voltage (CMV) fluctuations, which results in common mode currents inside the motor. Hence, the performance of the motor may be deteriorated. To reduce the CMV, this paper presents a family of active zero state PWM (AZSPWM) methods using an adaptive neuro-fuzzy interference system (ANFIS). The proposed approach uses a five-layer hybrid learning algorithm for training the network. The training data is obtained from the classical SVPWM method. To analyze the proposed PWM methods, simulation is carried out using MATLAB and evaluated.</div>

An Improved Modulation Method for Suppressing High Frequency Common-Mode Voltage in SiC Motor Drive System

High-frequency common-mode voltage generated by inverters causes severe negative effects, particularly in silicon carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)-driven motors. Additionally, common suppression strategies would increase hardware expenses or sacrifice the switching speed of SiC devices. This article proposes an improved no-zero vector modulation strategy to suppress high-frequency common-mode voltage without increasing the cost of hardware. In this method, only nonzero vectors are utilized to reduce common-mode voltage. Firstly, the influence of different switching states on the characteristics of SiC MOSFETs has been studied by double-pulse tests, which explains why zero vectors will cause more serious voltage oscillations. Secondly, common-mode voltage suppression failure caused by the high-frequency dead zone effect has been analyzed in detail. Based on traditional Active Zero State Pulse Width Modulation (AZSPWM), complementary device conduction logic and dead-zone compensation methods are proposed. In switching moments, different turn-on logic is selected to ensure that only one switch acts, and different dead zone compensation methods are selected to deal with the common-mode suppression failure, which effectively avoids high-frequency common-mode voltage spikes. Finally, simulation and experimental results verify that the improved modulation algorithm can effectively suppress high-frequency common-mode voltage.

Analytical Characterization of CM and DM Performance of Three-Phase Voltage-Source Inverters Under Various PWM Patterns

The need for analytical models and tools to investigate common-mode (CM) and differential-mode (DM) signals in motor drive systems is evident in previous literature, which focuses on simulations and experiments. In this article, an analytical model of CM voltage (CMV) for various pulsewidth modulation (PWM) schemes is presented as a double Fourier integral (DFI) and the DM current (DMI) is described by mathematical equations. The model is applied to different modulation schemes such as space vector PWM, two types of discontinuous PWM, and active zero state PWM (AZSPWM) for two-level and three-level multiphase inverters. The impact of these four modulation schemes on the CMV and DMI is comprehensively compared across varying modulation indices. The DFI model shows that while AZSPWM has the lowest CMV around the switching frequency, it has increased sideband CMV. However, it still yields the best total CMV reduction overall. An SiC inverter is built to experimentally validate the analytical model with a range of switching frequencies of 10-40 kHz. In this system, a high-resolution field-programmable gate array (FPGA) is used to implement the control algorithm and assess the impact of control bandwidth on CMV and DMI.

Analysis and Suppression of Shaft Voltage in SiC-Based Inverter for Electric Vehicle Applications

SiC mosfet s allow a higher frequency, lighter weight inverter over their Si counterparts for electric vehicle (EV) applications. However, using SiC-based EV traction inverters is likely to increase the shaft voltage in an ac motor drive system, which significantly affects the reliability of the system. This paper investigates the impact of high-speed switching of SiC devices and high switching frequency of SiC-based inverter on the common-mode voltage (CMV) and the shaft voltage. It is theoretically illustrated and experimentally demonstrated that the high switching frequency increases the amplitude of the shaft voltage, while the fast switching speed has limited influence on both CMV and the shaft voltage. Afterward, active zero state pulsewidth modulation (AZSPWM) and common-mode chokes are employed to mitigate the shaft voltage. The experimental results show that either the AZSPWM modulation scheme or common-mode chokes have the capability to minimize the shaft voltage. Better performance can be achieved by utilizing both techniques simultaneously. It is also observed that the high switching frequency enabled by the fast-speed SiC device is able to be helpful to the use of reduced shaft voltage technologies.

A three-dimensional active zero state PWM for common-mode voltage reduction of a three-phase four-leg voltage-source inverter

PurposeThis paper aims to investigate the common-mode voltage (CMV) issue of a three-phase four-leg voltage-source inverter. A new space vector modulation method, named as three-dimensional active zero state Pulse-width modulation (PWM) (3-D AZSPWM), is proposed to reduce the CMV level.Design/methodology/approachPWM is a general method to generate the switching signals of the power converters in order to obtain high-quality output voltages. However, the CMV produced by PWM methods has become a serious problem. 3-D AZSPWM is proposed to solve this issue. In 3-D AZSPWM, instead of using zero voltage vectors with high CMV level, appropriate complementary non-zero vectors are introduced to synthesize reference vector. The proposed method is classified into four types of AZSPWM1(a), AZSPWM1(b), AZSPWM2(a) and AZSPWM2(b) based on different complementary vectors chosen for each type. An extend software simulation using MATLAB/Simulink is performed to verify the superior performance of the proposed methods.FindingsCompared to other reduced CMV methods, the proposed method not only reduces the CMV but also retains the positive characteristics of the three-dimensional classical space vector PWM (3-D CSVPWM).Originality/valueThe proposed method does not suffer from linear modulation region limitation and also does not impose additional switching loss. Furthermore, calculated output voltage harmonic distortion factor illuminates acceptable quality of output voltage produced by the proposed method.

EMI Noise Reduction with New Active Zero State PWM for Integrated Dynamic Brake Systems

EMI Noise Reduction with New Active Zero State PWM for Integrated Dynamic Brake Systems

A New Active Zero State PWM Algorithm for Reducing the Number of Switchings

To reduce common-mode voltage (CMV), various reduced CMV pulse width modulation (RCMV-PWM) algorithms have been proposed, including active zero state PWM (AZSPWM) algorithms, remote state PWM (RSPWM) algorithms, and near state PWM (NSPWM) algorithms. Among these algorithms, AZSPWM algorithms can reduce CMV, but they increase the number of switchings compared to the conventional space vector PWM (CSVPWM). This paper presents a new AZSPWM algorithm for reductions in both the CMV and total number of switchings in BLAC motor drives. Since the proposed AZSPWM algorithm uses only active voltage vectors for motor control, it reduces CMV by 1/3 compared to CSVPWM. The proposed AZSPWM algorithm also reduces the total number of switchings compared to existing AZSPWM algorithms by eliminating the switchings required from one sector to the next. The performance of the proposed algorithm is verified by analyses, simulations, and experimental results.

Review on pulse‐width modulation strategies for common‐mode voltage reduction in three‐phase voltage‐source inverters

With wide application of inverters in modern industry, common-mode voltage (CMV) problems invoked severe negative effects. Hardware and software solutions have been proposed to reduce the CMV. Compared with hardware CMV mitigation solutions, software strategies based on pulse-width modulation (PWM) modifications have aroused widespread attention for their cost-effective and control flexible advantages. Up to date, various reduced CMV PWM (RCMV-PWM) strategies have been reported, such as active zero state PWM, remote state PWM, near state PWM, phase-shifted carrier PWM, carrier peak position modulation and so on. For convenience of understanding and utilising the existed RCMV-PWM strategies, this study conducts a review on this topic. According to the principle of CMV reduction algorithms, the study divides the reported RCMV-PWM strategies into three different categories. It also presents comparisons of CMV reduction techniques and output performances (like CMV value, output ripple and linearity range) between different strategies. Meanwhile, CMV suppression principles, problems in implementation and improvements of each technique are described in detail. Moreover, the inherent characteristics and development tendencies of the RCMV-PWM techniques are discussed so as to offer reference for further research.

Simple Carrier Based AZSPWM Algorithms for Vector Controlled Induction Motor Drive for Reduced Common Mode Voltage

Few simple carrier approach based Active Zero State Pulse Width Modulation (AZSPWM) algorithms are presented for vector controlled induction motor drives for reduced common mode voltage variations. Though, the classical space vector PWM (SVPWM) algorithm gives superior waveform quality, it gives large common mode voltage variations and the complexity involved is more. To overcome these drawbacks, a simple scalar (carrier comparison) approach has been presented in this paper. In the proposed approach, the modulating signals of the AZSPWM algorithms are derived in a simple form. By adding the suitable zero sequence signals to the instantaneous phase voltages, the modulating signals are derived. Then, by using two carrier signals, and by comparing the modulating signals and carrier waves the pulses are derived for the inverter devices. As the AZSPWM algorithms did not use the zero voltage vectors, the common mode voltage variations can be reduced from ±Vdc/2 to ±Vdc/6 when compared with the SVPWM algorithm. To show the effectiveness of the proposed AZSPWM techniques, the simulation studies have been carried out on vector controlled induction motor drive and results are presented and compared. The simulation results show the usefulness of the proposed AZSPWM algorithms.

Design of Hybrid PWM Algorithm for the Reduction of Common Mode Voltage in Direct Torque Controlled Induction Motor Drives

This paper presents a novel hybrid pulse width modulation (HPWM) technique for the reduction of common mode voltage (CMV) in direct torque controlled induction motor drives based on the concept of imaginary switching times. In the proposed approach, different active zero state PWM (AZPWM) sequences are considered in which the actual switching times are calculated based on the instantaneous values of phase voltages. Moreover AZPWM sequences utilize active voltage vectors for composing the reference voltage vector instead of using zero voltage vectors. But these sequences suffer from steady state ripples. To reduce the ripples in steady state, a HPWM technique is developed in which stator flux ripple analysis is done for all the AZPWM sequences in terms of actual switching times, dc link voltage (Vdc), sampling time period (Ts). To validate the proposed PWM algorithm, numerical simulation studies have been carried out using MATLAB-Simulink and results are presented and compared.

Common-Mode Voltage Reduction Pulsewidth Modulation Techniques for Three-Phase Grid-Connected Converters

This paper experimentally investigates the performance of three-phase voltage source pulsewidth modulation (PWM) converter, with the grid interfaced photovoltaic energy conversion system being the main application. In such applications the ground leakage current [common mode current (CMC)] should be much less than an ampere and this is difficult to obtain in transformerless (direct) connected systems. With the target being the reduction of the common mode voltage (CMV) and CMC, the converter performance is investigated thoroughly. Conventional PWM methods [space vector PWM (SVPWM) and discontinuous PWM (DPWM)] and recently developed reduced common mode voltage PWM (RCMV-PWM) methods [active zero state PWM (AZSPWM) and near state PWM (NSPWM)] are considered. The performance of a 1-kW rated PWM rectifier with additional common-mode capacitor emulating a PV system has been experimentally investigated. It is shown that the CMV and CMC of the tested RCMV-PWM methods is significantly less than conventional methods. In particular, NSPWM yields the best overall performance including low ground leakage current, low inverter output (phase current) and input (dc-link current) ripple, and low switching losses. Accounting for the parasitic capacitance effect, the resonant frequency of the common-mode circuit is identified and it is used in the converter design for the purpose of avoiding resonances involving large CMV-CMC. This paper aims help the design engineer select the appropriate PWM method for grid-connected applications and provides some design rules of thumb.