AC Gate Bias Research Articles

Roles of Trap States in the Dynamic Degradation of Polycrystalline Silicon Thin-Film Transistors Under AC Gate Bias Stress

Roles of Trap States in the Dynamic Degradation of Polycrystalline Silicon Thin-Film Transistors Under AC Gate Bias Stress

Gate Oxide Reliability and V<sub>TH</sub> Stability of Planar SiC MOS Technology

Similar charge to failure distributions with mean values of about 50 C/cm2 were measured for planar SiC MOSFETs and MOS capacitors. Fast occurring and saturating negative flatband and threshold voltage drops were found in time resolved 1 second long pulsed gate current stress with IG=1 mA/cm2 at T=150 °C. No substantial difference in VTH drift rate with VGS=28 V at T=150 °C was found after about 10 s recovery period for IG stressed devices compared with unstressed devices. Additionally, IG stressed and unstressed devices did not differ in final VTH shift at T=25 °C after VGS=28 V stress (during 3 hrs or 31 hrs). More gate oxide reliability characterization is important to determine if 1 mA/cm2 pulsed gate current stress creates any permanent changes to the SiC MOSFET device behaviour. Additionally, parametric shifts in VTH and RDSon was examined after long-term AC gate bias stress by a gate driver switching between-8V and 20V for four different commercially available SiC MOSFETs.

Thermal Annealing Improved Stability of Amorphous InGaZnO Thin-Film Transistors Under AC Bias Stresses

Amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) severely degrade under AC gate bias stress and AC drain bias stress, whose transfer curves respectively undergo positive shifts of 6.3 and 14.2 V after a stress time of 3000 s with a stress amplitude of 20 V. In this study, annealing at 400 °C in O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> atmosphere is performed to effectively reduce the acceptor-like trap states in the a-IGZO channel and the electric field in the etching-stop layer under the extended drain electrode, which participate in dynamic and DC degradation mechanisms, respectively. Thus, a-IGZO TFTs exhibiting excellent stability without any shift of the transfer curve under the same AC gate bias stress and AC drain bias stress are experimentally demonstrated simultaneously.

P‐3: Effects of Negative Bias Illumination Stress on IGZO Device and Luminance Behaviors in OLED Display Panel Operated by AC Conditions

Effects of light on InGaZnO (IGZO) thin film transistors were investigated under the AC gate bias illumination stress. DC NBIS on IGZO device results in dramatic negative Vth shifts. Whereas, Vth shift tends to disappear when the specific AC gate stress is applied with light exposure. We found that NBIS effect is released in specific pulse peak bias zone for fixed pulse frequency, base pulse voltage and duty. Hence, if we employ the pulse shape in specific zone, intrinsic reliability concerns over IGZO device particularly with NBIS would not be technical huddle for volume manufacturing production.

Dynamic Characterization of the Threshold Voltage Instability under the Pulsed Gate Bias Stress in 4H-SiC MOSFET

The threshold voltage (Vth) instability of 4H-SiC MOSFETs was investigated using high-speed IV measurement instrument. DC stress measurement of wide time span ranging from 10-6 to 103 s without relaxation effect was conducted. The high-speed measurement allowed of dynamic ΔVth measurement under pulsed AC gate bias stress. We investigated effects of NO POA in gate oxidation process on the Vth instabilities.

搭桥晶粒多晶硅薄膜晶体管栅交流电应力下的退化行为与退化机制研究

搭桥晶粒多晶硅薄膜晶体管栅交流电应力下的退化行为与退化机制研究

Abnormal degradation of high-voltage p-type MOSFET with n+ polycrystalline silicon gate during AC stress

We investigated the abnormal degradation of high-voltage p-type MOSFET (HV pMOSFET) under negative AC gate bias stress. In HV pMOSFET with n+ polycrystalline silicon (poly-Si) gate, the abnormal degradation occurs after the gradual degradation during negative AC stress. The abnormal degradation is suppressed by changing the gate material from n+ poly-Si to p+ poly-Si, and it is caused by hot holes produced by the impact ionization near the surface when electrons move from the gate toward the gate oxide. We suggest a possible mechanism to explain the improvement of degradation by using p+ poly-Si as a gate material.

Stretched-Exponential Trends in a-Igzo Tfts

A bias temperature stress (BTS) investigation of amorphous InGaZnO thin-film transistors (a-IGZO TFTs) is undertaken using the stretched-exponential (SE) relation to model the threshold voltage shift (ΔVTH) as a function of time, temperature, and applied gate voltage. Explicitly, the SE equation employed herein is described as ΔVTH (t, T, VG) = (VG-VTH0) (1-exp(-(t/τ)β)), where VTH0 is the initial unstressed TFT threshold voltage, τ is a trapping time, τ = τ0exp(Eτ/kBT), where τ0 is a trapping time prefactor, Eτ is an energy barrier, and β is an energy barrier parameter [1, 2]. Simulation indicates that a larger τ and/or β results in less ΔVTH, i.e., a more stable a-IGZO TFT. An alternate form of the SE voltage prefactor (VG-VTH0) involves the use of V0, which is identified as a saturation voltage [3, 4]. Either prefactor formulation can be used to accurately fit ΔVTH trends for stress times less than ~3 hours. However, as shown in Fig. 1, fitting of a sample data set restricted to stress times less than 3 hours leads to dramatically different saturated threshold voltage shifts, even though both prefactors precisely fit the initial 2 hours of data (see insert of Fig. 1). Physically, this is associated with the fact that the (VG-VTH0) prefactor corresponds to the applied overvoltage which explicitly depends on VG, while V0 is independent of VG. Simulation is useful for revealing various kinds of ΔVTH (t, T, VG) trends. For example, Fig. 2(a) shows that the relevant energy barrier, Eτ, associated with ΔVTH (10-5 s, 300 K, VG = 30 V) is very narrow for β = 1 and broadens dramatically as β → 0. The Eτ-β relationship is better represented by taking the derivative of ΔVTH with respect to Eτ, as shown in Fig. 2(b), where the magnitude of the peak increases and the distribution of Eτ narrows as β increases. As a larger β is indicative of a more stable TFT, it is reasonable to theorize that a narrow Eτ distribution is meaningful in predicting stable long-term TFT reliability. [1] M. Mativenga, et al., “High stable amorphous indium-gallium-zinc-oxide thin-film transistor using an etch-stopper and a via-hole structure,” Journal of Information Display, Vol. 12, No. 1, 47-50 (2011)[2] T. Y. Hsieh, et al., “Investigating degradation behavior of InGaZnO thin-film transistors induced by charge-trapping effect under DC and AC gate bias stress,” Thin Solid Films, 528, 53-56 (2013)[3] J. M. Lee, et al., “Bias-stress-induced stretched-exponential time dependence of threshold voltage shift in InGaZnO thin film transistors,” Applied Physics Letters, 93, 093304 (2008)[4] S. Park, et al., “Threshold voltage shift prediction for gate bias stress on amorphous InGaZnO thin film transistors,” Microelectronics Reliability, 52, 2215-2219 (2012) Figure 1

WITHDRAWN: Investigating degradation behavior of InGaZnO thin-film transistors induced by charge-trapping effect under DC and AC gate bias stress

WITHDRAWN: Investigating degradation behavior of InGaZnO thin-film transistors induced by charge-trapping effect under DC and AC gate bias stress

Investigating Degradation Behavior of InGaZnO Thin-Film Transistors Induced by Charge-Trapping Effect under DC and AC Gate-Bias Stress

This paper investigates the degradation mechanism of amorphous InGaZnO thin-film transistors under DC and AC gate bias stress. Comparing the degradation behavior at equal accumulated effective stress time, more pronounced threshold voltage shift under AC positive gate bias stress in comparison with DC stress indicates extra electron-trapping phenomenon occurs during the duration of rising/falling time in pulse. Contrarily, illuminated AC negative gate bias stress exhibits much less threshold voltage shift than DC stress, which suggesting the photo-generated hole does not has sufficient time to drift to the interface of IGZO/gate insulator and causes hole-trapping under AC operation. Since the evolution of threshold voltage fits the stretched-exponential equation well, the different degradation tendencies under DC/AC stress can be attributed to the different electron- and hole-trapping efficiencies, and this is further verified by varying pulse waveform.

Si Multidot FETs for Single-Electron Transfer and Single-Photon Detection

Recently, there have been increasing demands for controlling individual electrons, photons, and dopants in developing nm scale Si devices. Our most recent results on Si single-electron nano-devices will be presented. We have demonstrated single-electron transfer in random-tunnel-junctions by a cycle of ac gate bias, detection of photons and detection of individual acceptor ions by Si single-hole transistor.

Stability of polysilicon thin film transistors under switch operating

Ageing of low temperature polysilicon Thin Film Transistors (TFTs) under AC gate bias stress is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique. The drain and source regions are in-situ doped during the LPCVD deposition by using phosphine to fabricate n-type transistors. The active layer and the drain arid source regions are Solid Phase Crystallized. The field effect mobility is higher than 100 cm2/V.s, the subthreshold slope around 0.6 V/dec, the threshold voltage around 0.2V and the switching time around 370 nsec.As these TFTs are commonly used as switching devices in the most of applications in large area electronics field, the study of their stability under AC electrical stress is important. The present work shows that the effect of the positive or negative DC stress is higher than that of the AC stress and then the degradation of polysilicon TFTs is over-estimated when it is checked from the effects of DC gate bias stress.Degradation under bias stress is shown to originate from the creation of gap states at the channel-interface oxide and in the channel material. The lower influence of the AC stress is explained from an annealing effect of the created states by the application of an opposite sign bias stress.

High-frequency annealing effects on ionizing radiation response of MOSFET

The effects of high-frequency AC bias on the ionizing radiation response of MOSFETs are studied. Radiation-induced interface traps are annealed out during irradiation and postirradiation annealing when an AC bias is applied with a zero offset voltage. In addition, the recovery of 40-MHz-biased devices agreed with that of 860-MHz-biased ones for the same total number of alternating cycles of AC gate bias voltage. It is concluded that an alternating transition between inversion and accumulation caused by high-frequency AC bias is responsible, and the total number of transition cycles may be relevant for the annealing of radiation-induced interface traps. >