Ab Initio Quantum Transport Simulations Research Articles

Unit cell restricted Bloch functions basis for first-principle transport models: Theory and application

We present the theory and the application of a first-principle transport model employing a basis set obtained directly from the ab initio Bloch functions. We use a plane-wave density functional theory Hamiltonian and show that a judicious choice of the reduced basis set can effectively suppress the potentially thorny problem of the unphysical solutions. Our methodology enables ab initio transport simulations with a huge reduction of the size of the problem compared to the original ab initio formulation. Moreover, the approach can also be used for local and nonlocal empirical pseudopotential Hamiltonians, thus promising a wide range of possible applications. We report results for ab initio simulations of ${\mathrm{MoS}}_{2}$ field effect transistors, where the transport and electrostatics equations are solved self-consistently for channel lengths up to about 20 nanometers. The simulation results rapidly converge with the size of the basis set, so that the blocks of the Hamiltonian matrix can be reduced to a size below 100. Our methodology is a viable approach for ab initio and semiempirical quantum transport simulations and, in particular, it offers an alternative to the use of maximally localized Wannier functions.

Ohmic contacts of monolayer Tl2O field-effect transistors

Monolayer (ML) Tl2O, as a newly discovered metal-shrouded two-dimensional semiconductor with an appropriate bandgap and high carrier mobility, is a promising candidate as the channel materials for the next-generation field-effect transistors (FETs). Using ab initio electronic structure calculation and quantum transport simulation, the contact properties of ML Tl2O–metal interfaces based on FET are comprehensively investigated with Au, Sc, Tl, Ni, graphene, Ti2C, Ti2CF2, and Ti2C(OH)2 electrodes. ML Tl2O undergoes metallization with Au, Sc, Tl, Ni, and Ti2C, while it forms van der Waals-type contact with graphene, Ti2CF2, and Ti2C(OH)2. An n-type lateral Schottky contact is formed with Ni, Au, Sc, and Ti2C electrodes with the electron Schottky barrier height (SBH) of 0.25, 0.27, 0.27, and 0.36 eV, respectively, while a p-type lateral Schottky contact is formed with graphene electrode with the hole SBH of 0.10 eV. Surprisingly, a desired n-type Ohmic contact arises with Tl and Ti2C(OH)2 electrodes and a desired p-type Ohmic contact arises with Ti2CF2 electrode. The study not only provides a deep understanding of the interfacial properties of the ML Tl2O FETs but also reveals a versatile approach to realize both n- and p-type Ohmic contact for the ML Tl2O FETs.

Performance Limit of Monolayer WSe2 Transistors; Significantly Outperform Their MoS2 Counterpart.

With the scaling limits of silicon-based MOS technology, the critical and challenging issue is to explore more and more alternative materials to improve the performance of devices. Two-dimensional (2D) semiconductor WSe2 with a proper band gap and inherent stability under ambient conditions makes it a potential channel material for realizing new generation field-effect transistors (FETs). In light of the low on-state current of the experimental sub-10 nm 2D MoS2 FETs, we explore the limitation of the monolayer (ML) WSe2 device performance by using accurate ab initio quantum transport simulation. We find that the sub-10 nm 2D WSe2 FETs apparently outperform their MoS2 counterpart. The on-state current of the optimized p-type ML WSe2 FETs can satisfy the criteria of the International Technology Roadmap for Semiconductors (ITRS) on both the high-performance (HP) and low-power (LP) devices until the gate length is scaled down to 2 and 3 nm, respectively. By the aid of the negative capacitance effect, even the 1 nm gate-length WSe2 MOSFETs can satisfy both the HP and LP requirements in the ITRS 2028 completely. Remarkably, the ML WSe2 MOSFET has the highest theoretical on-current in LP application among the examined 2D MOSFETs at the 5 nm gate length to the best of our knowledge.

High-performance III-VI monolayer transistors for flexible devices.

Group III-VI family MX (M = Ga and In, and X = S, Se, and Te) monolayers have attracted global interest for their potential applications in electronic devices due to their unexpectedly high carrier mobility. Herein, via density functional theory calculations as well as ab initio quantum transport simulations, we investigated the performance limits of MX monolayer metal oxide semiconductor field-effect transistors (MOSFETs) at the sub-10 nm scale. Our results highlighted that the MX monolayers possessed good structural stability and mechanical isotropy with large ultimate strains and low Young's modulus, which are intensely anticipated in the next-generation flexible devices. More importantly, the MX monolayer MOSFETs show excellent device performance under optimal schemes. The on-state current, delay time, and power dissipation of the MX monolayer MOSFETs satisfy the International Technology Roadmap for Semiconductors (ITRS) 2013 requirements for high-performance devices. Interestingly, the sub-threshold swings were in a very low range from 68 mV dec-1 to 108 mV dec-1, which indicated the favorable gate control ability for fast switching. Therefore, we believe that our findings shed light on the design and application of MX monolayer-based MOSFETs in next-generation flexible electronic devices.

A 10 nm Asymmetric Graphene–Rhenium Disulfide Field‐Effect Transistor for High‐Speed Application

Field‐effect transistor devices with exfoliated 2D materials are potent in various optical and electronics applications including photodetectors, valleytronics, spintronic, circuits, memory, and optical modulators. However, these devices endure limited gate control, low carrier mobility, and high operating voltage. This study introduces a new asymmetric graphene–rhenium disulfide heterojunction Schottky barrier metal–oxide–semiconductor field‐effect transistor engineered with high graphene carrier mobility and high rhenium disulfide Ion–off ratio in a 10 nm channel‐length device. The proposed device has better gate control ability, Ion–off ratio of 106, high carrier mobility (87.44 cm2 V−1 s−1), and low subthreshold swing of 43.12 mV dec−1 in the subthreshold region at 0.05 V applied drain voltage. The significant reduction in subthreshold swing at low voltage opens a suite of high‐switching‐speed low‐powered nanologic applications for the upcoming Internet‐of‐Things era. The material properties of graphene–rhenium disulfide heterojunctions are derived using an ab initio quantum transport simulation tool.

Planar Direction‐Dependent Interfacial Properties in Monolayer In2Se3–Metal Contacts

2D semiconductor materials are promising channel materials in the next generation of field‐effect transistors (FETs). Recently, 2D In2Se3 has been fabricated and predicted to present planar direction‐dependent electrical properties. Herein, ab initio quantum transport simulations are used to explore the interfacial properties between monolayer (ML) In2Se3 and a series of common metal electrodes in a FET. By reversing the planar direction of ML In2Se3, different lateral interfacial properties are obtained: A highly desirable n‐type ohmic contact is shaped between Au and up‐directed ML In2Se3; however, a p‐type Schottky contact appears when the direction is switched. In addition, Ag can generate desirable lateral n‐type ohmic contact with both the directions of ML In2Se3. A reversion from n‐ to p‐type lateral Schottky contact occurs in both In and Sc when the direction switches from up to down. Down‐directed ML In2Se3 is dynamically unstable with the Pt and transforms into up‐direction to form a p‐type ohmic contact. The average pinning factor is 0.12 and 0.09 for up‐and down‐directed ML In2Se3, respectively, implying a strong Fermi‐level pinning. Therefore, the planar direction‐dependent interfacial properties of ML In2Se3–metal contacts are understood deeply, which can be exploited for the ML In2Se3 FET devices.

Interfacial charge transfers and interactions drive rectifying and negative differential resistance behaviors in InAs/graphene van der Waals heterostructure

Vertical heterostructures of two-dimensional (2D) materials are excellent candidates for designing next-generation electronic devices with superior performance. By using both ab initio electronic calculations and quantum transport simulations, we investigated the electronic and transport properties of InAs/graphene heterostructure. The results reveal that electrons and holes accumulate at different layers after the adsorption of InAs layer, forming the built-in electronic field at the interface. The electrostatic potential energy of InAs layer is higher than that of graphene, and it favors more electrons transferring from InAs to graphene layer. Comparing the comment methods by introducing impurity and carriers' injection, rectifying and negative differential resistance behaviors can also be realized by the combined effects of electron-hole distribution, interfacial hybridization, and contact barrier in InAs/graphene heterostructure device. It shows that the rectifying ration gradually increases with bias voltage, and the negative differential resistance effect happens at either positive or at negative bias voltage regions. Electrostatic potential distribution and contact barrier play important roles in determining transport properties. Increasing interfacial hybridization is helpful for transmission enhancement in the weak interlayer interaction van der Waals heterostructure.

Negative capacitance tunneling field effect transistors based on monolayer arsenene, antimonene, and bismuthene

Monolayer hexagonal arsenene, antimonene, and bismuthene are emerging two-dimensional (2D) semiconductors. We explore the possibility of their applications on 10 nm gate long tunneling field effect transistors (TFETs) from the ab initio quantum transport simulation. We predict that the ML bismuthene TFET has the largest on-state current Ion (1153 μA μm−1) among the three checked hexagonal group V-enes ones for high-performance (HP) application. We further propose a prototype negative capacitance TFET, where a ferroelectric dielectric is adopted in the TFET to improve the device performance. The resulting Ion is dramatically elevated to 1868 μA μm−1, which has met the requirement of International Technology Roadmap for Semiconductors for HP devices (1450 μA μm−1). Therefore, the combination of 2D semiconductor channel and negative capacitance technique breaks the bottleneck of a very low on-state current of conventional TFETs.

Bilayer tellurene–metal interfaces

Tellurene, an emerging two-dimensional chain-like semiconductor, stands out for its high switch ratio, carrier mobility and excellent stability in air. Directly contacting the 2D semiconductor materials with metal electrodes is a feasible doping means to inject carriers. However, Schottky barrier often arises at the metal–semiconductors interface, impeding the transport of carriers. Herein, we investigate the interfacial properties of BL tellurene by contacting with various metals including graphene by using ab initio calculations and quantum transport simulations. Vertical Schottky barriers take place in Ag, Al, Au and Cu electrodes according to the maintenance of the noncontact tellurene layer band structure. Besides, a p-type vertical Schottky contact is formed due to the van der Waals interaction for graphene electrode. As for the lateral direction, p-type Schottky contacts take shape for bulk metal electrodes (hole Schottky barrier heights (SBHs) ranging from 0.19 to 0.35 eV). Strong Fermi level pinning takes place with a pinning factor of 0.02. Notably, a desirable p-type quasi-Ohmic contact is developed for graphene electrode with a hole SBH of 0.08 eV. Our work sheds light on the interfacial properties of BL tellurene based transistors and could guide the experimental selections on electrodes.

Excellent Device Performance of Sub‐5‐nm Monolayer Tellurene Transistors

AbstractThe merging 2D semiconductor tellurene (2D Group‐VI tellurium) is a possible channel candidate for post‐silicon field‐effect transistor (FETs) due to its high carrier mobility, high drive current, and excellent air stability. The performance limits of sub‐5‐nm ML tellurene metal‐oxide‐semiconductor FETs (MOSFETs) are explored by employing exact ab initio quantum transport simulations. An optimized p‐type ML tellurene MOSFET meets both the high performance (along both the armchair and the zigzag directions) and the low power (along the armchair direction) requirements of the International Technology Roadmap for Semiconductors (ITRS) at a gate length of 4 nm with a negative capacity dielectric. Hence, choosing ML tellurene as the channel material provides a novel route to continue the Moore's law to 4 nm.

Magnetic structure and magnetic transport properties of armchair arsenene nanoribbons

Inducing magnetism for arsenene is important for developing high-performance spintronic devices. Here, we investigate the electronic and magnetic properties of armchair arsenene nanoribbons doped with transition metal Mn atom by the ab initio electronic structure calculations and quantum transport simulations. It is found that such structures are stable by calculated formation energy and molecular dynamics simulation. Magnetic states can be obtained by doping Mn atom in such ribbons at different doping-positions with the distance from the Mn atom to the ribbon edges. AAsNR-Mn experiences a transition from a half-semiconductor to a half-metal by applying an external electric field. Moreover, it possesses an outstanding magnetic device nature, such as perfect spin filtering effect (100%), and a spin-valve feature with giant magnetoresistance (GMR) approaching 106%. Our calculation indicates AAsNRs-Mn has a promising application for multifunctional spintronic devices.

Performance of Monolayer Blue Phosphorene Double-Gate MOSFETs from the First Principles.

We systematically study the device characteristics of the monolayer (ML) blue phosphorene metal-oxide semiconductor field-effect transistors (MOSFETs) by using ab initio quantum-transport simulations. The ML blue phosphorene MOSFETs show superior performances with ultrashort-channel length. We first predict the ultrascaled ML blue phosphorene MOSFETs with proper doping concentration and underlap structures are compliant with the high-performance (HP) and low-power (LP) requirements of the International Technology Roadmap for Semiconductors in the next decade in the aspects of the on-state current, delay time, and power dissipation. Encouragingly, the performances of the ML blue phosphorene MOSFETs are superior to that of the MOSFETs based on arsenene, antimonene, InSe, etc. in terms of the on-state current at similar device size. We also consider the electron-phonon scattering in 10.2 nm gate ML blue phosphorene MOSFET. It is found that the on-state current with the scattering of the blue phosphorene device is degraded by 25.4 and 23.6% for HP and LP applications, which can also fulfill the HP and LP application target. Therefore, we can deduce that ML blue phosphorene is an alternative channel material to silicon for ultrascaled FETs if the large-scale and high-quality blue phosphorene can be achieved.

Ultra compact electrochemical metallization cells offering reproducible atomic scale memristive switching

Here we show electrochemical metallization cells with compact dimensions, excellent electrical performance, and reproducible characteristics. An advanced technology platform has been developed to obtain Ag/SiO2/Pt devices with ultra-scaled footprints (15 × 15 nm2), inter-electrode distances down to 1 nm, and a transition from the OFF to ON resistance state relying on the relocation of only few atoms. This technology permits a well-controlled metallic filament formation in a highly confined field at the apex of an atomic scale tip. As a consequence of this miniaturization process, we achieve set voltages around 100 mV, ultra-fast switching times of 7.5 ns, and write energies of 18 fJ. Furthermore, we demonstrate very good cell-to-cell uniformity and a resistance extinction ratio as high as 6 · 105. Combined ab-initio quantum transport simulations and experiments suggest that the manufactured structures exhibit reduced self-heating effects due to their lower dimensions, making them very promising candidates as next-generation (non-)volatile memory components.

Unusual Fermi‐Level Pinning and Ohmic Contact at Monolayer Bi2O2Se–Metal Interface

AbstractVery recently, high‐mobility and air‐stable 2D semiconductor Bi2O2Se has been discovered and believed to be a promising channel candidate for the next‐generation field‐effect transistor (FET). High‐performance few‐layer Bi2O2Se FETs have been realized due to the existence of ohmic contact between few‐layer Bi2O2Se and the metal electrodes. However, monolayer (ML) Bi2O2Se FET exhibits poor device performance owing to lack of good contact between ML Bi2O2Se and the metal electrode. This work simulates the ML Bi2O2Se Schottky barrier field‐effect transistors with a sequence of common electrodes (Au, Pd, Pt, Ag, Sc, and Ti) for the first time by using ab initio quantum transport simulations. For Ag, Au, and Pd electrodes, a lateral n‐type Schottky contact is formed with similar Schottky barrier heights of 0.43–0.52 eV due to a strong usual Fermi‐level pinning (FLP) to the band gap of ML Bi2O2Se. Remarkably, Pt, Sc, and Ti electrodes lead to a desirable lateral n‐type ohmic contact because of an unusual FLP above the ML Bi2O2Se conduction band as a result of electrode work function modification at the interface. Therefore, high performance is anticipated for ML Bi2O2Se devices with these low‐resistance ohmic contacts.

Sub 10 nm Bilayer Bi2O2Se Transistors

AbstractDue to high carrier mobility and excellent air stability, emerging 2D semiconducting Bi2O2Se is attracting much attention as a potential channel candidate for the next‐generation field effect transistor (FETs). Although the fabricated bilayer (BL) and few layers Bi2O2Se FETs exhibit a large current on/off ratio (>106) and a near‐ideal subthreshold swing value (≈65 mV dec−1), the performance limit of ultrashort channel Bi2O2Se FET is obscure. Here the ballistic performance upper limit of the sub 10 nm BL Bi2O2Se metal‐oxide‐semiconductor FETs (MOSFETs) is simulated for the first time by using ab initio quantum transport simulations. The optimized BL Bi2O2Se n‐type MOSFETs can fulfill the high performance device requirements on the on‐state current, delay time, and power dissipation of the International Technology Roadmap for Semiconductors in 2028 until the gate length is scaled down to 5 nm. Therefore, Moore's law can be extended to 5 nm by taking BL Bi2O2Se as the channel.

Sub-10 nm tunneling field-effect transistors based on monolayer group IV mono-chalcogenides.

The development of air-stable channels with a high on-state current (Ion) is in high demand for the feasible application of TFETs. Monolayer group IV mono-chalcogenides (i.e., GeS, GeSe, SnS, and SnSe), as emerging air-stable atomic-thin semiconductors, are potential channels for sub-10 nm tunneling field-effect transistors due to their high carrier mobility and anisotropic electronic properties. Herein, we investigated the performances of sub-10 nm monolayer (ML) group IV mono-chalcogenide TFETs using ab initio quantum transport simulation. The ML GeSe TFET exhibited the best performance with regards to both high Ion and low leakage current (Ileak) among the four devices, followed by the ML SnSe TFET with a high Ion. The Ion of the optimal ML GeSe TFET with a physical gate length of Lg = 10 nm surpasses the International Technology Roadmap for Semiconductors (ITRS, 2013 Edition) requirements for high-performance (HP) and low-power (LP) devices, simultaneously, and that of the ML SnSe TFET with Lg = 10 nm surpasses the requirement of ITRS HP devices. In combination with our former works, we suggest an Eg of 0.77-1.19 eV and of 0.11-0.15m0 to search for competitive 2D channels with a high Ion for HP application in TFET devices with a planar homogeneous p-i-n architecture.

Electrical contacts and tunable rectifications in monolayer GeSe-metal junctions

Two-dimensional (2D) semiconductors present great potential for electronic and optoelectronic applications due to their uniform thickness and tunable band gaps. Using ab initio electronic structure calculations and quantum transport simulations, we demonstrate the asymmetric metal contact design in the case of 2D GeSe, with a systematic study of the interfacial properties and transport properties of three common metal contacts (Ag, Au, and Pd) to the 2D semiconductor. Because of the different work functions, Ag contacted to GeSe forms n-type Schottky contact, while Pd forms p-type Schottky contact, respectively, and the reversed rectifying behaviors can be found in the I–V characteristics of symmetric contacted Ag–GeSe–Ag and Pd–GeSe–Pd junctions. More importantly, rectifying behaviors in both junctions can be significantly enhanced by the design of asymmetric metal contact (with the right-side electrode being replaced by Au). Our results are very helpful for the further design of the transistors based on 2D GeSe.

Sub-5 nm Monolayer Arsenene and Antimonene Transistors

Novel two-dimensional (2D) semiconductors arsenene and antimonene are promising channel materials for next-generation field effect transistors (FETs) because of the high carrier mobility and stability under ambient conditions. Stimulated by the recent experimental development of sub-5 nm 2D MoS2 FETs, we investigate the device performance of monolayer (ML) arsenene and antimonene in the sub-5 nm region by using accurate ab initio quantum transport simulation. We reveal that the optimized sub-5 nm double-gate (DG) ML arsenene and antimonene metal-oxide-semiconductor FETs (MOSFETs) can fulfill the low power requirements of the International Technology Roadmap for Semiconductors in 2028 until the gate length is scaled down to 4 nm. When the gate length is scaled down to 1 nm, the performances of the DG ML arsenene and antimonene MOSFETs are superior to that of the DG ML MoS2 MOSFETs in terms of the on-current. Therefore, 2D arsenene and antimonene are probably more suitable for ultrascaled FETs than 2D MoS2 in the post-silicon era.

Ohmic contacts between monolayer WSe2 and two-dimensional titanium carbides

Formation of Ohmic contact is crucial for achieving high device performance in two-dimensional (2D) materials based transistors. By using ab initio electronic structure calculations and quantum transport simulations, we reveal the great potential of 2D titanium carbides as the electrode materials for monolayer (ML) WSe2 device. In the vertical direction, both tunnel barrier and Schottky barrier are absent in all the three hybrid heterostructures of ML WSe2/Ti2C and ML WSe2/Ti2CY2 (Y = F and OH), implying a high vertical carrier injection efficiency. In the lateral direction, although pristine Ti2C and ML WSe2 form a Schottky contact with electron barrier of 0.40 eV, Ti2CF2/ML WSe2 and Ti2C(OH)2/ML WSe2 form p-type quasi-Ohmic and n-type Ohmic contacts, respectively. Therefore, 2D titanium carbides can be promising candidates as electrode materials for the ML WSe2 transistors by proper controlling of the surface functional group.

Atomic defects in monolayer WSe2 tunneling FETs studied by systematic ab initio calculations

Atomic defects in monolayer WSe2 tunneling FETs (TFETs) are studied through systematic ab initio calculations aiming at performance predictions and enhancements. The effects of various defect positions and different passivation atoms are characterized in WSe2 TFETs by rigorous ab initio quantum transport simulations. It is suggested that the Se vacancy (VSe) defect located in the gate-controlled channel region tends to increase the OFF current (Ioff), whereas it can be well suppressed by oxygen passivation. It is demonstrated that chlorine (Cl) passivation at the source-side tunneling region can largely suppress Ioff, leading to an impressively improved on–off ratio (Ion/Ioff) compared with that without any defect. However, it is also observed that randomly positioned atomic defects tend to induce significant fluctuation of the TFET output. Further discussions are made with focus on the performance-variability trade-off for robust circuit design.