6T Bitcell Research Articles

Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate

The failure probabilities of industrial SRAM cells fall below the ppm (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−6</sup> ) range, disqualifying the computational-intensive Monte-Carlo simulations for efficient robustness assessment. Starting from a novel two-dimensional threshold voltage imbalance representation, we propose a new methodology for fast and accurate prediction of the subthreshold SRAM hold stability failure rate. The probability is derived in a closed form which involves the transistor threshold-voltage standard deviations and only requires the two quick DC extractions of the worst- and best-case static noise margins. We validate our approach on a Six-Transistor (6T) bitcell in 28 nm Fully Depleted Silicon-On-Insulator (FD-SOI) CMOS technology. Our method turns out to be especially insightful for comparative and sensitivity analyses, for instance to study the effect of supply voltage downscaling or temperature variations. Finally, we show that the achieved accuracy and the capability of estimating extremely low failure probabilities (down to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−9</sup> ), combined with the important gain in simulation and post-processing cost, makes our methodology attractive compared to other recent modelling works.

A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM

This paper presents a half-selected robust 12T bitcell with built-in write-assist for sub-threshold SRAM. The proposed 12T bitcell is robust enough in bit-interleaving architecture to enhance soft-error immunity combined with error correction code. The read stability of the proposed bitcell is improved by read decoupled. The writability is improved by data-dependent supply-cutoff write-assist. Both row and column f-selected bitcells can hold data stably during write operations. Simulation results based on a standard 55nm CMOS technology show that the read static noise margin of the proposed bitcell is 16.13x as that of the conventional 6T bitcell. Moreover, the write failure in the sub-threshold region is eliminated. In addition, the leakage consumption is improved by 15.7% compared with 6T bitcell.

SRAM-Based PUF Reliability Prediction Using Cell-Imbalance Characterization in the State Space Diagram

This work proposes a methodology to estimate the statistical distribution of the probability that a 6T bit-cell starts up to a given logic value in SRAM memories for PUF applications. First, the distribution is obtained experimentally in a 65-nm CMOS device. As this distribution cannot be reproduced by electrical simulation, we explore the use of an alternative parameter defined as the distance between the origin and the separatrix in the bit-cell state space to quantify the mismatch of the cell. The resulting distribution of this parameter obtained from Monte Carlo simulations is then related to the start-up probability distribution using a two-component logistic function. The reported results show that the proposed imbalance factor is a good predictor for PUF-related reliability estimation with the advantage that can be applied at the early design stages.

A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS

In this work, we present a compute-in-memory (CIM) macro built around a standard two-port compiler macro using foundry 8T bit-cell in 7-nm FinFET technology. The proposed design supports 1024 4 b × 4 b multiply-and-accumulate (MAC) computations simultaneously. The 4-bit input is represented by the number of read word-line (RWL) pulses, while the 4-bit weight is realized by charge sharing among binary-weighted computation caps. Each unit of computation cap is formed by the inherent cap of the sense amplifier (SA) inside the 4-bit Flash ADC, which saves area and minimizes kick-back effect. Access time is 5.5 ns with 0.8-V power supply at room temperature. The proposed design achieves energy efficiency of 351 TOPS/W and throughput of 372.4 GOPS. Implications of our design from neural network implementation and accuracy perspectives are also discussed.

Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment

We present experimental results of the cross-section related to cosmic-ray irradiation at ground level for minimum-sized six-transistor (6T) and eight-transistor (8T) bit-cells SRAM memories implemented on a 65 nm CMOS standard technology. Results were obtained from accelerated irradiation tests performed in the mixed-field irradiation facility of the CERN High-energy Accelerator test facility (CHARM) at the European Organization for Nuclear Research in Geneva, Switzerland. A 1.45× higher SEU cross-section was observed for 6T-cell designs despite the larger area occupied by the 8T cells (1.5× for MCU). Moreover, the trend for events affecting multiple bits was higher in 6T-cells. The cross-section obtained values show that the memories have enough sensitivity to be used as a radiation monitors in high energy physics experiments.

Characterization of single-ended 9T SRAM cell

We present a circuit-level technique of designing a lower write-power along with variability-resistant 9-MOFTET static random-access memory cell. Our proposed bitcell exhibits lower write-power consumption owing to reduction of activity factor and breakup of feedback path between the cross-coupled inverters during write operation. It exhibits higher read static noise margin (by 3.09 ×) compared with standard 6T SRAM cell @ minimum-area. LP9T shows higher static margin for write operation (by 41%) compared with 8T (S6T) @ iso-area (minimum-area). These improvements are achieved due to breakup of feedback path during the process of writing a bit on to the storage node. The paper investigates in detail the influence of variation in process related parameters, environmental parameters such as supply voltage and temperature on most of the important design parameters of the bitcell and compares the obtained simulation results with conventional 6-MOSFET (6T) and 8-MOSFET (8T) bitcells. It demonstrates its invariableness by showing 1.5 × tighter disperse in read time variability with a cost of 1.41 × higher read time compared with S6T @ minimum-area. It also exhibits 39% narrower disperse in read time variability in comparison to 8T @ iso-area. It draws lower power (2.06 ×) from supply voltage while flipping of stored data during write mode compared with standard 8T SRAM cell @ iso-area. It also compares key design metrics of LP9T with those of few other 9T SRAM cells found in the literature. This work also realizes the proposed design using CNFET. The CNFET-based design outperforms its CMOS counterpart in all respect.

Single bit‐line 8T SRAM cell with asynchronous dual word‐line control for bit‐interleaved ultra‐low voltage operation

This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal–oxide–semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.

Characterization of a novel 10T SRAM cell with improved data stability and delay performance for 20-nm tri-gated FinFET technology

PurposeThis paper aims to propose a new ten-transistor (10T) SRAM bit-cell with differential read and write operations. The cell structure has read buffer on each side of the cell to improve read performance and comprises six main body transistors’ connections similar to the commercial 6T SRAM cell to improve write performance. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on a silicon-on-insulator (SOI) substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell. The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher read static noise margin (RSNM) as compared with that of 8T and 6T bit-cells, respectively, at a VDD of 0.9 V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit- cell. The overall electrical quality of the SRAM circuit with the proposed bit-cell is enhanced up to 1.673 times and 1.22 times as compared with the 8T SRAM-NEW and 6T bit-cells, respectively.Design/methodology/approachA new 10T SRAM bit-cell with differential read and write operations is proposed. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on an SOI substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell.FindingsThe proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher RSNM as compared with that of the 8T and 6T bit-cells, respectively, at a VDD of 0.9V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with the 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit-cell.Originality/valueThe proposed bit-cell is novel compared with existing bit-cells.

A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array

A multi-functional in-memory inference processor integrated circuit (IC) in a 65-nm CMOS process is presented. The prototype employs a deep in-memory architecture (DIMA), which enhances both energy efficiency and throughput over conventional digital architectures via simultaneous access of multiple rows of a standard 6T bitcell array (BCA) per precharge, and embedding column pitch-matched low-swing analog processing at the BCA periphery. In doing so, DIMA exploits the synergy between the dataflow of machine learning (ML) algorithms and the SRAM architecture to reduce the dominant energy cost due to data movement. The prototype IC incorporates a 16-kB SRAM array and supports four commonly used ML algorithms—the support vector machine, template matching, $k$ -nearest neighbor, and the matched filter. Silicon measured results demonstrate simultaneous gains (dot product mode) in energy efficiency of 10 $\times $ and in throughput of 5.3 $\times $ leading to a 53 $\times $ reduction in the energy-delay product with negligible ( $\le $ 1%) degradation in the decision-making accuracy, compared with the conventional 8-b fixed-point single-function digital implementations.

A near-threshold 10T differential SRAM cell with high read and write margins for tri-gated FinFET technology

In this paper, a new 10T SRAM bit-cell working in the near-threshold region with differential read and write operations is proposed. The cell structure comprises six main body transistors having connections similar to commercial 6T SRAM cell to improve write performance and has a separate read buffer on each side of cell to improve read performance. Efficacy of the proposed bit-cell is tested in 20nm tri-gated FinFET technology with the help of HSPICE simulations in near-VT and super-VT operating regions. Performance characteristics of the proposed bit-cell are compared with other recently reported 10T and 8T differential sensing bit-cells, along with the commercial 6T cell. The proposed bit-cell achieves 6.57%, 33.33% and 51.64% higher RSNM as compared to 10T P-P-N, 8T SRAM-NEW and 6T bit-cells, respectively, in near-VT operating region. The read delay, write delay and static power consumption of the proposed bit-cell are comparable with that of 6T bit-cell in both operating regions. The overall electrical quality of SRAM circuit with the proposed bit cell is enhanced up to 8.192, 1.13 and 2.39 times compared to that of the 10T P-P-N, 8T SRAM-NEW and 6T bit-cells, respectively, in near-VT operating region. The proposed bit-cell can operate with a 38.8%, 30% and 5.54% lower VDD as compared with 6T, 8T SRAM-NEW and 10T P-P-N bit-cells, respectively, under equal read data stability conditions. Influence of process variation on bit-cell stability is studied through 10,000 Monte Carlo simulations. The study shows that the proposed bit-cell meets the required six sigma value (6σ) for all operations even at VDD =0.5V. Variations in the bit-cell performance metrics for temperature rise from −40°C to 100°C are also studied.

Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation

Conventional static random access memory (SRAM) suffers from high leakage power when implemented in advanced CMOS nodes, while modified bitcells or assist techniques are required to achieve robust low-voltage operation. Gain-cell eDRAM (GC-eDRAM) is an interesting area-efficient alternative to SRAM, but requires refresh cycles and typically a boosted write word-line (WWL). This brief proposes a hybrid GC-eDRAM/SRAM bitcell addressing the leakage power and low voltage robustness issues of SRAM, while avoiding bandwidth-consuming refresh and WWL boost of conventional GC-eDRAM. In the hybrid 8T bitcell, an SRAM keeper latch is connected to the storage node (SN) of a gain cell. The SRAM keepers are power gated most of the time for leakage reduction; the keepers are powered on only during zero bandwidth consuming refresh cycles, after write, and before read, to ensure strong data levels on the SN. Compared to a conventional 6T SRAM bitcell, the hybrid 8T bitcell has a 2T read port and an interruptible keeper for both robust read and write at low voltages. Simulations in 65-nm CMOS show that the hybrid bitcell enables 35% (at 400 mV) to 55% (at 1 V) lower data retention power than an 6T SRAM cell at 25 °C.

Device-Circuit Cosimulation for Energy Efficiency in Sub-10-nm Gate Length Logic and Memory

Sub-10-nm gate length devices are expected to have severe short channel effects along with new leakage mechanisms, such as direct source-to-drain tunneling (DSDT). In this paper, in order to improve the leakage and to obtain the highest performance/stability in such deeply scaled devices, we perform device–circuit cosimulation for sub-10-nm gate length to optimize devices for logic and memory. For that purpose, double-gate MOSFETs with sub-10-nm gate length are optimized using symmetric/asymmetric gate-to-source/drain underlaps to improve the ON-state current to the OFF-state current ratio and the intrinsic gate delay. Using resulting device characteristics, the effectiveness of supply gating to improve standby leakage in the circuits is studied. We show that supply gating is effective in reducing DSDT current, as well as thermionic leakage current. Also, various SRAM designs are explored to improve stability and leakage in sub-10-nm gate length bit-cells. The analysis shows that 6T SRAM bit-cells with asymmetrically underlapped devices can provide improvement in read stability over symmetric 6T bit-cells, as well as traditional 6T bit-cells. However, the need for higher stability in the sub-10-nm gate length regime due to parameter variation would require us to investigate other bit-cell configurations. Our analysis on 1R/1W differential 8T SRAM bit-cells show that significant increase in read/write stability as well as improvement in write time, and leakage can be achieved compared with the optimized 6T SRAM bit-cells.

Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology

In this paper, a new layout for SRAM 6T bitcell is presented. The new layout is a simple modification over the traditional 6T layout, but it has demonstrated better soft error tolerance over the traditional layout in radiation experiments. The area of the new layout is 31 % larger than the traditional layout. In TCAD simulation, it demonstrates over 2? smaller error cross section than the traditional layout. In alpha particle and proton experiments, its soft error rate can be reduced up to 73 % compared to the traditional layout.

A 128 Kbit SRAM With an Embedded Energy Monitoring Circuit and Sense-Amplifier Offset Compensation Using Body Biasing

Embedded SRAMs are continuing to be one of the most critical components that limit the performance and energy budget of today's systems. To enable better system level optimization, this paper introduces an embedded energy monitoring circuit that measures the absolute energy consumption of a 128 kbit SRAM circuit that is fabricated using a 65 nm low-power CMOS process. Monitoring circuit results are measured to be accurate within 10% of the actual energy consumption and it works with minimal overhead (below 1% active power). Secondly, to achieve energy-efficient and high-performance SRAM operation, various circuit techniques are employed. 8T bit-cells with word-line voltage boosting is used to enable operation for a wide supply range from 370 mV to 1.2 V. Since variation effects are more prominent at low-voltages, SRAM performance is improved by using a two stage sensing scheme. Global sensing is performed by offset compensated sense amplifiers that leverage body biasing to achieve up to 2x offset reduction for only 3.5% area overhead compared to SRAM area.

Novel 8T Bit-cell with High RSNM for Sub-threshold SRAM

Since the sub-threshold circuit technology was widely applied to SRAM circuit, the power supply voltage was greatly reduced, and then, the performance of environmental parameters and process deviations on sub-threshold circuit become critical. The changes in environmental parameters and process deviations easily make traditional 6T SRAM circuit lead to fatal errors, particularly, the Read Static Noise Margin (RSNM) is deteriorated obviously. In order to improve the performance of RSNM, we proposed a novel 8T SRAM bit-cell which uses the read and write separation structure and Partial Dynamic Threshold voltage (PDT) technology. This paper firstly introduces the PDT technology and read and write separation structure; then proposes the novel 8T structure and explains the operating principle of the 8T bit-cell; finally gives the result of the simulation for the stability performance of the 8T bit-cell compare to other 3 kinds of 6T bit-cell. The comparison results show that the proposed 8T bit-cell greatly improves the RSNM of the SRAM bit-cell.

An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications

Energy consumption is a key issue in portable biomedical devices that require uninterrupted biomedical data processing. As the battery life is critical for the user, these devices impose stringent energy constraints on SRAMs and other system on chip (SoC) components. Prior work shows that operating CMOS circuits at subthreshold supply voltages minimizes energy per operation. However, at subthreshold voltages, SRAM bitcells are sensitive to device variations, and conventional 6T SRAM bitcell is highly vulnerable to readability related errors in subthreshold operation due to lower read static noise margin (RSNM) and half-select issue problems. There are many robust subthreshold bitcells proposed in the literature that have some improvements in RSNM, write static noise margin (WSNM), leakage current, dynamic energy, and other metrics. In this paper, we compare our proposed bitcell with the state of the art subthreshold bitcells across various SRAM design knobs and show their trade-offs in a column mux scenario from the energy and delay metrics and the energy per operation metric standpoint. Our 9T half-select-free subthreshold bitcell has 2.05× lower mean read energy, 1.12× lower mean write energy, and 1.28× lower mean leakage current than conventional 8T bitcells at the TT_0.4V_27C corner. Our bitcell also supports the bitline interleaving technique that can cope with soft errors.

Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability

In this work, we proposed a single-ended read disturb-free 9T SRAM cell for bit-interleaving application. A column-aware feedback-cutoff write scheme is employed in the cell to achieve higher write margin and non-intrusive bit-interleaving configuration. And a dynamic read-decoupled assist scheme is utilized by cutting loop to relax the interdependence between stability and read current, resulting in robust read operation and better read performance simultaneously. Moreover, the lower write and leakage energy consumptions are also achieved. We compared area, stability, SNM sensitivity and energy consumption between proposed 9T and standard 6T bit-cells. The write ability of 9T cell is 1.40× higher that of 6T cell at 1.0V, and 8.16× higher at 0.3V. The write and leakage energy dissipations are 26% and 13% lower than that of 6T at 1.0V. In addition, robust read and better process variation tolerance are provided for proposed design with area penalty.

Effect of Supply Voltage on Ability and Stability in IP3 SRAM Bit-Cell at 45nm CMOS Technology using N-Curve

The Leakage power, performance, data retentation, and stability are the key challenges in Static Random Access Memory (SRAM) at Deep-Sub-Micron (DSM) CMOS technology. In the DSM technology, when threshold voltage, channel length, and gate oxide thickness are reduced, leakage currents in deep sub-micrometer regimes causes power dissipation in CMOS digital circuits which may affect the data ability and stability in the SRAM. In this work the effect of supply voltage has been observed in the IP3 SRAM Bit-Cell using N-Curve methodology at the room temperature (RT). To see the effect of supply voltage variations on the stability and ability parameters in the 6T and IP3 SRAM Bit-Cells, the supply voltage has been varied from 0.6V to 1.0V in step of 0.1V. It has been seen that the read, write stability and ability are comparable in both cells at RT. The other design parameters taken from the CMOS technology available on 45nm are as tOX = 2.4 nm, Vthn = 0.224 V, and Vthp = 0.24 V at RT = 27°C.

Single-ended, robust 8T SRAM cell for low-voltage operation

Recently, an SRAM has been in the development stage, with its objective to withstand the ever-increasing process variations as well as to support ultra-low power applications, even at subthreshold supply voltages. In this paper, a new 8T SRAM cell, which employs a single bitline scheme to perform the write and read operations, is proposed. This scheme enhances the write ability and read stability by cutting off the feedback loop of the inverter pair, thereby eliminating the read and write constraints on the transistor dimensions. Additionally, it efficiently trims down the write power and standby power consumption. The experimental results show that the proposed 8T cell achieves 4.66× write ability, 2.33× read noise margin, 28.0% write power reduction, and 3.3× lower standby power dissipation when compared with a 6T bit-cell at 0.5V through a Monte Carlo simulation (10,000 times) using the TSMC 65-nm process. Moreover, it also achieves higher process variation tolerance at an ultralow operating voltage.

Implementation of an Efficient SRAM for Ultra-Low Voltage Application Based on ST for Better Read Stability and Write Ability

Operation of standard 6T static random access memory (SRAM) cells at sub or near threshold voltages is unfeasible, predominantly due to degraded static noise margins (SNM) and poor robustness. We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better read- stability as well as better write-ability compared to the standard 6T bitcell. In this paper we are going to propose a new SRAM bitcell for the purpose of read stability and write ability by using 90nm technology , and less power consumption, less area than the existing Schmitt trigger1 based SRAM. Design and simulations were done using DSCH and Microwind. Index Terms: read stability, write ability, Schmitt trigger. I. Introduction PORTABLE electronic devices have extremely low power requirement to maximize the battery lifetime. Various device-/circuit-architectural-level techniques have been implemented to minimize the power consumption. Supply voltage scaling has significant impact on the overall power dissipation.With the supply voltage reduction, the dynamic power reduces quadratically while the leakage power reduces linearly (to the first order). However, as the supply voltage is reduced, the sensitivity of circuit parameters to process variations increases. This limits the circuit operation in the low-voltage regime, particularly for SRAM bitcells employing Minimum-sizedtransistor. These minimum geometry transistors are vulnerable to interdie as well as intradie process variations. Intradie process variations include random dopant fluctuation (RDF) and line edge roughness (LER). This may result in the threshold voltage mismatch between the adjacent transistors in a memory bitcell, resulting in asymmetrical characteristics. The combined effect of the lower supply voltage along with the increased process variations may lead to and increased memory failures such as read-failure, hold-failure, write- failure, access-time failure. Moreover, it is predicted that embedded cache memories, which are expected to occupy a significant portion of the total die area, will be more prone to failures with scaling.