4H-SiC Interface Research Articles

Exploring the border traps near the valence band in the SiO2 - SiC system using above-band-gap optical excitation

Studying near-valence-band (EV) defects at the insulator–n-type 4H-SiC interface is challenging due to the low minority carrier concentration. Herein, we present a technique for characterizing the border traps near EV in an n-type 4H-SiC MOS capacitor by generating holes using above-band-gap optical excitation (OE). A rise in capacitance was observed under OE (due to hole capture by border traps), remaining stable long after the optical stimulus was removed, resulting in a persistent photocapacitance effect. We show the dynamics of the capture process and perform a quantification of the captured holes in samples with thermally grown oxide and different postoxidation annealing treatments. Published by the American Physical Society 2024

High voltage response of graphene/4H-SiC UV photodetector with low level detection

A self-powered graphene/silicon carbide (G/4H-SiC) ultraviolet photodetector of a p-i-n like-structure with high voltage response has been fabricated to detect and measure low intensity ultraviolet (UV) radiation. Bilayer graphene sheet grown by chemical vapor deposition (CVD) method was transferred on the top of an epilayer structure of n-/n+ 4 H-SiC. In this structure, two Schottky contacts were formed: one at G/ n- 4H-SiC interface and the other at bulk-4 H-SiC/Cr/Au interface. The photodetector's characteristic measurements revealed low dark current of ∼ 0.58 nA and spectral voltage responsivity of ∼ 0.75 V/W at 300 nm wavelength. Under low level UV illumination of 300 nm wavelength, the photodetector exhibited a leakage current and a photogenerated response voltage of 1.1 nA and 10 mV, respectively. The time-dependent photovoltage measurements displayed a rapid photovoltage response with rise and decay times of ∼74 ns and ∼ 580 ns, respectively. This novel device holds promise for applications requiring sensitive and self-powered UV detection.

Nucleation of Threading Dislocations in 4H-SiC at Early Physical-Vapor-Transport Growth Stage

In this work, we identify the nucleation mechanism of threading dislocations (TDs) associated with stacking faults (SFs) and 15R-SiC at the early growth stage of 4H-SiC single crystals grown by the physical vapor transport (PVT) technology. By combining molten KOH etching and photochemical etching, we successfully reveal etch pits of TDs and linear etch patterns of SFs on the (112̅0) surface of 4H-SiC single crystals. Systematic investigations based on transmission electron microscopy (TEM) observations and Raman analysis indicate that the Si–C bilayer stacking sequence of SFs is (3, 2) in Zhdanov’s notation. The accumulation of SFs (3, 2) gives rise to the polymorph fluctuation and thus the formation of 15R-SiC at the early PVT growth stage of 4H-SiC single crystals. Quantitative stress analyses indicate that the strain field distributions along the SFs (3, 2) and the 15R-/4H-SiC interfaces are inhomogeneous, which give rise to the nucleation of TDs and low-angle grain boundaries (LAGBs), respectively. The nucleation of LAGBs releases the high stress at the 15R-/4H-SiC interface, which facilities the following 4H-SiC single-crystal growth. Our work indicates that the avoidance of polymorph fluctuation is important to the reduction of TDs at the early growth stage of PVT-grown 4H-SiC single crystals.

Study of the Bonding Characteristics at β-Ga2O3(201)/4H-SiC(0001) Interfaces from First Principles and Experiment

For the first time, β-Ga2O3 were prepared on 4H-SiC (0001) substrates using a low-pressure chemical vapor deposition (LPCVD) technique. The obtained β-Ga2O3/4H-SiC heterostructures display strongly preferential growth orientation along the <201> of β-Ga2O3. Combining the experimental results, interfacial properties, such as the work of adhesion (Wad), electronic properties and bonding characteristics of β-Ga2O3(201)/4H-SiC(0001) heterointerface were systemically studied using first principles. Four different β-Ga2O3(201)/4H-SiC(0001) interface models composed of different atom stacking sequences were established. It was found that the interface consisting of silicon terminated of 4H-SiC (0001), and oxygen terminated of β-Ga2O3(201) (Si-O) has the lowest relaxation energy and the highest stability. Results indicated that the binding of interface Si and C to the O atoms is stronger than that to the Ga atoms. The results of the difference charge density and electron localization function reveals that the Si and C atoms at interface are bonded with O atoms of β-Ga2O3 by covalent bonds, in which Si-O and C-O covalent bonds play a favorable role in the final stable configurations formation. This work will provide a further understanding of the various electronic behaviors of the β-Ga2O3(201)/4H-SiC(0001) heterointerface.

Investigation of the interface electronic characteristics of β-Ga2O3 (1 0 0)/4H-SiC (0 0 0 1)

Due to lower thermal conductivity of β-Ga2O3, gallium oxide power device based on high thermal conductivity substrates has received extensive attention. As a high thermal conductivity semiconductor material, 4H-SiC is suitable as a substrate to combine with β-Ga2O3 due to its small lattice mismatches. Herein, first principle is utilized to analyze the interfacial geometry structures, formation energy, interface binding energy and the electronic properties of the bonding mechanism at different β-Ga2O3 (100)/4H-SiC (0001) interfacial models. The interface formation energy and interface binding energy of β-Ga2O3 (100)/4H-SiC (0001) heterointerfaces are studied by using first principles. The results show that six different β-Ga2O3 (100)/4H-SiC (0001) heterostructures can be stable. Among the six interface models, Si-O interface possesses the smallest values of interface formation energy and interface binding energy after geometry relaxation, indicating highest thermodynamic stability. The differential charge density, bader charge, electron local function and partial density of states (PDOS) of β-Ga2O3 (100)/4H-SiC (0001) interface models are comprehensively investigated to understand the interfacial bonding strength and stability. It is shown that electrons are mainly transferred from the 4H-SiC side to the β-Ga2O3 side. Compared to other interface models, Si-O models, Si-GaO models can form strong Si-O chemical bond at the interface, while the interaction between the C-O models and C-GaO models forms a C-O bond with covalent bond properties.

Reliable evaluation method for interface state density and effective channel mobility in lateral 4H-SiC MOSFETs

The electrical performance of silicon carbide metal-oxide-semiconductor field effect transistors (4H-SiC MOSFETs) are strongly related to the presence of interface states at the silicon dioxide (SiO2)/4H-SiC interface, whose density is much higher than in the Si/SiO2 system. In particular, the charged interface states determine a degradation of the carrier mobility in the channel of the MOSFET with respect to the bulk mobility. A reliable and consistent method for the evaluation of the interface state density (D it) and the effective channel mobility (μ ch) in these devices is presented in this work. The two quantities are simultaneously extracted by a combined fit of the current–voltage (I–V) and capacitance–voltage (C–V) electrical characteristics collected on a single device. The simultaneous fit of the I–V and C–V characteristics, which can be easily measured on the same device, noticeably improve the reliability of D it and μ ch estimation. The results obtained at different temperatures indicate an increase of the μ ch with T, in agreement with a dominance of the Coulomb scattering effect as the degradation mechanism of the carrier channel mobility induced by the presence of charged interface states.

Low-temperature formation of Mg/n-type 4H-SiC ohmic contacts with atomically flat interface by lowering of Schottky barrier height

To obtain an ohmic contact with a flat interface using a low-temperature process, we investigated the behavior of Schottky barrier height (SBH) at the Mg/n-type 4H-SiC interface to low-temperature annealing. Our results revealed that annealing at 200 °C reduced SBH; a low SBH of 0.28 eV was obtained on the lightly doped substrate. Atomic force microscopy measurements revealed negligible increase in the surface roughness after Mg deposition and annealing. Using the low-temperature process, a contact resistivity of 6.5 × 10−5 Ω·cm2 was obtained on the heavily doped substrate, which is comparable to Ni/4H-SiC subjected to annealing of above 950 °C.

Ab initio -based approach for the oxidation mechanisms at SiO2 /4H-SiC interface: Interplay of dry and wet oxidants during interfacial reaction

Effects of the coexistence of dry and wet oxidants on the reaction process at ${\mathrm{SiO}}_{2}$/4H-SiC(0001) and ($000\overline{1}$) interfaces during SiC oxidation are systematically investigated by performing ab initio calculations. We find characteristic features of the interfacial reaction mechanisms, which are dependent on the plane orientation and wet oxidation condition. The incorporation of wet oxidants leads to lower barrier heights for the reaction of ${\mathrm{O}}_{2}$ molecules, resulting in the promotion of interfacial reaction at the ${\mathrm{SiO}}_{2}$/4H-SiC(0001) interface. In contrast, the coexisting ${\mathrm{O}}_{2}$ molecule assists the reactions by ${\mathrm{H}}_{2}\mathrm{O}$ molecule and OH groups at the ${\mathrm{SiO}}_{2}$/4H-SiC($000\overline{1}$) interface. Furthermore, we estimate the linear rate constants in the Deal-Grove model using the calculated barrier heights and reveal that the preferable wet ambient condition at the ${\mathrm{SiO}}_{2}$/4H-SiC(0001) interface is different from that at the ${\mathrm{SiO}}_{2}$/4H-SiC($000\overline{1}$) interface. The difference in the rate constants is caused by the difference in the rate-limiting reaction pathway between ${\mathrm{SiO}}_{2}$/4H-SiC(0001) and ($000\overline{1}$) interfaces. These calculated results offer better understanding of the atom-scale mechanisms for the significant enhancement of SiC oxidation by the interplay of dry and wet oxidants.

SiO<sub>2</sub>/4H-SiCにおける界面準位と界面構造の相関

SiO<sub>2</sub>/4H-SiCにおける界面準位と界面構造の相関

Lowering of the Schottky barrier height of metal/n-type 4H-SiC contacts using low-work-function metals with thin insulator insertion

We examined the lowering of the Schottky barrier height (SBH) of a metal/n-type 4H-silicon carbide (SiC) contact using low-work-function metals to realize an ohmic contact through a low-temperature process. We found that the SBHs of Y, Mg, and Hf/n-type 4H-SiC contacts deviated from the Schottky limit and that the SBH was greater than ∼0.5 eV at minimum. Inserting 0.3 and 0.7 nm thick SiN x layers into a Mg/n-type 4H-SiC interface could help effectively reduce the SBH; Mg/SiN x /n-type 4H-SiC exhibited an SBH as low as ∼0.36 eV. This reduction in the SBH could be attributed to the suppression of the metal-induced gap state manifested at the conduction band edge. Finally, through a quantitative analysis, it was demonstrated that the contact resistivity of a Mg/SiN x (0.3 nm)/4H-SiC interface could be reduced by approximately one order of magnitude compared with that of a Mg/4H-SiC interface at donor concentrations below ∼3 × 1019 cm−3.

Low-Energy Muons as a Tool for a Depth-Resolved Analysis of the SiO<sub>2</sub>/4H-SiC Interface

In this work, the potential of muon spin rotation (μSR) with low-energy muons (LE-μ) for the investigation of oxidation-induced defects at the SiO2/4H-SiC interface is explored. By using implantation energies for the muons in the keV range and comparing the fractions of muonium in different regions, the depth distribution of defects in the first 200 nm of the target material can be resolved. Defect profiles of interfaces with either deposited or thermally grown SiO2 layers on 4H-SiC are compared. The results show an increased number of defects in the case of a thermal oxide, both on the oxide and on the SiC side of the interface, with a spatial extension of a few tens of nm.

Gate Capacitance and Conductance-Voltage Characteristics of Vertical 4H-SiC MOSFETs

We have characterized gate capacitive and conductive behaviors of commercial Si and 4H-SiC vertical MOSFETs that have never been reported previously. The characteristics and possible physical reasons are determined and corroborated with device simulations. The measurements were carried out on different 1200V 4H-SiC MOSFETs from several vendors by impedance analyzer. Typical C-V characteristics of gate-controlled diodes are observed in those MOSFETs, while several conductance peaks are also captured in G-V measurements. These conductance peaks, reproduced with numerical simulations, are not necessarily related to the behavior of any interface states at the gate oxide/ 4H-SiC interface.

Tuning the high-κ oxide (HfO2, ZrO2)/4H-SiC interface properties with a SiO2 interlayer for power device applications

SiC based power devices are promising for the next generation energy-efficient power converters. But its device performance is always largely limited by the tradition thermal SiO2 gate dielectric. The high-κ dielectric gate oxides have been widely used in Si and III-V devices. However, high quality dielectric layer using high-κ oxide for SiC power device is still lacking sufficient theoretical investigation. In this paper, the properties of XO2/4H-SiC (X = Hf or Zr) interfaces with a SiO2 interlayer are systematically studied by density-functional supercell calculations. Reliable interface atomic structures without any gap states have been built according to the electron counting rule. Based on the models, the electronic structure of each interface is obtained by hybrid functional. The interfacial characteristics including the averaged potential and charge transfer analysis are calculated in detail. The calculated band edge line-ups are comparable with the experimental reports. In term of the band alignment, HfO2 and ZrO2 directly bonding to SiC are not suitable dielectric materials for SiC based power device, due to the relatively smaller conduction band offsets (CBO). While introducing the SiO2 interlayer can effectively tune the interface properties, especially the band alignment. With HfO2(ZrO2)/SiO2 stack as the dielectric layer for 4H-SiC, the interface has the large CBO (>1 eV) to efficaciously confine the channel carriers, indicating that the HfO2(ZrO2)/SiO2/4H-SiC stack is the promising strategy for SiC based power device applications.

Anomalous band alignment change of SiO2/4H–SiC (0001) and (000–1) MOS capacitors induced by NO-POA and its possible origin

For SiO2/4H–SiC (0001) and (000–1) n-type metal-oxide-semiconductor capacitors, the relationship between flatband voltage and the thickness of oxide was investigated after NO post-oxidation annealing to evaluate the expected flatband voltage (VFB) without a fixed charge effect. After removal of the fixed charge effect, there was an anomalous negative shift of VFB on (0001) 4H–SiC, which would be attributed to the result of dipole layer formation at the interface. The effects of the dipoles were investigated from the perspective of the SiO2/4H–SiC band alignment shift. We could find the correlation between the shift of VFB and that of the band alignment between SiO2 and the 4H–SiC interface; we concluded that stable Si–N bonds at the interface induce a dipole layer, and this is one of the reasons for the unexpected shift reported for VFB or threshold voltage of metal-oxide-semiconductor field-effect transistors, as well as the fixed charge effects. A significant difference in the band alignment on (0001) and (000–1) was also clarified, which would be one of the reasons for the disagreement of VFB on those faces.

SiO2/4H-SiC界面における界面準位と界面構造の相関

SiO2/4H-SiC界面における界面準位と界面構造の相関

Hysteresis effect in current–voltage characteristics of Ni/n-type 4H-SiC Schottky structure**Project supported by the National Natural Science Foundation of China (Grant Nos. 61804118, 61774117, and 61774119), the Fundamental Research Funds for the Central Universities, China (Grant Nos. 20101185935 and 20106186647), the National Key Basic Research Program of China (Grant No. 2015CB759600), the Shaanxi Key Research and Development Program, China (Grant No.

Hysteresis current–voltage (I–V) characteristics are often observed in a highly non-ideal (n > 2) as-deposited nickel (Ni)/4H-SiC Schottky contact. However, we find that this kind of hysteresis effect also exists in an as-deposited Ni/n-type 4H-SiC Schottky structure even if the ideality factor (n) is less than 1.2. The hysteresis I–V characteristics is studied in detail in this paper by using the various measurements including the hysteresis I–V, sequential I–V sweeping, cycle I–V, constant reverse voltage stress (CRVS). The results show that the hysteresis I–V characteristics are strongly dependent on the sweeping voltage and post-deposition annealing (PDA). The high temperature PDA (800 °C) can completely eliminate this hysteresis. Meanwhile, the magnitude of the hysteresis effect is shown to decrease in the sequential I–V sweeping measurement, which is attributed to the fact that the electrons tunnel from the 4H-SiC to the localized states at the Ni/n-type 4H-SiC interface. It is found that the application of the reverse bias stress has little effect on the emission of those trapped electrons. And a fraction of the trapped electrons will be gradually released with the time under the condition of air and with no bias. The possible physical charging mechanism of the interface traps is discussed on the basis of the experimental findings.

First Principles Study of the Stability and Diffusion Mechanism of a Carbon Vacancy in the Vicinity of a SiO2/4H–SiC Interface

The carbon vacancy in bulk 4H‐SiC and in the vicinity of an SiO2/(0001)‐4H‐SiC interface using density‐functional theory is studied. It is found that the migration is hindered in the immediate vicinity of the interface, with the energy barrier for diffusion being ≈15% greater than the same defect in bulk 4H‐SiC. Herein, it is shown that the increased barrier is a consequence of the stabilization of the vacancy in the immediate interface due to a combination of strengthened reconstructions and interfacial relaxation, coupled with the destabilization of the transition‐state structure.

The Correlation between the Reduction of Interface State Density at the SiO<sub>2</sub>/SiC Interface and the NO Post-Oxide-Annealing Conditions

We fabricated SiO2/4H-SiC (0001) MOS capacitors with oxidation temperature at 1350°C, followed by post-oxide-annealing (POA) in NO simply by the control of POA temperatures and times. A correlation between the reduction of interface state density and the increasing of N concentration at the interface has been indicated by C-ψs measurement and secondary ion mass spectrometry (SIMS). The SiO2/4H-SiC interface density decreased when POA temperature was elevated, and the sample annealed at 1300°C for 30min showed the lowest interface state density about 1.5×1012 cm-2eV-1 at Ec-E=0.3 eV when the N concentration is 11.5×1020 cm-3. Meanwhile, the SiO2 /4H-SiC interface annealed at 1200°C for 120min showed the highest N concentration at the 4H-SiC/SiO2 interface is 12.5×1020 cm-3, whereas the interface state density is 2.5×1012 cm-2eV-1 at Ec-E=0.3 eV higher than 1300°C for 30min. The results suggested that higher temperature POA might be much more efficiency in decreased the 4H-SiC MOS interface density with increasing the N area concentration.

Detection and Cryogenic Characterization of Defects at the SiO2/4H-SiC Interface in Trench MOSFET

We employed the thermal dielectric relaxation current (TDRC) method for the detection and cryogenic characterization of traps at the 4H-SiC/SiO2 interface in n-channel trench MOSFETs and n-MOS trench capacitors. The interface of trench devices on the ( $\textsf {11}\overline {2}\textsf {0}$ )-plane atomically differs from the interface of standard lateral devices [(0001)-plane]. In the MOSFET, two TDRC signal peaks originating from electron traps were found and characterized by parameter variation in TDRC measurements. One peak corresponds to interface states located 0.13 eV below the 4H-SiC conduction band edge EC. The other one is attributed to the near-interface traps (NITs) with an electron emission barrier of 0.3 eV. The NIT peak shows an inverse dependence on the discharging voltage compared to regular interface states. In contrast to the MOSFET, only NITs were measured in n-type MOS capacitors. The results found in trench devices were also confirmed for lateral devices. Therefore, we show that the study of SiC MOS capacitors is not sufficient for the understanding of degradation mechanisms in SiC MOSFETs. The interface states at EC-0.13 eV detected in MOSFETs are assumed to contribute to the degradation of the apparent channel mobility and ON-resistance of SiC MOSFETs. These states are strongly reduced by annealing in NO compared to N2.

Fermi level unpinning of metal/p-type 4H-SiC interface by combination of sacrificial oxidation and hydrogen plasma treatment

An ideal metal/p-type 4H-SiC interface with a “free-pinned” Fermi level has been achieved by the combination of sacrificial thermal oxidation (SO) and hydrogen plasma treatment (HPT) on the SiC surface. It is found that the Fermi level pinning could be attributed to the contaminants and defects of the p-type 4H-SiC surface. According to the X ray photoelectron spectroscopy and deep-level transient spectroscopy results, the oxygen and carbon contaminants decreased after SO. However, high-density carbon interstitial-related defects were generated close to the valance band during oxidation. With the subsequent HPT, the chemical residues and detrimental carbon-induced defects were eliminated by the reaction with hydrogen atoms. The p-type 4H-SiC surface was chemically and electrically well saturated with the surface Fermi level position close to the bulk position. An analytical model for the elimination of surface contaminants and defects was proposed to reveal the underlying mechanism of Fermi level depinning.